Historical background of microelectronicsjaco.ec.t.kanazawa-u.ac.jp/edu/micro1/pdf/1.1.pdf · Technology node • Feature size or technology node is represented by 1/2 pitch or hp

1.1 Technology trends

Historical background ofmicroelectronics

2

1.1.1 Origin of LSI

3

Patent of J. Kilby (1959)

US PatentNo. 2 138 743, 1964

Jack S. Kilby, Texas Instruments Inc.,2000 Nobel Prize winnerSource: TI Inc.

4

Patent of R. Noyce (1959)

US PatentNo. 2 981 877, 1961

Robert Noyce, Fairchild Semiconductor International, Inc.Source: Innopedia

5

Year Innovation Inventor1959 Patent application of Solid State Circuit TI, J. Kilby (Registration: 1964)

Patent application of Unitary Circuit Fairchild Semiconductor International, R. Noyce (Registration: 1961)

1961 IC (Integrated Circuit) made in Japan Mitsubishi Electric Corporation (Renesas Electronics Corporation)

1962 Start of mass production of logic family Fairchild, TI

1965 IC calculator Sharp Corporation

Moore's Law Gordon Moore (Intel Corporation)

1970 Chipset of MP944 Garrett AiResearch Corp., American Microsystems, Inc. (Official announcement 1998)

1971 Microprocessor 4004 嶋正利(Busicom corp.), Marcian Edward Hoff Jr., Federico Faggin (Intel Corp.)

1974 Microprocessor TMS1000（US Pat.：3,757,306, 4074351, 1973）

TI, Gary Boone and Michael Cochran (Microcontroller with RAM and IO)

Technological innovations

The world's first microprocessor

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TI TMS10008um p-MOS technology,8,000 transistors,fCLK = 100k-400kHzData 4bit, 43 instructions,256bit RAM, 1kbit ROM

Intel 400410um p-MOS technology,2,250 transistors,fCLK = 500k-740kHzData 4bit, 48 instructions,

Source: National Museum of American History

Source: http://www.4004.com/

Soyrce: http://firstmicroprocessor.com/

Garrett AiResearch MP944p-MOS technology,Data 20bit, fCLK = 375kHz

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1.1.2 Trends of process technology

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Index of integration

• Logic LSI– Number of transistors per chip– Number of gates per chip (based on 2-input NAND

conversion)• Memory

– Number of bits (Not Byte)• Mixed signal LSI (including analog circuits)

– The performance does not depend on the integration, but the figure of merit is defined to compare the circuit performance.

9

1.00E+03

1.00E+04

1.00E+05

1.00E+06

1.00E+07

1.00E+08

1.00E+09

1.00E+10

1970 1975 1980 1985 1990 1995 2000 2005

Year

Tr./C

hip

Moore's low (1965)

Annual growth rate of microprocessors

= 59% = 4times/3years

Source: Intel Corporation

Annual growth rate of DRAM

= 73%=3times/2years

Gordon Moore's Law

Gordon Moore

DRAM

MPU1K

4K

16K

64K

256K

1M

4M

16M

64M

256M512M

1G

PenI

V

PenI

IIPe

nII

PenP

ro

Pent

um

8048

6

8038

6

8028

6

8086

8080

4004 68

00

6800

0 6802

0

6803

0 6804

0Po

wer

PC 6

01

Pow

erPC

604

Pow

erPC

620

Dennard's scaling law (1974)• The reduction of the transistor size leads to

both performance and integration.• The length, width and height are scaled down

as the same ratio k.

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Robert H. Dennard,1968, Inventor of DRAMSource: Wikipedia

Effects of scaling (Theoretical estimation is discussed in Chapter 6.)Integration Speed Power consumption

/TransistorPower consumption /area

Scaling factor k 1/k2 1/k k2 1k = 0.7 2 1.4 0.5 1

Driving force of microfabrication technology

• Dennard's scaling law is a basis of the development in the microfabrication technology.

• Industrial advantages of scaling1. Reduction of the manufacturing cost (material, energy, and

transportation)2. Performance improvement of the LSI3. Reduction of the power consumption of LSI

• Contribution to Sustainable Development Goals (SDGs)1. Compatibility between the performance and manufacturing cost.2. The semiconductor industry is typical knowledge-intensive

industries and have not declined for over 70 years.11

12

Structure of MOSFET (Transistor)

n-Si substrateSiO2

p-Sin-Si n-Si

metal-1

metal-2

metal-3via-2

via-1

contact

Interconnect layersfeature size = hp(M1)

MOSFETfeature size = L or Leff

L

poly-Si gate

2xhp(M1)Leff

hp: half pitch

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Structure of DRAM and Flash memory

word

floating gate

n-Sip-SiSiO2

contact

bit

read

NAND Flash

2xhp(poly)2xhp(M1)

DRAM

bit

VDD

VDD

wordword

bit bit

Scaling of MOSFET (Transistor)

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Scale down of a transistorPOLY

n+/p+

L

W

250nm180nm130nm 90nm 65nm 40nm 28nm 20nm1200nm

600nm 500nm 350nm 14nm

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Technology node• Feature size or technology node is represented by 1/2 pitch or

hp between interconnects.• The technology cycle (rate of the advancing) has been

progressing at 1-step per about 3years.

250 → 180 → 130 → 90 → 65 → 40 → 28 → 20 → 14 (nm)

0.7 0.7Technology node

Metals of interconnect

Minimum Pitch½ pitch½ pitch

Step Step Speed-up

Terminology• Process

– means the manufacturing methods. This term focuses on the type of integrated devices.

• Technology– means the manufacturing methods. This term focuses on the feature

size.

• Examples– "CMOS process" is a fabrication technology to integrate p-ch

MOSFETs and n-ch MOSFETs.– "CMOS 7nm technology" is a CMOS process to microfabricate 7nm

structure.

16

17

10

100

1000

1995 1998 2001 2004 2007 2010 2013 2016 2019

Year

Size

(nm

)Scaling trends

Logic hpDRAM hpGate Length L180nm

130nm100nm

65nm

28nm

20nm

40nm

0.7/3years

0.7/2years0.7/2.5years

ITRS2007, 2011

30MTr./Chip 14nm

7nm transistor is available for mass production.

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1

10

100

1000

10000

2000

2002

2004

2006

2008

2010

2012

2014

2016

2018

2020

2022

Size

(nm

)Comparison in size

Gate Length (Printed)

Gate Length (Physical)

M1 hp (Lithography)

Yeast, Red corpuscles

Bacteria

Virus

Low molecularDye, Saccharide

Nanotechnology

ITRS 2004, 2005

0.7x/3years

Wavelength of visible light

Diesel exhaust particle

COVID-19

0.1

1

10

100

1000

1996 2000 2004 2008 2012 2016 2020

Peak

Tra

nsiti

on fr

eque

ncy

(GH

z)

Year

Cellular

CDMA

WLAN 802.11a

350nm

250nm

180nm

130nm 90nm65nm

45nm32nm 22nm

16nm 11nmCMOSHigh Speed Bipolar

Bipolar

CMOS Amp., Mixer (20dB)

CMOS ADC, Small Digital

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Trends of operating frequency

Analog circuits

RF-LSI (developed by MeRL)

Digital circuits

Frequency 1.7/3years,Area 0.3~0.25/3yesrs

MOSFET

Bipolar transistor

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Trends of logic LSI cost

Cost of high-performance logic LSI having SRAMYear

Tran

sisto

rs p

er c

hip

(M tr

ansis

tors

)

MPU

cos

t (m

icro

cent

s/tra

nsist

or)

2000 2005 2010 2015100

1000

10000

0.1

1

10

100

1000Based on ITRS2002

21Year

DR

AM

Cap

acity

(G b

it)

DR

AM

cos

t (m

icro

cent

s/bi

t)

2000 2005 2010 20150.1

1

10

100

0.01

0.1

1

10

Trends of DRAM cost

64G32G

8G4G

2G

1G

512M

Based on ITRS2002

[参考] 半導体の微細化限界

• 最終的な限界＝技術進歩の必要性に依存

• 物理的限界（材料）、技術的限界（微細加工）、経済合理性(ビジネスとして成り立つかどうか)では限界が決まらない

– 多くの微細化限界説が提唱されたが、その度に新しい解決策も提案されてきた

– 時代は、そこで生活する人々が創るものであり、新しい時代は若者の意思によって生み出されていることを、LSI技術の歴史が示している

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Exothermic density issue

231

10

100

1000

0.11

テクノロジ (um)

発熱

密度

(W

/cm

2)

i38616MHz

i48633MHz

Pentium100MHz

PentiumPro

Pentium IIPentium III 400MHz

Pentium III 1GHzホットプレート

原子炉

The performance of microprocessor is evaluated by power density/operating speed.

The power consumption is proportional to the operating speed(clock frequency).

Multicore processor, Quantum computer

The power density of microprocessors

Hotplate

Nuclear reactor

Pow

er d

ensi

ty (W

/cm

2 )

Technology (m)

1.1.3 Trends of design technology

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Explosive increase in design workload

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10 127Integration

10 persons 1613 persons

Cumulative total number of engineers

20092020

The workload of the LSI design is increasing fourfold with increasing twofold the circuit scale.

1000

104

105

106

107

108

109

1010

10

100

1000

104

105

106

107

108

1980 1985 1990 1995 2000 2005 2010 2015 2020

年

Productivity of LSI design

26

SchematicLogic synthesis

High-level synthesis ？

Feature phoneDVD player

DVD recorderHDTV receiver

Smartphone

Gap of productivity

Inte

grat

ion

(tran

sist

ors/

chip

)

Har

dwar

e pr

oduc

tivity

(man‐m

onth

)So

ftwar

e pr

oduc

tivity

(man‐m

onth

)

Year

EDA (Electronic design automation)

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Schematic

Layout

HDL code

HDL: Hardware Description Language

Logic synthesis

Place & route

Enhancement of productivity

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A high-level abstraction reduces the quantity of the code.

The technology that automatically generates low-level descriptions from high-level abstraction is required to design LSI.

3.7m75cm 7.5cm

Schematic HDL SystemC

The design complexity of 7500M gates requires the 2800 man-month of competent engineers. (It is virtually impossible.)

74000 pages

15000 pages1500 pages

Logic synthesis High-level synthesis

Design verification• Simulator

– Circuit simulator– Logic simulator (HDL simulator)– High level synthesis tool*

• Emulator– A development of SoC (System on a chip)

requires the hardware emulation system which perform a high-speed simulation of the LSI behavior by the hardware accelerator.

– The emulator system provides the virtual transaction from the peripherals.

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7200M gates emulator @Kanazawa University

600M gates emulator @Kanazawa University

* High level synthesis tool = CAD which compile a code written in high-level language into HDL.

1.1.4 Industrial structure

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Industrial structure in the post-Cold War (産業の米)

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Equipment590

Unit: 100M$

Material410

Source: F. Huang, Green IT international symposiumIC Handbook, JEITA, 2009.

Semiconductor

2560

Electronics industry13000

Automotive MedicalSpace

Defense

Internet Contents service５００００

CommunicationBroadcasting

Chemical PowerThe semiconductor production is only 1% od GDP, but tremendously influences all industry.

The market size of the application of semiconductors in Japan is over 40% of GDP.

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Changes in the industrial structure in 1990s

IDM Fabless IP provider Foundry Subcontractor UniversityDesign ○ ○ ○ × × ○

Front-end process ○ × × ○ × ×

Back-end process ○ × × △ ○ ×

Test ○ × × × ○ ○

Own capitalized ○ × × × × ○

OEM supply ○ ○ ○ ○ ○ ×

Own branded products supply ○ ○ × △ △ ×

Integrated Device Manufacturer (IDM) Horizontal international specialization

W company

X company

Y company

Z company

LSI design

IP Core design

Front-end process

Back-end process

Fabless

IP provider

Foundry

ARM, InSilicon

TSMC, UMC, SMIC

ASE, ChipMOS

NOTE: IP (Intellectual Property) is a software and hardware assets which can be embedded into LSI.

Qualcomm, NVIDIA, Xilinx

Subcontractor

D c

ompa

ny

C c

ompa

ny

B c

ompa

ny

A c

ompa

ny

Manufacturing Equipment

Advancement of open innovation

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IDM LSI User

FablessIDM

LSI user

University

ProductsR & D investment

Foundry

After 2010

Players of open innovation

Custom design

Mass production of general-purpose products

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@ Kanazawa Univ.

VDEC is a national academic network by10 universities to provide the CAD software license and LSI manufacturing service.

Hokuriku VDEC sub-center

東大東工大

東北大

北大

金沢大

名大

広大 京大

阪大

九大

VLSI Design and Education Center (VDEC) is established in 1996.

Multi-project chip of VDEC

Hokuriku VDEC subcenter inKanazawa University

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VDEC design room VDEC test room VDEC server room

EmulatorCAD server

LSI testerClean room

Terminals for design practice

要点の日本語解説

• 半導体産業の構造変化– 国際的水平分業によりファブレス（LSI製造の外注）が可能になった

– ユーザを中心とするオープンイノベーションが進行している

– LSIは買ってくるのではなく、自分が必要とする機能を設計し、製造外注することが常識になっている

• 量産からカスタム指向への変化– 2010年以降、LSI設計者は、半導体メーカではなく、各アプリケーシ

ョン領域に分散している

– 新しい技術よりも、「何を作ればよいか」を考えて、付加価値を生み出す考え方が必要

– 今後の技術の全体像を考えるための基礎としてLSI設計を学ぼう

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