High speed serial interfaces challenge embedded systems developers

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High-speed Serial Interfaces Challenge

Embedded Systems Developers

“We Accelerate Growth” November 4th, 2010

Presented by:

Jessy Cavazos

Industry Director

Test & Measurement Group

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Introduction & Objectives

Embedded System Designer/Developer

Test & Measurement(Oscilloscopes, Logic Analyzers,

Protocol Analyzers, etc.)

Industrial PCs

Processors

(Microcontrollers, Microprocessors, ASICs,

DSP, FPGAs)

I/O Circuitry

(ADC and DAC)

Operating Systems

(Commercial, In-House, Open-Source)

Packaged Embedded Systems

Unpackaged Embedded Systems

CustomOff-the-Shelf

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Evolution of Serial Interfaces

Parallel - ~ 1995

Single-lane Serial - ~ 2002

Multi-lane Serial - ~ 2010

Processor Board

I/O Controller

100 MHz

Serial LinesClock

Address

Control

Processor Board

I/O Controller

Protocol #1 Protocol #2

Backplane

TX

RX

TX

RX

Processor Board

I/O Controller

Protocol #1

I/O Controller

I/O Controller

Storage Controller

Protocol #4Protocol #5

Backplane TX

RXProtocol #2

Protocol #3

TX

RX

TX

RX

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Serial Interface Types

Most recent evolution is sRIO

Most recent evolution is sRIO

Chip-to-chip Protocols

Chip-to-chip Protocols

•Chip-to-chip communications

•Characterized by short distance restrictions and lower latency

•Chip-to-chip communications

•Characterized by short distance restrictions and lower latency

Most recent evolution is PCIe,

sRIO

Most recent evolution is PCIe,

sRIO

Board-to-board (Backplane)

Protocols

Board-to-board (Backplane)

Protocols

• “Backplane” protocols

• More complex protocols

• Driven by video, mobile data and computing storage

• “Backplane” protocols

• More complex protocols

• Driven by video, mobile data and computing storage

Most recent evolution is

Ethernet, Fibre Channel

Most recent evolution is

Ethernet, Fibre Channel

Box-to-box (Network) Protocols

Box-to-box (Network) Protocols

•“Network” protocols

•Longer distances connecting major networks

•“Network” protocols

•Longer distances connecting major networks

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Key Challenges with Serial Interfaces

Custom Protocols

Multiple Protocol Domains

Designing for Testability

Signal Integrity Issues

Protocol Compliance and Interoperability

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Test Equipment Challenges

Illustrative Quotes from Research:

“My design has several different protocols. When I debug it, I need to see how they interact.”

“It takes too many tools to do my job. Should I use an oscilloscope, logic analyzer, signal generator, BERT tester or protocol analyzer? I don't have the budget or bench space for all of these and I could spend half my career just trying to learn how to use all of these.”

1-2 Years 3-4 Years 5-6 Years

Challenges

Very High High Medium Low

Impact:

Multiple Tools but Less Time

Single Design but Multiple Protocols

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Testing & Debugging Time

• Test & Debug Time: 23%

• Reducing this time would have a huge impact on time-to-market

Documentation; 2%

Overall System Spec; 15%

Concep-tual

Design; 12%

Detailed Design;

22%Simulation; 8%

Prototyp-ing; 12%

Prep for Production; 6%

Test & Debug 23%

Source: EETimes 2010 Embedded Market Study

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Solutions: Present and Future

Current Solutions Future SolutionsCurrent SolutionsCurrent Solutions Future SolutionsFuture Solutions

• Standard testing and debugging tools: high-speed oscilloscopes, logic analyzers, and protocol analyzers

• Silicon level testingEg: National Instruments

• Mixed protocol analyzerEg: Absolute Analysis’ Investigator

• Standard testing and debugging tools: high-speed oscilloscopes, logic analyzers, and protocol analyzers

• Silicon level testingEg: National Instruments

• Mixed protocol analyzerEg: Absolute Analysis’ Investigator

• Innovative LicensingEg: Tektronix, FuturePlus Systems

• Integrated, multi-function platformEg: Absolute Analysis’ Investigator

• Continued focus on bandwidth and signal integrity requirements

• Innovative LicensingEg: Tektronix, FuturePlus Systems

• Integrated, multi-function platformEg: Absolute Analysis’ Investigator

• Continued focus on bandwidth and signal integrity requirements

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Conclusions

•Problems vary with different serial interfaces•Chip-to-chip•Board-to-board (backplane)•Box-to-box (network)

•Key challenges in serial interface design include •Signal integrity•Protocol compliance and interoperability•Multiple tools needed for testing•Design for testability

•Test solutions must focus on reducing test & debug time for both the present and the future•23% of embedded project time used in test & debug

•Problems vary with different serial interfaces•Chip-to-chip•Board-to-board (backplane)•Box-to-box (network)

•Key challenges in serial interface design include •Signal integrity•Protocol compliance and interoperability•Multiple tools needed for testing•Design for testability

•Test solutions must focus on reducing test & debug time for both the present and the future•23% of embedded project time used in test & debug

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Absolute Analysis

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Absolute Analysis Inc.

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Conventional Test Equipment Discrete Components

– Oscilloscopes– Logic Analyzers– Bit Error Rate Testers (BERT)– Signal Generators– Protocol Analyzers

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Next Generation

Integrated Test Solution

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Connectivity

@ the Chip level

@ the System

level

@ the Board level

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Investigator™ Hardware Architecture

InvestigatorInterface Card

010110101….

011011011….

Encoded Data Stream

ProtocolDatabase

ProtocolDatabase

Editor

Rapid & Easy Customization

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10G & PCI Express NIC Debug

Mixed Protocol

Testing

10G Ethernet

& PCI Express

Time-Correlated Trace View

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Innovation & Expertise

www.AbsoluteAnalysis.com [email protected]

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For Additional Information

Sarah SaatzerCorporate CommunicationsNorth America Corporate CommunicationsFrost & Sullivan(210) [email protected]

Kiran UnniResearch DirectorMeasurement & Instrumentation(210) 247 [email protected]

Jessy CavazosResearch DirectorMeasurement & InstrumentationFrost & Sullivan(210) [email protected]