High-speed Serial Interface Lect. 8 – SERDES 2013-1 High-Speed Circuits and Systems Lab., Yonsei University 1
High-speed Serial Interface
Lect. 8 – SERDES
2013-1High-Speed Circuits and Systems Lab., Yonsei University1
Block diagram
2013-1High-Speed Circuits and Systems Lab., Yonsei University2
Sampler
ClockRecoveryPLL
Channel
Tx Rx
• Where are we today?
RxEqualizer
TxDriverSerializer Deserializer
SERDES• HSI is also called SERDES
– SER for serializer, and DES for deserializer
– Core data rate is much lower than interface• Digital signal processing usually employs parallel architecture.
– HSI requires data-rate converting unit• Serializer: Low-speed parallel data High-speed serial data• Deserializer: High-speed serial data Low-speed parallel data
2013-1High-Speed Circuits and Systems Lab., Yonsei University3
DFF-based Serializer• 4:1
2013-1High-Speed Circuits and Systems Lab., Yonsei University4
D Q D Q D Q D Q
D Q D Q D Q D Q
ParallelData#3
ParallelData#2
ParallelData#1
ParallelData#0
SerialData
ParallelClock
SerialClock
LoadSignal
Sample#3
Sample#2
Sample#1
Sample#0
S3 S2 S1
DFF-based Serializer• 4:1
2013-1High-Speed Circuits and Systems Lab., Yonsei University5
Serial Data
Parallel Clock
Serial Clock
Load Signal
Sample #0
Sample #1
Sample #2
Sample #3
D01
D21
D31
D02
D12
D22
D32
D03
D13
D23
D33
D00
D10
D20
D30
D01 D11 D21 D31 D02 D12 D22 D32 D03 D13D20 D30D10
D11
S1 D11 D21 D31 D12 D22 D32 D13D20 D30
S2 D21 D31 D22 D32
S3 D31 D32
D23
D33
D23
D30 D33
MUX-based Serializer• 4:1
2013-1High-Speed Circuits and Systems Lab., Yonsei University6
D Q
D Q
D Q
D Q
Parallel data #0
Parallel data #1
Parallel data #2
Parallel data #3
SEL0
SEL1
SEL2
SEL3
Serial Data
Parallel CLK #0
Parallel CLK #1
Parallel CLK #2
Parallel CLK #3
SEL0~3
P0
P1
P2
P3
D Q
Serial CLK
MUX-based Serializer• 4:1
2013-1High-Speed Circuits and Systems Lab., Yonsei University7Serial Data
Parallel CLK#3
P0
P1
P2
P3
D02
D22
D32
D03
D13
D23
D33
D04D01
D11
D21
D31
D01 D11 D21 D31 D02 D12 D22 D32 D03 D13D20 D30D10
D12
SEL0
SEL1
SEL2
SEL3
Parallel CLK#2
Parallel CLK#1
Parallel CLK#0
D20
D30
DFF-based Deserializer
• 1:4
2013-1High-Speed Circuits and Systems Lab., Yonsei University8
D Q D Q D Q D Q
D Q D Q D Q D Q
SerialClock
ParallelClock
SerialData
ParallelData#3
ParallelData#2
ParallelData#1
ParallelData#0
S3 S2 S1 S0
DFF-based Deserializer
• 1:4
2013-1High-Speed Circuits and Systems Lab., Yonsei University9
S3
Parallel Clock
Serial Clock
Parallel data #0
Parallel data #1
Parallel data #2
Parallel data #3
D01
D21
D31
D02
D12
D22
D32
D03
D13
D23
D33
D00
D10
D20
D30
D01 D11 D21 D31 D02 D12 D22 D32 D03 D13D20 D30D10
D11
S2
S1
S0
S3 D01 D11 D21 D31 D02 D12 D22 D32 D03 D13D20 D30
D01 D11 D21 D31 D02 D12 D22 D32 D03D20 D30D10
D01 D11 D21 D31 D02 D12 D22 D32D20 D30D10
D01 D11 D21 D31 D02 D12 D22D20 D30D10
D00
D00
D00
MUX-based Deserializer
• 1:4
2013-1High-Speed Circuits and Systems Lab., Yonsei University10
D Q
D Q
D Q
D Q
Parallel data #0
Parallel data #1
Parallel data #2
Parallel data #3
Serial Data
Parallel CLK #0
Parallel CLK #1
Parallel CLK #2
Parallel CLK #3
No selection switchJust parallel-sampled
P0
P1
P2
P3
D Q
Serial CLK
D Q
D Q
D Q
D Q
Parallel CLK #0
S0
MUX-based Deserializer
• 1:4
2013-1High-Speed Circuits and Systems Lab., Yonsei University11
Serial Clock
Parallel data #0
Parallel data #1
Parallel data #2
Parallel data #3
D01
D21
D31
D02
D12
D22
D32
D03
D13
D23
D33
D00
D10
D20
D30
D11
S0 D02 D12 D22 D32 D03 D13 D23D21 D31D11 D33 D04
Parallel CLK#3
Parallel CLK#2
Parallel CLK#1
Parallel CLK#0
D14
P0
P1
P2
P3
D02
D22
D32
D03
D13
D23
D33
D04D01
D11
D21
D31
D12
Symbol alignment• Deserialized data cannot be directly used
– Symbol boundary unknown at Rx– Data need to be re-aligned in the subsequent digital-processing
stage
2013-1High-Speed Circuits and Systems Lab., Yonsei University12
Serial data D02 D12 D22 D32 D03 D13 D23D21 D31D11 D33 D04 D14
Symbol boundary deserializer think
Original symbol boundary
Parallel data #0
Parallel data #1
Parallel data #2
Parallel data #3
D20
D01
D11
D21
D31
D02
D12
D22
D32
D03
D13
D30
Symbol boundary deserializer think
Original symbol boundary
Serializer Design Example (김성근)
Serializer
Serializer structure
Dataalign
Dataalign
Seria-lizer
D1
D2
Dataalign
DataalignD3
D4
Dout
Clock
900
180270
PulseGenerator
Pulse2Pulse1
Pulse3Pulse4
Serializing block
Select signal generator
Data aligning block
Block diagram
Serializer
Serializer structure – Serializing block
Dataalign
Dataalign
Seria-lizer
D1
D2
Dataalign
DataalignD3
D4
Dout
Clock
900
180270
PulseGenerator
Pulse2Pulse1
Pulse3Pulse4
Serializing blockBlock diagram
- MUX structure- Easy way to serialize
Outp
CLK1 CLK2
D1p D2nD1n D2p
Outn
CLK3 CLK4
D3p D4nD3n D4p
MUX structure
Serializer
Serializer structure
Dataalign
Dataalign
Seria-lizer
D1
D2
Dataalign
DataalignD3
D4
Dout
Clock
900
180270
PulseGenerator
Pulse2Pulse1
Pulse3Pulse4
Select signal generator
Block diagram
Serializer
Serializer structure – Select signal generator
CLK1
CLK2
CLK3
CLK4
Serializer
Serializer structure – Select signal generator
A B Out
0 0 0
0 1 0
1 0 0
1 1 1
AB Out
Serializer
Serializer structure
Dataalign
Dataalign
Seria-lizer
D1
D2
Dataalign
DataalignD3
D4
Dout
Clock
900
180270
PulseGenerator
Pulse2Pulse1
Pulse3Pulse4
Data aligning block
Block diagram
Serializer
Serializer structure – Data aligning block
Serializer
Serializer structure – Data aligning block
OutputData
Data1 & CLK1
Data2 & CLK2
Data3 & CLK3
Data4 & CLK4
Serializer
Chip layout
1
2
3
4
1 : Output buffer2 : 4:1 serializer3 : Clock source (PLL)4 : Data input buffer
10Gbps Transmitter
10Gbps 4:1 serializer- 4:1 Mux structure
2.5GHz clock generator- Phase-Locked Loop
Specification
Input : 2.5Gbps x 4 parallel data
200um
480u
m
Output : 10Gbps serial data
Size : 200um x 480um
Power : 125.4 mW Serializer 14.4 mW PLL 9.8 mW Output buffer 23.2 mW Input buffer 78 mW
Serializer
Measurement
Op
D1p D1n
VDD
D2
D3
.
..
On
VDD
bias1
bias2
.
..
D4GND
bias3
Measurement setup
Operating data-rate : 10Gbps output with 2.5Gbps input
4 parallel input : 1 AC signal and 3 DC signal for probing
Serializer
Measurement
1011100110011011100
Serializer operation verification
D1 : 100100100D2 : 111111111D3 : 111111111D4 : 000000000
①
③②
④Out : …111001100110…
Serializer output eye quality
10Gbps eye-diagram with 2.5Gbps input data
DC current consumption : 120mA