SS SS SS SS L L L Semiconductor System Lab Semiconductor System Lab Semiconductor System Lab Semiconductor System Lab Seong-Jun Song 1 MS Thesis Design and Implementation of High-Speed CMOS Clock and Data Recovery Circuit for Optical Interconnection Applications Seong-Jun Song Dec. 20, 2002 Semiconductor System Laboratory, Department of Electrical Engineering and Computer Science, Korea Advanced Institute of Science and Technology (KAIST)
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High-Speed CMOS Clock and Data Recovery Circuit for ...
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SSSSSSSS LLLLSemiconductor System LabSemiconductor System LabSemiconductor System LabSemiconductor System Lab
Seong-Jun Song 1
MS Thesis
Design and Implementation ofHigh-Speed CMOS Clock and Data Recovery
Circuit for Optical Interconnection Applications
Seong-Jun Song
Dec. 20, 2002Semiconductor System Laboratory,
Department of Electrical Engineering and Computer Science,Korea Advanced Institute of Science and Technology (KAIST)
Seong-Jun Song 2SSSSSSSS LLLLSemiconductor System LabSemiconductor System LabSemiconductor System LabSemiconductor System Lab
Outline
! Introduction! Motivation! Problem Definition! Proposed 1/8-Rate CDR! Building Blocks! Measurement Results! Conclusion & Further Works
Seong-Jun Song 3SSSSSSSS LLLLSemiconductor System LabSemiconductor System LabSemiconductor System LabSemiconductor System Lab
IntroductionOptical Input Data Noise Corrupted Data Boosted Data
Recovered ClockRetimed DataRecovered Clock
PreAmp
PostAmp
DecisionCircuit
ClockRecovery
Circuit
Freq.Divider
1:4DEMUX
NetworkInterfaceFramer
AGC*
* AGC : Automatic Gain Control
Seong-Jun Song 4SSSSSSSS LLLLSemiconductor System LabSemiconductor System LabSemiconductor System LabSemiconductor System Lab
Motivation
III-V, Si Bipolar, SiGe HBT
☺ Very high-speed☺ Inherently low noise# High cost# High power consumption# Not compatible with
other technologies
☺ Low cost☺ High level of integration☺ Low power consumption# Less speed# High noise
CMOS
Long-Haul Applications(SONET, Gigabit Ethernet)
Short-Haul Applications(Backplane, Chip-to-Chip)
The Solution is Novel CDR Architecture and Circuit Techniques
In CMOS !!!
Seong-Jun Song 5SSSSSSSS LLLLSemiconductor System LabSemiconductor System LabSemiconductor System LabSemiconductor System Lab
Outline
! Introduction! Motivation! Problem Definition! Proposed 1/8-Rate CDR! Building Blocks! Measurement Results! Conclusion & Further Works
Seong-Jun Song 6SSSSSSSS LLLLSemiconductor System LabSemiconductor System LabSemiconductor System LabSemiconductor System Lab
Generic CDR Configuration
PreAmp
PostAmp
DecisionCircuit
ClockRecovery
CircuitFreq.
Divider
1:4DEMUX
NetworkInterfaceFramer
AGC
PhaseDetectorPhase
DetectorLoopFilter
LoopFilter VCOVCOEdge
DetectorEdge
Detector
Clock and Data Recovery (CDR)
PLL-Based Clock Recovery Circuit
Seong-Jun Song 7SSSSSSSS LLLLSemiconductor System LabSemiconductor System LabSemiconductor System LabSemiconductor System Lab
Performance Limitation of 0.25-µµµµm CMOS *Max. Performance ≅≅≅≅ 2GHz (2-Gb/s)
Delay Delay Delay
! Simulation result for 0.25-µµµµm CMOS differential ring oscillators with resistive loads and isolation buffers
Simple VCO3 4 5 6 7
0.8
1.2
1.6
2.0
2.4
M
ax. O
scill
atio
n Fr
eque
ncy
(GH
z)
A Number of Delay Stages* M. Fukaishi, et al., JSSC, Dec. 1998
Seong-Jun Song 8SSSSSSSS LLLLSemiconductor System LabSemiconductor System LabSemiconductor System LabSemiconductor System Lab
Substrate Noise Effect of VCO
Substrate noise voltage
* M. van Heijningen, et al., JSSC, Aug. 2002
VCO
PreAmp
PostAmp
CDR 1:4DEMUX
Si Substrate
Noise-SensitiveAnalog Blocks
VCOSwitching Noise
f ∝∝∝∝ *
Seong-Jun Song 9SSSSSSSS LLLLSemiconductor System LabSemiconductor System LabSemiconductor System LabSemiconductor System Lab
Conventional CDR Techniques (1/2)
! Half-Rate Clock Technique **# Half-rate clock frequency (2GHz)# Close to performance limitation# Difficult to design VCO
0 1 2 3 4Data
CK
0 1 2 3 4Data
CK
! Full-Rate Clock Technique *# Full-rate clock frequency (4GHz)# Impossible to design VCO
** M. Rau, et al., JSSC, July 1997
* M. Soyuer, et al., JSSC, Dec. 1993
Seong-Jun Song 10SSSSSSSS LLLLSemiconductor System LabSemiconductor System LabSemiconductor System LabSemiconductor System Lab
Conventional CDR Techniques (2/2)
! Oversampling Technique *☺ Quarter-rate clock frequency (1GHz)☺ Easier to design VCO# Highly clock phase resolution# Quantization jitter# Extra decision logic
0 1 2 3 4Data
CK0
CK1
CK2
* C.-K. Yang, et al., JSSC, May 1998
Seong-Jun Song 11SSSSSSSS LLLLSemiconductor System LabSemiconductor System LabSemiconductor System LabSemiconductor System Lab
Outline
! Introduction! Motivation! Problem Definition! Proposed 1/8-Rate CDR! Building Blocks! Measurement Results! Conclusion & Further Works
Seong-Jun Song 12SSSSSSSS LLLLSemiconductor System LabSemiconductor System LabSemiconductor System LabSemiconductor System Lab
Seong-Jun Song 36SSSSSSSS LLLLSemiconductor System LabSemiconductor System LabSemiconductor System LabSemiconductor System Lab
Normalized Performance Comparison
[1] H. Wang, et al., ISSCC, 1999[2] K. Iravani, et al., CICC, 1998[3] J. E. Rogers, et al., ISSCC, 2002[4] M. Rau, et al., JSSC, July 1997[5] K. Nakamura, et al., SOVC, 1998[6] C.-K. Yang, et al., JSSC, May 1998[7] S.-H. Lee, et al., JSSC, Dec. 2002[8] M.-K.E. Lee, et al., SOVC, 20020 1 2 3 4 5 6 7 8 9 10