High Performance Digital Fractional-N Frequency Synthesizers Michael Perrott Michael Perrott October 16, 2008 Copyright © 2008 by Michael H. Perrott All rights reserved.
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High Performance Digital Fractional-N Frequency Synthesizers
Michael PerrottMichael PerrottOctober 16, 2008
Copyright © 2008 by Michael H. PerrottAll rights reserved.
Why Are Digital Phase-Locked Loops Interesting?
PLLs are needed for a wide range of applications- Communication systems (both wireless and wireline)y ( )- Digital processors (to achieve GHz clocks)
Performance is important- Phase noise can limit wireless transceiver performancePhase noise can limit wireless transceiver performance- Jitter can be a problem for digital processors
The standard analog PLL implementation is problematic in many applications- Analog building blocks on a mostly digital chip pose
design and verification challenges- The cost of implementation is becoming too high …
Can digital phase-locked loops offer excellent performance with a lower
cost of implementation?2
Just Enough PLL Background …Just Enough PLL Background …
What is a Phase-Locked Loop (PLL)?
ref(t)
out(t)
ref(t)
out(t)out(t)
e(t) v(t)
out(t)
e(t) v(t)
e(t) v(t) out(t)ref(t) Analog
Loop FilterPhase
Detect
VCO de BellescizeVCO de BellescizeOnde Electr, 1932
VCO efficiently provides oscillating waveform with i bl fvariable frequency
PLL synchronizes VCO frequency to input reference frequency through feedback
4
q y g- Key block is phase detector
Realized as digital gates that create pulsed signals
Integer-N Frequency Synthesizers
ref(t)
div(t)div(t)
e(t) v(t)
Fout = N Fref
e(t) v(t) out(t)ref(t) Analog
Loop FilterPhase
Detect
VCOVCO
Divider
N
div(t) Sepe and JohnstonUS Patent (1968)
Use digital counter structure to divide VCO frequency- Constraint: must divide by integer values
U PLL t h i f d di id t t
N
5
Use PLL to synchronize reference and divider output
Output frequency is digitally controlled
Fractional-N Frequency Synthesizers
ref(t)
div(t) Wells
Kingsford-SmithUS Patent (1974)
Fout = M.F Fref
div(t)
e(t) v(t)
WellsUS Patent (1984)
e(t) v(t) out(t)ref(t) Analog
Loop FilterPhase
Detect
VCORiley
VCO
Divider
N[k]
div(t)
Nsd[k] Σ−Δ
M d l tM.F
US Patent (1989)JSSC ‘93
[ ]sd[ ]Modulator
M.F
Dither divide value to achieve fractional divide values
6
- PLL loop filter smooths the resulting variations
Very high frequency resolution is achieved
The Issue of Quantization Noise
ref(t)
div(t)
Fout = M.F Fref
div(t)
e(t) v(t)
e(t) v(t) out(t)ref(t) Analog
Loop FilterPhase
Detect
VCOVCO
Divider
N[k]
div(t)
Nsd[k] Σ−Δ
M d l tM.F[ ] Nsd[k]
ModulatorM.F
Σ−Δ Quantization Noise
Limits PLL bandwidth
7
fIncreases linearity requirements of phase detector
Striving for a Better PLL ImplementationStriving for a Better PLL Implementation
Analog Phase Detection
phase errorD Q1
ref(t)
error(t)
D Q
ref(t)
div(t)
reset
1
( )
div(t)
Reg
div(t)error(t)
out(t)ref(t) Analog
Loop FilterPhase
Detect
VCO
Pulse width is formed according to phase difference
VCODividerdiv(t)
g pbetween two signalsAverage of pulsed waveform is applied to VCO input 9
Tradeoffs of Analog Approach
Phase Detector
Characteristic
Phase Detector Signals
f
ref(t)
div(t)
Av
era
ge
of
err
or(
t)
error(t)phase error
A
out(t)Analog
Loop FilterPhase
Detect
VCO
ref(t)
Benefit: average of pulsed output is a continuous, linear
VCODividerdiv(t)
g p p ,function of phase errorIssue: analog loop filter implementation is undesirable 10
Issues with Analog Loop Filter
VoutCharge
Perror(t)
Icp
VoutPump
CintCint
out(t)ref(t) Analog
Loop FilterPhase
Detect
VCO
Charge pump: output resistance mismatch
VCODivider
Charge pump: output resistance, mismatchFilter caps: leakage current, large area
11
Going Digital …
out(t)ref(t) Analog
Loop FilterPhase
Detect
VCODivider
Time out(t)ref(t) Digital
Staszewski et. al.,TCAS II, Nov 2003
-to-
Digital
g
Loop Filter
DCODivider
Digital loop filter: compact area, insensitive to leakageChallenges: g- Time-to-Digital Converter (TDC)- Digitally-Controlled Oscillator (DCO)
12
Classical Time-to-Digital Converter
div(t)Delay Delay Delay
div(t) 1
1
Delay
Reg
D Q
Reg
D Q
Reg
D Q
e[k]
e[k]
1
1
0
0
ref(t) ref(t)
Time
-to-
Digital
out(t)ref(t) Digital
Loop Filter
DCODCODividerdiv(t)
Resolution set by a “Single Delay Chain” structurey g y- Phase error is measured with delays and registers
Corresponds to a flash architecture 13
Impact of Limited Resolution and Delay Mismatch
div(t) 1
1
Phase Detector
Characteristic
r
Delay varies due to mismatch
e[k]
1
1
0
0 de
tec
tor
ou
tpu
t
ref(t) phase error
Time
-to-
Digital
out(t)ref(t) Digital
Loop Filter
DCODCODividerdiv(t)
Integer-N PLL- Limit cycles due to limited resolution (unless high ref noise)Limit cycles due to limited resolution (unless high ref noise)
Fractional-N PLL- Fractional spurs due to non-linearity from delay mismatch 14
Examine Noise Performance: Narrow-Bandwidth Case
Assumptions: - TDC ΔT= 20psTDC ΔT 20ps- carrier freq.
= 3.6GHz - f f- reference freq.
= 50MHz- PLL BW Total
= 50kHz- 3rd order ΔΣ
Noise
VCO noise dominates performance everywhere …Don’t need very high TDC resolutionΔ−Σ fractional-N quantization noise is not an issue
15
Examine Noise Performance: Wide-Bandwidth Case
Assumptions: - TDC ΔT= 20psTDC ΔT 20ps - carrier freq.
= 3.6GHz - f f- reference freq.
= 50MHz- PLL BW
Total Noise
= 500kHz- 3rd order ΔΣ
Noise dominated by TDC at low frequenciesNoise dominated by ΔΣ fractional-N noise at high frequencies
16
To Meet High Performance Applications like GSM….
Assumptions: - TDC ΔT = 6psTDC ΔT 6ps- carrier freq.
= 3.6GHz - f f- reference freq.
= 50MHz- PLL BW Total
= 500kHz- 3rd order ΔΣ
(20dB lower)
Noise
N d 6 TDC l ti d 20dB ll ti f Δ Σ
(20dB lower)
Need 6-ps TDC resolution and 20dB cancellation of Δ−Σfractional-N noise to achieve 500kHz bandwidth
17
Can We Improve the Effective Resolution ofTime-to-Digital Conversion?
18
Proposed Approach: A Better Time-to-Digital Converter
D
Delay
D D
Delay Delayref(t)
ref(t)
out(t)
Reg
D Q
Reg
D Q
Reg
D Q
( )
out(t)
error[k]out(t)
Gated Ring Oscillator
ref(t)
ref(t)
O ill t
enable(t)S QR
t(t)
ref(t)out(t)
enable(t)
OscillatorWaveform
Logic
out(t)
error[k]Straayer,PerrottUS Patent in progress
19
This is a simplified view- We will need a few slides to properly explain this …
US Patent in progress…
Consider Measurement of the Period of a Signal
Ring OscillatorVdd Input
x[0] x[1] x[2] x[3]
CounterReset
Oscillator
Count
Counter
RegisterInput
Count
O t Out 3 3 4 3Out Out 3 3 4 3
Use digital logic to count number of oscillator cycles during each input periodg p p- Assume that oscillator period is much smaller than that
of the inputNote: output count per period is not consistent
20
Note: output count per period is not consistent- Depends on starting phase of oscillator within a given
measurement period
Examine Quantization Error in Measurements
Ring OscillatorVdd Input
x[0] x[1] x[2] x[3]
CounterReset
Oscillator
Count
Counter
RegisterInput
Count
O Out 3 3 4 3Out Out 3 3 4 3
Quantization error varies according to starting phase of the oscillator within a given measurement periodof the oscillator within a given measurement period- Leads to scrambling of the quantization noise
But there is something rather special about the
21
scrambling action …
A Closer Examination of Quantization Noise
Ring OscillatorVdd Input
x[0] x[1] x[2] x[3]
CounterReset
Oscillator
Count
Counter
RegisterInput
Count
O t Out 3 3 4 3
Errorq[0] q[1] q[2] q[3]
-q[0] -q[1] -q[2] -q[3]
Calculate impact of quantization noise in time:Out Out 3 3 4 3
Take Z-transform:
22Quantization noise is first order noise shaped!
Relating to Phase Error Between Two Signals
Ring OscillatorVdd Input
x[0] x[1] x[2] x[3]
CounterReset
Oscillator
Count
Counter
RegisterInput
Count
O t Out 3 3 4 3
Errorq[0] q[1] q[2] q[3]
-q[0] -q[1] -q[2] -q[3]
Out Out 3 3 4 3
Ref
PLL O t
Time
-to-
Di i l
Ref
PLL Out
Phase Error[0] Phase Error[1]Gap Gap
Digital
PLL Out
Measurement of phase error between two signals
23
Measurement of phase error between two signalsrequires gaps between measurements- What is the implication of such gaps?
The Impact of Non-Consecutive Measurements
Ring OscillatorVdd Input
x[0] x[2]
CounterReset
Oscillator
Count
Counter
RegisterInput
Count
O t Out 3 4
Errorq[0] q[2]
-q[1] -q[3]
Out Out 3 4
Consider measuring input period every other cycle- Analogous to phase measurement between two signalsAnalogous to phase measurement between two signals
Key observation:- Quantization noise is no longer first order noise shaped!
24Is there a way to restore noise shaping?
Proposed GRO TDC StructureProposed GRO TDC Structure
A Gated Ring Oscillator (GRO) TDC
Ring Oscillator
Phase Error[1] Phase Error[2]
div(t)Enable
Osc(t)
ref(t)Enable
CounterReset
Count[k]
ref(t)
Logic
Count[k]
Quant q[1] q[2]
Register
e[k]e[k]
div(t)
3 4
Quant.Error[k]
q[1] q[2]
-q[0] -q[1]
Enable ring oscillator only during measurement intervals- Hold the state of the oscillator between measurements
Quantization error becomes first order noise shaped!Quantization error becomes first order noise shaped!- e[k] = Phase Error[k] + q[k] – q[k-1]- Averaging dramatically improves resolution! 26
Simple gated ring oscillator inverter-based core
Enabled Ring Oscillator Disabled Ring Oscillator
(a) (b)
Gate the oscillator by switchingthe inverter cores to the
Enable
Enable
Delay Element
M4
Von-1
power supply VoiVoi-1
Vo4Vo1
Von
V
Vo5
M3
M2
EnableVo2Vo3 M1
Improve Resolution By Using All Oscillator Phases
Ring Oscillator
Enable
Phase Error[1] Phase Error[2]
div(t)Enable
Osc
ref(t)
Resetref(t)
Logic
Osc.Phases(t)
Counters
Register
Count[k]
e[k]
div(t)
Count[k]
e[k]
e[k] 11 10
Quant.Error[k]
q[1] q[2]
-q[1]-q[0]Helal, Straayer, Wei,
Perrott VLSI 2007e[k] 11 10
Raw resolution is set by inverter delayEffective resolution is dramatically improved by averaging 28
GRO TDC Also Shapes Delay MismatchEnable
Measurement 1
Enable
Measurement 2
Enable
Measurement 3
Enable
Measurement 3
Barrel shifting occurs through delay elements across
Measurement 4
Barrel shifting occurs through delay elements across different measurements- Mismatch between delay elements is first order shaped! 29
First Generation GRO Prototype
15 Stage Gated Ring Oscillator
enable
enable(t)S QR
VariableDelay
enable
Logic error[k]
e ab e
GRO implemented as a custom 0 13 CMOS IC0.13u CMOS ICExternal setup consists of signal source and variable delay
30
- Test issue: variable delay is nonlinear
Measured GRO Results Confirm Noise Shaping
enable
15 Stage Gated Ring Oscillator
enable
enable(t)S QR
VariableDelay
enable
Logic error[k]30
40
Harmonics dueli i f
Input variable
10
20
e (
dB
)
to nonlinearity ofvariable delay
delay signal
-10
0
Am
plit
ud
e
N i h d
310.01 0.1 1 10 100
-30
-20
Frequency (MHz)
Noise shapedquant. noise
Next Generation GRO: Multi-path oscillator concept
Single InputSingle Output
Multiple InputsSingle Output
Use multiple inputs for each delay element instead of oneAllow each stage to optimally begin its transition based on i f ti f th ti GRO h t tinformation from the entire GRO phase state Key design issue is to ensure primary mode of oscillation
32
Multi-path inverter core
Lee, Kim, LeeJSSC 1997JSSC 1997
Mohan, et. al., CICC 2005
Proposed Multi-Path Gated Ring Oscillator TDC
Hsu, Straayer, PerrottISSCC 2008
Oscillation frequency near 2GHz with 47 stages…Reduces effective delay per stage by a factor of 5-6!
ISSCC 2008
y p g yRepresents a factor of 2-3 improvement compared to previous multi-path oscillators
34
Prototype 0.13μm CMOS Multi-Path GRO-TDC
Timing Generation
Enable 47-stageGated Ring Oscillator
Start
Stop
StateRegister
Z1-47
Start
CLK
MeasurementCells
Start
Stop
Enable
1 72 3 4 5 6
OutAdder
CLK
Straayer, Perrott
Two implemented versions:- 8-bit, 500Msps
y ,VLSI 2008
- 11-bit, 100Msps version2-21mW power consumption depending on input duty cycle
Measured noise-shaping of multi-path GRO
-40
65,536 pt. FFT(Hanning window + 20x averaging)
279.2TDC Output after 1MHz LPF
µ
Input of
1.2pspp
70
-60
-50
ctr
al D
en
sit
y
s2/H
z) 279.0
DC
Ou
tpu
tµ
1.2pspp
-90
-80
-70
Po
we
r S
pec
(dB
ps
278.8
Filte
red
TD
µ
Ideal variance of1.2ps
104 105 106 107
Frequency (Hz)
-100 278.6
Time (µµs)
0 40 80 120 160 200
Noise of 80fsrms in 1MHz BW
Ideal variance of
50-Msps quantizer
with 1ps steps
p
(a)(a) (b)
Data collected at 50MspsMore than 20dB of noise-shaping benefit
µ
80fsrms integrated error from 2kHz-1MHzFloor primarily limited by 1/f noise (up to 0.5-1MHz)
36
Can We Reduce Sigma-DeltaQuantization Noise Caused by Divider Dithering?
37
The Nature of the Quantization Noise Problem
PFD LoopFilter
Ref Out
DivN/N+1
M-bit 1-bit
Div
ΔΣFrequency ΔΣ
ModulatorFrequencySelection
OutputSpectrum
QuantizationNoise Spectrum
F
Noise
FrequencySelection
pp
Fout
PLL dynamicsΔΣ
Increasing PLL bandwidth increases impact of ΔΣIncreasing PLL bandwidth increases impact of ΔΣfractional-N noise- Cancellation offers a way out! 38
Previous Analog Quantization Noise Cancellation
Phase error due to ΔΣ is predicted by accumulating ΔΣ quantization errorGain matching between PFD and D/A must be precise
Matching in analog domain limits performance39
Proposed All-digital Quantization Noise Cancellation
Hsu Straayer Perrott
Scale factor determined by simple digital correlation
Hsu, Straayer, PerrottISSCC 2008
Scale factor determined by simple digital correlation Analog non-idealities such as DC offset are completely eliminated 40
Details of Proposed Quantization Noise Cancellation
Correlator out is accumulated and filtered to achieve scale factor- Settling time chosen to be around
10 usSee analog version of this technique in Swaminathan et.al., ISSCC 2007 41
Proposed Digital Wide BW Synthesizer
Gated-ring-oscillator (GRO) TDC achieves low in-band noisenoiseAll-digital quantization noise cancellation achieves low out-of-band noiseDesign goals:Design goals: - 3.6-GHz carrier, 500-kHz bandwidth- <-100dBc/Hz in-band, <-150 dBc/Hz at 20 MHz offset 42
Overall Synthesizer Architecture
Note: Detailed behavioral simulation model available at http://www.cppsim.com
43
Dual-Port LC VCO
Frequency tuning:- Use a small 1X varactor to minimize noise sensitivityUse a small 1X varactor to minimize noise sensitivity- Use another 16X varactor to provide moderate range- Use a four-bit capacitor array to achieve 3.3-4.1 GHz range 44
Digitally-Controlled Oscillator with Passive DAC
1X varactor minimizes noise sensitivitynoise sensitivity16X varactor provides moderate rangeA f bit it
Goals of 10-bit DAC- Monotonic
A four-bit capacitor array covers 3.3-4.1GHz
- Minimal active circuitry and no transistor bias currents- Full-supply output range 45
Operation of 10-bit Passive DAC (Step 1)
5-bit resistor ladder; 5-bit switch-capacitor arrayStep 1: Capacitors Charged- Resistor ladder forms VL = M/32•VDD and VH = (M+1)/32•VDD,
where M ranges from 0 to 31where M ranges from 0 to 31- N unit capacitors charged to VH, and (32-N) unit capacitors
charged to VL 46
Operation of 10-bit Passive DAC (Step 2)
Step 2: Disconnect Capacitors from Resistors, Then pConnect Together- Achieves DAC output with first-order filtering- Bandwidth = 32• C /(2π•Cl d)•50MHzBandwidth 32 Cu/(2π Cload) 50MHz
Determined by capacitor ratioEasily changed by using different Cload 47
Now Let’s Examine Divider …
Issues: - GRO range must span entire reference period during
initial lock-in48
Proposed Divider Structure
Divide value =N0+N1+N2+N3
Resample reference with 4x division frequency- Lowers GRO range to one fourth of the reference period 49
Proposed Divider Structure (cont’d)
Place ΔΣ dithered edge away from GRO edge- Prevents extra jitter due to divide-value dependent delay 50
Dual-Path Loop Filter
Step 1 resetStep 1: resetStep 2: frequency acquisition- Vc(t) variesVc(t) varies- Vf(t) is held at midpoint
Step 3: steady-state lock conditions- Vc(t) is frozen to take quantization noise away- ΔΣ quantization noise cancellation is enabled
51
Fine-Path Loop Filter
Equivalent to an analog lead-lag filter- Set zero (62.5kHz) and first pole (1.1MHz) digitally( ) p ( ) g y- Set second pole (3.1MHz) by capacitor ratio
First-order ΔΣ reduces in-band quantization noise 52
Linearized Model of PLL Under Fine-Tune Operation
1
1 z-1
Accumulator
Gain
first-orderIIR
K1
1-z-1
1-α
1-αz-1K2 Gain
Gain
e[k]T
TDCGain
1Φref[k]
LoopFilter
2 K
DT-CTΦout(t)V
DACGainΔΣ VCO
e[k]T
2π
1
Δtdel
Φref[k]
H(z)2πKv
sT
CT-DT
Φdiv[k]
Φout(t)
z=ej2πfT s=j2πf
V
2B1
divider
Standard lead-lag filter topology but implemented in
1
T
1
Nnom
CT DTdivider
Sta da d ead ag te topo ogy but p e e teddigital domain- Consists of accumulator plus feedforward path
53
Same Technique Poses Problems for Coarse-Tune
DAC thermal noise impacts pperformance due to the higher coarse VCO gain- Can we somehow lowerCan we somehow lower
the DAC bandwidth?
54
Fix: Leverage the Divider as a Signal Path
Bypass to divider for feed-forward path allows coarseforward path allows coarse DAC bandwidth to be dramatically reduced!
55
Linearized Model of PLL Under Coarse-Tune Operation
e[k]T
2
TDCGain
1
Δt
Φref[k]2πKvc
T
DT-CTΦout(t)V
2B
DACGain
1
1 1
Accum. VCO
1
644
1-α
1 z-1
first-orderIIR
2π Δtdel s
1
CT-DT
Φdiv[k] s=j2πf
2B1-z-1 64
Kz-1
2
Divider
1-αz-1
1
T
1
Nnom
Kc 1-z-1
z2π
Routing of signal path into Sigma-Delta controlling the divider yields a feedforward path
nom
y- Adds to accumulator path as both signals pass back
through the divider- Allows reduction of coarse DAC bandwidthAllows reduction of coarse DAC bandwidth
Noise impact of coarse DAC on VCO is substantially lowered
56
Die Photo
0.13-μm CMOSActive area: 0.95 mm2Active area: 0.95 mmChip area: 1.96 mm2
VDD: 1.5VCurrent: - 26mA (Core)- 7mA (VCO output ( p
buffer at 1.1V)
GRO-TDC:GRO-TDC:- 2.3mA- 157X252 um2
57
Power Distribution of Prototype IC
DACDivider
1.4mW
GRO-TDC
Ref. Buffer
3.4mW(7%)
3.0mW
2.8mW
(7%)
(6%) (3%)
21.0mW (46%)
Digital
VCO 6.8mW (15%)
(7%)
7.7mW (17%)
g
Notice GRO and digital quantization noise
VCO Pad Buffer
Total Power: 46.1mW
Notice GRO and digital quantization noise cancellation have only minor impact on power (and area)
58
Measured Phase Noise at 3.67GHz
Suppresses quantization qnoise by more than 15 dB15 dBAchieves 204 fs (0 27 degree)(0.27 degree) integrated noise (jitter)Reference spur: -65dBc
59
Calculation of Phase Noise Components
−60
−40 VCO NoiseFinepath ΣΔ Quantization NoiseFine−tune DAC Thermal
−80
−60 Fine−tune DAC ThermalCoarse−tune DAC ThermalDivider Noise (1% left)GRO NoiseRef NoiseClose−loop Noise
−120
−100
dBc/
Hz
Close−loop Noise
−160
−140
103
104
105
106
107
−180
−160
foffset
offset
See wideband digital synthesizer tutorial available at http://www.cppsim.com 60
Measured Worst Spurs over Fifty Channels
55
-50 Integer boundary(50MHz•73)
-60
-55r(
dBc)
(50MHz 73)
-70
-65
Spur
16 2-75
3.62 3.63 3.64 3.65 3.66 3.67
16.2us
frequency (GHz)Tested from 3.620 GHz to 3.670 GHz at intervals of 1 MHz- Worst spurs observed close to integer-N boundaryWorst spurs observed close to integer N boundary
(multiples of 50 MHz)-42dBc worst spur observed at 400kHz offset from boundary
61
Conclusions
Digital Phase-Locked Loops look extremely promising for future applications- Very amenable to future CMOS processes- Excellent performance can be achieved
A low-noise, wide-bandwidth digital ΔΣ fractional-N frequency synthesizer is achieved with- High performance noise shaping GRO TDC- High performance noise-shaping GRO TDC- Quantization noise cancellation in digital domain
Key result: < 250 fs integrated noise with 500 kHz bandwidth
Innovation of future digital PLLs will involve joint circuit/algorithm development
62
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