HIGH PERFORMANCE CMOS WITH METAL INDUCED LATERAL CRYSTALLIZATION OF AMORPHOUS SILICON A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING AND THE COMMITTEE ON GRADUATE STUDIES OF STANFORD UNIVERSITY IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY Amol Ramesh Joshi March 2003
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HIGH PERFORMANCE CMOS WITHMETAL INDUCED LATERAL CRYSTALLIZATION
Figure 3.1: Molar free energy of a mixture of Ni and Si. Ni has a lowerfree energy at the NiSi2/α-Si interface while Si has a lowerfree energy at the NiSi2/c-Si interface. Source: Derivedfrom Fig. 14 in Hayzeldenet al.[51].
3.1 : Introduction 25
[111][100] [110]
α−Si
NiSi Precipitates2
Figure 3.2: Schematic diagram showing NiSi2 precipitate orientationsfavorable (〈110〉) and unfavorable (〈100〉, 〈111〉) for MILC.The〈100〉 and〈111〉 oriented precipitates have normalswhich will intersect either the top or bottom surface.Source: Derived from Fig. 12 in Hayzeldenet al.[51].
Hayzeldenet al.[51] showed that octahedral NiSi2 precipitates form after Ni implanta-
tion in α-Si film and annealing at 400C for 3 hours. Upon further annealing at 500C,
c-Si nucleates on one or more faces of the octahedral NiSi2. Migration of these NiSi2 pre-
cipitates leads to growth of needles of c-Si which are parallel to〈111〉 directions. Fig. 3.2
shows NiSi2 precipitates oriented in〈100〉, 〈110〉 and〈111〉 in anα-Si film bounded only
by upper and lower surfaces. The shaded area in each represents the face on which MILC
starts and the arrow indicates the normal to the face which is also the direction along which
crystal growth takes place. So it can be seen that for the〈100〉 and 〈111〉 oriented pre-
cipitates, all of the face normals are such that crystal growth which starts on them will be
stopped soon because of either the upper or lower surface of the film. However, the〈110〉
oriented precipitate will have a better chance of causing extensive c-Si growth because four
of the111 planes exhibit normals within the plane of film.
The observations by Hayzeldenet al.[51] showed that c-Si needles often fan out with
26 Chapter 3 : A Model for Crystal Growth during MILC
a consequent reduction in NiSi2 thickness and increase in growth velocity. They showed
that the growth velocity is inversely proportional to the NiSi2 thickness which agrees with
diffusion limited growth. However, observations by Jinet al.[58] showed that the MILC
rate decreases with time which apparently does not match with diffusion-limited growth.
In this chapter we present a model to predict MILC crystal growth as a function of time. It
also reconciles the two observations by Hayzeldenet al.and Jinet al.
For 3-D integrated circuits where the thermal budget and maximum process temperature
are constrained to keep underlying interconnects and devices intact, this model will be
helpful in choosing a proper annealing temperature and time. If the maximum length of
transistors to be fabricated is known, the crystallization length need not exceed that length
and the time required for MILC can be calculated with the model.
In a typical MILC process used for making TFTs,α-Si is deposited on SiO2 surface
and covered with SiO2 deposited at a low temperature. After gate electrode deposition and
definition, a low temperature oxide is deposited as an interlayer dielectric. Contact holes
are opened over the source/drain and Ni is deposited. Upon annealing at a temperature
close to 400C, NiSi2 forms in the contact holes. Ni induced crystallization occurs when
theα-Si film is annealed at 500C as part of the original NiSi2 moves towardα-Si in the
channel leaving behind a trail of c-Si. While the NiSi2 front moves intoα-Si, about 0.02
atomic % Ni is left behind in the crystallized silicon [59].
3.2 Relation between MILC Growth Rate and NiSi2
Thinning Rate
The shape of crystals observed by Hayzeldenet al.[51] and Jinet al.[58] is needle-like.
Hayzeldenet al. made observations on isolated crystals of Si obtained with MILC where
3.2 : Relation between MILC Growth Rate and NiSi2 Thinning Rate 27
X
Y
Line of Ni
Needle−like Crystals
MILC Front
Figure 3.3: Illustration of MILC starting from a long line of Ni.
the growth can be essentially considered 1-D. In samples considered by Jinet al., when
MILC starts from a Ni covered region, Ni will go downward as well as sideways. Since
the sample is a thin film ofα-Si, we can ignore the downward movement of Ni. That
leaves us two dimensions to consider in the plane of the film. The lateral growth starts
out from a line of Ni with many needle-like crystals growing side by side and continues
uniformly into surroundingα-Si regions. As illustrated in Fig. 3.3 the resultant MILC front
is a straight line parallel to the starting line of Ni. Since there is no variation in the direction
perpendicular to crystal growth, we are again left with the 1-D case.
For simplifying calculations, throughout this model we have assumed that the initial
NiSi2 in the contact holes has been removed after a short anneal at a temperature close to
500 C. This short annealing will move the NiSi2 front away from the contact hole. With
28 Chapter 3 : A Model for Crystal Growth during MILC
The two cases discussed so far can be described by a combined model which takes into
account a certain range ofτ1 values. It can be further expanded toτ1 values not considered
earlier. In the following two subsections we describe each case.
38 Chapter 3 : A Model for Crystal Growth during MILC
3.5.1 Large Values ofτ 1
We start with the same equation (3.36) as before but include a negative constant of integra-
tion. So new expression ofΓ(t) is
Γ(t) =ks0Cα-Si
Nητ1e
−t/τ1 − β (3.49)
The expression for the growth rate will remain as in equation (3.38).β can be rewritten as
β =ks0Cα-Si
Nητ1e
−τ2/τ1 (3.50)
whereτ2 is the time at which the NiSi2 front thickness will go to zero and MILC will stop.
τ2 will depend onτ1 but the value has to be obtained by numerical calculations. In order to
getτ2 numerically, we make the following rearrangement of equations.
At t = ttr, NiSi2 thickness is
Γtr =D∆C
N
(ks0Cα-Si
N
)−1
ettr/τ1 =ks0Cα-Si
Nητ1(e
−ttr/τ1 − e−τ2/τ1) (3.51)
which gives
1− e−(τ2−ttr)/τ1 =D∆C
N
(ks0Cα-Si
N
)−2η
τ1e2ttr/τ1 (3.52)
From the growth rate equation (3.40), we can obtainttr and also simplify equation (3.52)
as
1− e−(τ2−ttr)/τ1 =2(τ0 − ttr)
τ1(3.53)
So
τ2 = ttr − τ1 ln
[1− 2(τ0 − ttr)
τ1
](3.54)
Γ(t) andL(t) = η(Γ0 − Γ(t)) can be obtained fromτ2.
3.5 : Combined Model for MILC Growth Estimation 39
It is easy to see that whenτ1 →∞,
τ2 = ttr − τ1
[−2(τ0 − ttr)
τ1
]= 2τ0 − ttr (3.55)
which agrees with the case of constant surface reaction rate in section 3.4.1. On the other
hand, asτ1 → 2(τ0 − ttr), τ2 → ∞ which agrees with the case of an exponentially de-
creasing surface reaction rate as discussed in section 3.4.2. So both the cases discussed in
section 3.4 are extreme cases of this general case.
3.5.2 Small Values ofτ 1
If τ1 < 2(τ0 − ttr), the earlier discussion does not apply. We have to start with equa-
tion (3.36) and use a positive constant of integration.
Γ(t) =ks0Cα-Si
Nητ1e
−t/τ1 + β (3.56)
Physically,β now represents the final thickness of NiSi2. As a result, not all of the Ni can
be used for MILC and the maximum extent of crystallization is now given by
Lmax = η(Γ0 − β) (3.57)
At t = ttr, the NiSi2 thickness is given by
Γtr =D∆C
N
(ks0Cα-Si
N
)−1
ettr/τ1 =ks0Cα-Si
Nητ1e
−ttr/τ1 + β (3.58)
β =ks0Cα-Si
Nητ1
(D∆C
N
(ks0Cα-Si
N
)−2η
τ1e2ttr/τ1 − 1
)e−ttr/τ1 (3.59)
40 Chapter 3 : A Model for Crystal Growth during MILC
ttr can be obtained from equation (3.40) and equation (3.59) can be simplified to
β =ks0Cα-Si
Nητ1
(2(τ0 − ttr)
τ1− 1
)e−ttr/τ1 (3.60)
Upon calculatingβ, Γ(t) andL(t) can be obtained. Asτ1 → 2(τ0 − ttr), β → 0 which
is same as theτ2 → ∞ case discussed in the section on largeτ1. At the other extreme, as
τ1 → 0, ν → 0, ttr → 0 andβ → Γ0 which means that MILC does not occur at all.
3.6 Results and Discussion
In order to see how the model compares with experimental data, the predictions of our
model in section 3.4 were plotted along with data from Jinet al.[58]. Fig. 3.6 and 3.7 show
the length of the crystallized region and MILC rate respectively at 500C as a function
of time. The transition between diffusion limited and surface reaction limited regimes is
marked by circles. Fig. 3.7 shows a diffusion limited growth regime at smaller times as
observed by Hayzeldenet al.[51]. Unfortunately, they only state that growth rate increases
with time but apart from a mention of 5A/s (1.8µm/hr) average growth rate, no details
of its increase with time were found. It can be noted that rate of 1.8µm/hr is somewhat
higher than our model predicts. This is probably due to a higher value ofη (owing to
lower levels of Ni in c-Si) in the sample. After a period of 10 to 18 hours, growth becomes
surface reaction limited. The differences between the model and experiment may have
arisen because in the experiment by Jinet al.[58], the initial NiSi2 was removed after a
3 hour anneal at 500C. This short anneal may have introduced more Ni into the c-Si region
than assumed by our model. The agreement between experimental data and exponentially
decreasing reaction rate is better than that with constant reaction rate.
3.6 : Results and Discussion 41
0
10
20
30
40
50
60
70
80
0 10 20 30 40 50 60 70 80
MIL
C L
engt
h (µ
m)
Annealing Time (hr)
Data from Jin et al. [58]
Reaction rate is constantReaction rate exponentially decreasing
Figure 3.6: Comparison of model and experimental results for MILClength.
The concept of decreasing reaction rate constant,ks, with time was adopted to con-
sider the reduction in the amount ofα-Si available for reaction with Ni due to competing
processes of nucleation and crystallization. Another factor which may contribute is the re-
duction of driving force due to atomic rearrangement inα-Si after extended annealing [58].
The model was then expanded to consider cases of differentτ1 values. Theτ1 value indi-
cates how fast homogeneous nucleation of theα-Si film is occurring or how fast the driving
force for reaction is decreasing. At any temperature there is a competition between MILC
and SPC. Forτ1 > 2(τ0−ttr), it was shown that the MILC growth will occur until all of the
Ni from the NiSi2 front is consumed. At low temperatures (about 500C or below), homo-
geneous nucleation and crystallization ofα-Si is quite slow and MILC wins against SPC.
So τ1 and the extent of crystallization,Lmax are expected to be large. Ifτ1 < 2(τ0 − ttr),
42 Chapter 3 : A Model for Crystal Growth during MILC
0
0.5
1
1.5
2
0 10 20 30 40 50 60 70 80
MIL
C R
ate
(µm
/hr)
Annealing Time (hr)
Data from Jin et al. [58]
Reaction rate is constant
Reaction rate exponentially decreasing
Data from Jin et al. [58]
Reaction rate is constantReaction rate exponentially decreasing
Regime transition point
Figure 3.7: Comparison of model and experimental results for MILCrate. The transitions between diffusion limited and surfacereaction limited regimes are marked by circles.
MILC growth will stop before all of the Ni from the NiSi2 front is consumed indicating
that SPC is getting faster. This is expected to occur at high temperatures where the ho-
mogeneous nucleation and crystallization ofα-Si is rapid. At very high temperatures,τ1
will go to zero, indicating no MILC growth. The plots in Fig. 3.8 and 3.9 show the re-
sults of numerical calculations at 500C for the combined model for small as well as large
values ofτ1. It can be seen that a reasonable match with MILC growth and MILC rate
data is obtained withτ1 = 41.7 hr. The time constant obtained by extrapolating data in
Kosteret al.[60] is about 694 hours at 500C. The discrepancy arises because the time
dependence we assumed may not be exact. The choice of time dependence found in the lit-
erature [60–62] varies with the method of Si film deposition and later processing. Also, our
3.6 : Results and Discussion 43
0
10
20
30
40
50
60
70
80
0 10 20 30 40 50 60 70 80
MIL
C L
engt
h (µ
m)
Annealing Time (hr)
τ1 = ∞
τ1 = 41.7 hr
τ1 = 27.8 hrτ1 = 13.9 hr
Data from Jin et al. [58]
Large τ1 caseSmall τ1 case
Figure 3.8: Results of numerical calculations of MILC length forcombined model.
simple model does not take into account all factors affecting nucleation and crystallization
processes as well as the presence of impurities.
The model is able to predict the results of MILC growth at 500C when the initial
supply or NiSi2 seed for MILC has been removed. Due to the lack of the data at temper-
atures other than 500C, the model could not be verified for those temperatures. It has
been assumed that the concentration difference∆C in the NiSi2 moving front remains un-
changed during diffusion limited growth and its magnitude is not known. Similarly,Cα-Si
is not known. Based on the data of Ni diffusivity in silicon [63] at 500C we can take
D ≈ 1× 10−11 cm2/s. Then we find∆C = 6.25× 1019/cm3. This excess∆C is small
compared to the amount of Ni in the NiSi2 and may be due to the segregation coefficient
between silicon and NiSi2.
44 Chapter 3 : A Model for Crystal Growth during MILC
0
0.5
1
1.5
2
0 10 20 30 40 50 60 70 80
MIL
C R
ate
(µm
/hr)
Annealing Time (hr)
τ1 = ∞
τ1 = 41.7 hr
τ1 = 27.8 hr
τ1 = 13.9 hr
Data from Jin et al. [58]
Large τ1 caseSmall τ1 case
Regime transition point
Figure 3.9: Results of numerical calculations of MILC growth rate forthe combined model. The transitions between diffusionlimited and surface reaction limited regimes are marked bycircles.
When it comes to predicting MILC rates for the cases where the original Ni source is
not removed, this model faces difficulties explaining the higher observed growth rates [58].
However, we can suggest a qualitative explanation. Since the Ni source also supplies Ni to
the newly formed c-Si, the Ni loss from NiSi2 moving front is expected to be smaller which
will give us a higher value ofη. Another reason may be that due to an additional flux of Ni
from the original Ni source, levels of Ni concentrationCα-Si, Cc-Si, Cback andCfront may all
rise and provide an increased Ni flux for reaction withα-Si.
3.7 : Summary 45
3.7 Summary
We have proposed a comprehensive, physical model for predicting MILC growth as a func-
tion of time with the initial Ni seed removed and compared with experimental data. This
model incorporates competition between MILC and SPC through a time-varying reaction
rate constant.
L(t) obtained from the case of a surface reaction rate decreasing exponentially has a
better match with the experimental data than the constant reaction rate case. As long as
the surface reaction rate is decreasing slowly (largeτ1), MILC will dominate and with the
initial NiSi2 removed, the maximum MILC growth is going to be the same regardless of
the surface reaction rate. However, the time needed to reach the final growth will depend
on surface reaction rate. If the surface reaction rate is decreasing rapidly (smallτ1), as it
is typically at high temperatures due to homogeneous nucleation, MILC does not achieve
its maximum growth. Since the model enables us to find outL(t), the time and the ther-
mal budget for a crystallization anneal can be estimated based on the dimensions of the
transistor to be fabricated.
In the next chapter, we will describe experiments for the study of dopant activation
and crystal growth during the MIC process. Understanding of both of these processes is
important for good quality CMOS devices.
Chapter 4
Crystallization and Dopant Activation
with Metal Induced Crystallization
4.1 Introduction
The presence of grain boundaries in MOS transistor channels can cause the following ef-
fects (a) reduction in on-current, (b) degradation of subthreshold slope, and (c) an increase
in leakage current. All of these are illustrated in fig. 4.1. As the number of grain bound-
aries increased from 0 to 1 or more, the on-current of the device shown in fig. 4.1 reduced
by more than a factor of 10 and the subthreshold slope decreased. Also, for more than 4
grain boundaries, the leakage current increased. For fabricating a good CMOS transistor,
therefore, grain boundaries inside the transistor channel need to be avoided. This means
that the method of crystallization used should yield large grains of Si. Since MILC occurs
at low temperatures there is a possibility that large crystals can be obtained without causing
excess homogeneous nucleation. In this chapter, we are going to study different methods
for starting MILC and see which method is better for eliminating the grain boundaries from
46
4.1 : Introduction 47
Figure 4.1: Effects of grain boundaries on transistor performance.Source: Subramanianet al.[29]
the channel.
Dopant activation is crucial for obtaining high performance transistors. Since series
resistance in transistors is one of the major hurdles in improving drive current, demands
on dopant activation to obtain low sheet resistance and contact resistivity will be more
severe as scaling continues more or less as predicted by ITRS [1]. Conventional thermal
activation of dopant requires high temperatures. Using MIC for dopant activation is one of
the ways to achieve dopant activation at low temperature [52, 64] where it is a byproduct of
crystallization. Here we present a comparison of nickel induced dopant activation and high
temperature activation along with some thought on the mechanism of activation during the
MIC process.
48 Chapter 4 : Crystallization and Dopant Activation with MIC
4.2 Experimental Details
4.2.1 Dopant Activation
For our dopant activation experiments, about 350 nm thickα-Si layers were deposited on
thermally oxidized Si wafers using silane LPCVD at 500C. Some films were implanted
with boron (32 keV, 2×1015 /cm2 + 80 keV, 2×1015 /cm2), some with phosphorus (70 keV,
2× 1015 /cm2 + 160 keV, 3× 1015 /cm2) and others were left undoped. 25 nm thick nickel
was sputter deposited on one film of each kind and annealed at 400C for 4 hours in N2 to
form nickel silicide. After the unreacted nickel was removed by etching in H2SO4+H2O2,
the samples were annealed at 450C for 24 hours in N2 to crystallize theα-Si film and
activate the dopant. Fig. 4.2 shows the schematic cross section of the samples. These
samples were analyzed with the spreading resistance measurement technique as a function
of depth inside the samples. Some wafers without Ni which had the same dopant implants
were annealed in an N2 ambient at 800C for 2 hours. They served as the control samples
for comparison.
4.2.2 TEM Study of Crystal Growth During MILC
Samples for plan view TEM of wide areaα-Si films crystallized with Ni-MILC were pre-
pared in order to study the grain size. 1µm SiO2 was grown on Si wafers and 100 nm thick
α-Si was deposited on it using LPCVD at 500C. After coating the wafers with photore-
sist, long seeding holes were opened photolithographically. 5 nm thick Ni was deposited
and patterned using photoresist liftoff. The wafers were annealed at 500C for 24 hours in
N2+H2 and diced in 3 mm×3 mm pieces. These pieces were immersed in concentrated HF
to dissolve the 1µm thermal oxide. After the oxide etching, portions of the Si films floated
to the surface of the HF. After diluting the HF with large amounts of water, the floating Si
4.2 : Experimental Details 49
α
Thermal SiO
c−Si Substrate
2
−Silicon FilmBefore Annealing
Nickel Layer
Silicon Atom
Dopant Atom
450 C Anneal
2
c−Si Substrate
Thermal SiO
α−Silicon Crystallized
Grains
and Activated with Nickel
Figure 4.2: Schematic of dopant activation experiment.
films were captured with a copper grid for mounting in TEM sample holders for plan-view
observation.
A study of crystal growth during the MILC process in submicron features was per-
formed using the cross-section TEM sample preparation method developed by Choet
al. [65]. Similar to our transistor structure, 1µm SiO2 was grown over Si substrates and
100 nm thickα-Si films were deposited by LPCVD. A layer of low temperature oxide
(LTO) was deposited and seeding holes were opened. 25 nm Ni was deposited and the
wafers were annealed at 400C to form the silicide. After wet etching of unreacted Ni,
100 µm long and 140 nm wide lines were patterned with electron beam lithography be-
tween seeding holes. Using plasma etching, mesas of 0.4µm height were formed in order
to facilitate side-view TEM observation of crystal growth. After mesa formation, samples
were annealed at 500C for 24 hours in N2+H2 to crystallize the lines ofα-Si with MILC.
50 Chapter 4 : Crystallization and Dopant Activation with MIC
4.3 Results and Discussion
4.3.1 Dopant Activation Results with Spreading Resistance Analysis
Dopant activation at 800C without Ni and at 450C with Ni was compared. Fig. 4.3 shows
the resistivity measured by spreading resistance analysis as a function of depth inside the
crystallized poly-Si film. There are seven curves shown in the figure. Three of them are for
phosphorus doped films, three for boron doped films and one for an undoped film. It can
be noticed that for doped samples, the poly-Si resistivities are similar for 800C 2 hour
anneal without Ni and 450C 24 hour anneal with Ni. Samples without Ni show 6 orders
of magnitude higher resistivity than samples with Ni for the same 450C 24 hour anneal.
The Ni-crystallized undoped film also shows 6 orders of magnitude higher resistivity than
Ni-crystallized doped films after 450C 24 hour anneal. This shows that Ni is activating
dopants and the difference between resistivities of Ni-crystallized undoped and doped films
is caused by dopant activation.
The dopant activation during MIC is related to the crystallization process which is simi-
lar to the dopant activation which occurs during pure thermal SPC. We have already seen in
Chapter 3 that MIC occurs as a result of Ni moving towardsα-Si in order to reduce the free
energy and Si atoms fromα-Si attach to the NiSi2 template. While this process is going
on, dopant atoms can get placed on lattice sites and therefore get activated.
4.3.2 TEM Results for MILC
Top-view TEM images of MILC structures for wide areaα-Si are shown in fig. 4.4(a). The
crystal growth started from the bottom part of figure and theα-Si/poly-Si boundary is near
the top. It can be seen that some of the crystals are over 2µm wide but many are narrower
than 1µm. Near the starting point of MILC, the average width of grains was estimated
4.3 : Results and Discussion 51
10-4
10-3
10-2
10-1
100
101
102
103
104
105
106
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
Res
istiv
ity (
Ω-c
m)
Depth Inside Poly-Si Film (µm)
B-doped, no Ni (450°C)P-doped, no Ni (450°C)B-doped, with Ni (450°C)P-doped, with Ni (450°C)B-doped, no Ni (800°C)P-doped, no Ni (800°C)
Undoped, with Ni (450°C)
Figure 4.3: Spreading resistance measurement profiles of the samplesfor dopant activation experiment.
to be 0.6µm by observing changes in selective area diffraction (SAD) patterns. The SAD
of MILC poly-Si andα-Si regions are shown in fig. 4.4(b) and 4.4(c) respectively. The
MILC region is composed of several crystals of different orientation as seen from the SAD
pattern. The amorphous region SAD shows just diffused rings.
Fig. 4.5(a) shows side-view TEM images of a transistor structure with a width of
140 nm. Here the MILC was initiated from a region of size 2µm×2 µm, surrounding
the seeding hole and continued in the 140 nm wideα-Si line. Unlike the wide area TEM
images mentioned above, the MILC in 140 nm wideα-Si line produces a single crystal.
A SAD pattern of the MILC region is shown in fig. 4.5(b). The dots in the SAD image
confirm that the MILC region is a single crystal. The diffused rings in the SAD result from
the SiO2 underneath which is amorphous. The TEM also indicates that the single crystal Si
52 Chapter 4 : Crystallization and Dopant Activation with MIC
obtained from the MILC has many defects and is not as good as bulk-Si crystal. Along the
length of the structure, the crystal orientation changed every few microns but the silicon
remained single crystal. The length of each single crystal region is well over 1µm and it is
not possible to capture it in one TEM photograph. Silicon far away from the seeding point
stayed amorphous after the 500C 24 hour anneal. Fig. 4.5(c) shows the boundary between
the MILC and amorphous regions which is several tens ofµm away from the starting point
of MILC.
Our observations agree with TEM observations of MILC in submicron lines by Guet
al. [66]. They observed that a single crystal results for MILC for linewidths between 50 nm
and 200 nm but at higher widths competitive grain growth can occur in the beginning
of lateral crystallization. The difference between MILC for wide and narrow regions is
schematically shown in fig 4.6. If the region to be crystallized is wide, multiple grains can
grow side by side leaving one or more grain boundaries in the region. In narrow regions,
there is a higher probability that only one of those grains will grow and occupy the entire
channel region. Therefore, it is desirable to use narrow devices.
It is seen from TEMs that crystals grown with MILC in 140 nm lines are larger than the
CMOS transistors withWdrawn = L = 0.1µm. So these transistors should essentially be in
single crystal Si and should have high performance.
4.3 : Results and Discussion 53
(a)
(b) (c)
Figure 4.4: (a) Plan view TEM of MILC region; (b) selective areadiffraction pattern of MILC poly-Si; and (c) selective areadiffraction pattern ofα-Si.
54 Chapter 4 : Crystallization and Dopant Activation with MIC
(a)
(b)
(c)
Figure 4.5: (a) TEM of transistor structure; (b) selective area diffractionpattern; and (c) boundary ofα-Si and crystallized Si.
4.4 : Summary 55
Seeding Hole
Narrow Channel
Wide Channel
Grain Boundary
Figure 4.6: Illustration of MILC growth in wide and narrow channelregions.
4.4 Summary
In this chapter, we saw how crystallization and dopant activation take place when MIC is
used. TEM studies show that MILC in wide area yields a poly-Si film with lots of grain
boundaries but in narrow structures (140 nm) it yields single crystals well over aµm in
length. These are long enough to contain a single MOS transistor.
Dopant activation with nickel at 450C for 24 hours was found to be comparable to
thermal activation without nickel at 800C for 2 hours. This activation is good for the
source/drain and gate electrode during low temperature fabrication of CMOS. The mecha-
nism of dopant activation can be related to rearrangement of Si and dopant atoms as they
56 Chapter 4 : Crystallization and Dopant Activation with MIC
attach to the template left behind by NiSi2 in silicide-mediated crystal growth driven by
free energy difference between Ni/α-Si and Ni/c-Si. The next chapter will discuss reliabil-
ity issues of MOS capacitors when MIC is used for dopant activation in the gate electrode.
Chapter 5
Nickel Induced Crystallization of α-Si
Gate Electrodes at 500C and MOS
Capacitor Reliability
5.1 Introduction
We have seen in the previous chapter that MIC with Ni can be used to activate dopants.
For a low temperature process, it gives a nice way to activate dopants in gate electrodes or
source/drain regions which would otherwise require high temperatures. This will be helpful
especially for devices in the upper layers of 3-D IC or devices which cannot tolerate high
temperatures due to reliability concerns about new materials such as high-κ gate dielectric.
Ni is a fast diffuser [67] and a deep trap [68] in silicon. Therefore, if Ni is used to activate
dopants in gate electrodes, it is important to study the effects of Ni MIC on gate oxide and
overall capacitor reliability. In this chapter, we report details of materials analysis as well
as electrical measurements such as C-V, I-V and QBD for capacitors with and without Ni.
57
58 Chapter 5 : MIC for Gate Electrodes and MOS Capacitor Reliability
5.2 Experimental
PMOS capacitors were fabricated on (100) oriented n-type crystalline Si substrates with a
dopant concentration of 1015/cm3. Standard LOCOS was used for isolation. The gate di-
electric was 10 nm thick SiO2 thermally grown at 1000C in an ambient of 70% O2+30% N2.
Immediately after oxide growth,in-situ phosphorus dopedα-Si was deposited at 550C
by LPCVD. The thickness of theα-Si layer was 150 nm and the dopant was not activated.
The gateα-Si was patterned using plasma etching. LTO was deposited by LPCVD over the
patterned gate electrodes and spacers were formed on the sidewalls using anisotropic SiO2
plasma etching.
On an experimental wafer A, a 5 nm thick Ni layer was deposited and the samples were
annealed in N2+H2 at 400C for 4 hours to form silicide over theα-Si gate electrode.
No silicide was formed on the sidewalls because they were protected by SiO2 spacers.
Unreacted Ni was etched in a mixture of H2SO4+H2O2. Crystallization anneal conditions
for wafer A and control wafers B and C are shown in Table 5.1. A schematic cross section
of a capacitor on wafer A is shown in Fig. 5.1. Capacitor structures for wafers B and C
were similar but they did not have any Ni. Capacitors of size 100µm×100µm were used
for all electrical measurements except for Zerbst plots.
5.3 Results and Discussion
5.3.1 SIMS and Spreading Resistance Analysis
Since Ni is a midband trap in Si, any Ni going through the gate oxide into the channel
region will degrade the performance of devices. Therefore, it is important to find out the
amount of Ni in the gate electrode and in the channel. Secondary ion mass spectroscopy
(SIMS) was performed on wafers A, B and C to obtain the concentrations of Ni and P. From
5.3 : Results and Discussion 59
Table 5.1: Annealing conditions for crystallization of the gateα-Si onexperimental and control wafers. Wafers B and C do nothave any silicide.
Crystallization AnnealWafer Ni Temperature Time Ambient
(C) (hours)A Yes 500 24 N2+H2
800 2 N2
B No FOLLOWED BY500 24 N2+H2
C No 500 24 N2+H2
Fig. 5.2(a), the concentration of Ni is in excess of 1021/cm3 in the gate electrode for wafer
A near the top and bottom surfaces of the poly-Si. This high concentration of Ni at the
interface of poly-Si and oxide comes from the NiSi2 front moving inα-Si during MIC [33]
and stopping upon reaching the gate oxide. The SIMS analysis was again performed on
wafer A after removing the poly-Si gate electrode and the gate oxide. The SIMS profile
in Fig. 5.2(b) shows only a very small amount of Ni in the substrate which is not different
from the background level for Ni during SIMS measurements. The profile in Fig. 5.2(b)
resulted from the surface Ni which got redeposited from the etching chemicals. In order
to obtain a more reliable result, one of the samples was polished from the backside and
thinned down to 2 micron. Then a Ni profile was obtained with SIMS starting from the
back surface. No distinguishable Ni signal was found.
From the SIMS profile in Fig. 5.2(a), the concentration of P in the gate electrode is
approximately 1021/cm3 for all wafers. In order to find out the active dopant concentration,
resistivity profiles for wafers A, B and C were obtained by spreading resistance measure-
ments. The resistivity as a function of depth in the gate electrodes is plotted in Fig. 5.3. It
60 Chapter 5 : MIC for Gate Electrodes and MOS Capacitor Reliability
Amorphous Silicon GateSiO Spacer2(n−type)
Thermal SiO 2
Ni
Crystallization Anneal
Gate Electrode Crystallized
10 nm
c−Si Substrate(n−type)
using Nickel MIC
and Ni Wet Etch
500 C 24 hour
Figure 5.1: Schematic cross section of MIC capacitor.
can be seen that the dopant on wafer C did not get activated with a 500C 24 hour anneal in
the absence of Ni. Therefore, it was excluded from further electrical measurements. On the
other hand, the active dopant concentration obtained from spreading resistance on wafers
A and B is approximately 1020/cm3 (10%) and 5× 1019/cm3 (5%), respectively.
5.3 : Results and Discussion 61
1018
1019
1020
1021
1022
0 20 40 60 80 100 120 140
Con
cent
ratio
n (a
tom
s/cm
3 )
Depth In Poly-Si Gate Electrode (nm)
Ni profile: Wafer A (Ni)
P profile: Wafer A (Ni)
P profile: Wafer B (no Ni, 800°C)
P profile: Wafer C (no Ni, 500°C)
Poly-Si/SiO2 Interface →
(a)
1016
1017
1018
0 5 10 15 20 25 30 35 40
Con
cent
ratio
n (a
tom
s/cm
3 )
Depth In Substrate (nm)
Ni profile in substrate: Wafer A (Ni)
← SiO2/Si Interface
(b)
Figure 5.2: SIMS profiles: (a) Ni and P in the gate stack; and (b) Ni inthe substrate.
62 Chapter 5 : MIC for Gate Electrodes and MOS Capacitor Reliability
10-4
10-3
10-2
10-1
100
101
102
103
104
0 20 40 60 80 100 120 140
Res
istiv
ity (
Ω-c
m)
Depth In Poly-Si Gate Electrode (nm)
Wafer A (Ni)Wafer B (no Ni, 800°C)Wafer C (no Ni, 500°C)
Poly-Si/SiO2 Interface →
Figure 5.3: Spreading resistance profiles in the gate stack.
5.3.2 TEM Studies
The cross section transmission electron micrographs of the gate stack for wafers A and B
are shown in Fig. 5.4(a) and 5.4(b), respectively. It can be seen that wafer B has colum-
nar grains in the poly-Si with a grain size close to 0.15µm. The grains on wafer A are
somewhat smaller and are not columnar. They appear to be split in different layers. Energy
dispersive spectroscopy (EDS) analysis on the wafer A poly-Si cross section showed about
30 atomic % Ni near the top of the film and also at the interface of the poly-Si and gate
oxide which suggests NiSi2 at these locations. The top NiSi2 is formed after a 400C sili-
cidation anneal and the interface NiSi2 is a result of MIC. Unlike SIMS, the EDS analysis
did not show any Ni in the middle of the poly-Si film or in the substrate.
The discrepancy between the SIMS results and EDS observations can be explained as
5.3 : Results and Discussion 63
follows. EDS is a local measurement and is helpful in finding out the Ni concentration
in small areas, for example, near the interface of the poly-Si and the gate oxide. The
measurement obtained with EDS has an accuracy of about 1 atomic % which is worse than
that of SIMS. During the SIMS analysis which starts from the top surface of the poly-Si,
the Ni present at the top surface gets pushed inside due to collisions with the incident ion
beam. This results in a higher than actual value at the center of the poly-Si film. In other
words, the Ni profile obtained with SIMS is smeared out.
5.3.3 C-V Measurements
C-V plots for 100µm×100µm size capacitors on wafers A and B were obtained at low
frequency (quasi-static) with a ramp rate of 0.05 V/s and also at a high frequency (10 kHz).
The results are shown in Fig. 5.5(a) and 5.5(b), respectively. Each of the plots represents an
average of measurements performed on 10 identical capacitors. Devices on wafer A show
a positive VFB shift of about 0.1 V which indicates 0.1 eV increase in the gate electrode
workfunction. The VFB shift is not from fixed charge. The fixed charge is positive and
would have caused a negative flat band shift. In our Ni samples, the shift is in the positive
direction. So we are left with the gate electrode workfunction as the cause of flat band
shift. The positive shift of 0.1 V in the VFB is due to a 0.1 eV increase in the gate elec-
trode workfunction. This indicates that theφms and the barrier height for electrons (φb) are
higher by 0.1 eV for the MIC devices. The slope of the C-V curve in the transition region
between accumulation and inversion is lower for wafer A. This degradation of slope is due
to interface traps which are close to 5× 1011/cm2-eV. These traps are probably due to the
lack of a high temperature (800C) anneal.
The change of gate workfunction may be useful for modern short channel devices with
undoped channels which rely on the gate workfunction for adjustment of threshold voltage.
64 Chapter 5 : MIC for Gate Electrodes and MOS Capacitor Reliability
(a)
(b)
Figure 5.4: Cross section TEM of the gate stack: (a) wafer A; and (b)wafer B.
This change is caused by the presence of about 30 atomic % Ni at the gate electrode-oxide