HIGH PERFORMANCE AND LOW POWER SRAM CELL DESIGN …

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Int. J. Elec&Electr.Eng&Telecoms. 2016 Shilpa Saxena and Rajesh Mehra, 2016

HIGH PERFORMANCE AND LOW POWER SRAMCELL DESIGN USING POWER GATING

TECHNIQUEShilpa Saxena1* and Rajesh Mehra2

*Corresponding Author: Shilpa Saxena, [email protected]

In this paper the stable and power-efficient method is presented to design and implement Static-RAM Cell. Static-RAM is one of the essential building block for the VLSI design. Due to theirhigher speed Static-RAM based Cache memories and System-on-chips are commonly used.Due to device scaling there are several design challenges for Static-RAM design in nanometertechnology. The Static-RAM implementation is based on 45 nm CMOS submicron technology.The transmission gates are used in the access path of the SRAM Cell and the Sleep transistorspower gating technique is used for low leakage power and high performance. The transient anddc analysis of the proposed ST13T Static-RAM cell has been obtained for high performance. Itcan be observed from the results that the percentage reduction of 33.66% in power dissipation,62.18% in noise, 10.20% in delay and 38.14% in PDP is obtained for the proposed ST13T circuitwith power gating technique are that shows the high performance for Static-RAM Cell.

Keywords: CMOS integrated circuit, Integration VLSI, Layout, Logic design, Nanometers,Static-RAM chips

INTRODUCTIONFabrication of thousands of transistors into asingle chip in an Integrated Circuit (IC) is knownas the Very-Large-Scale Integration (VLSI). Inthe year 1970s, VLSI technology started whenupgraded semiconductor electronicstechnologies were being developed. Beforethe invention of VLSI technology, most ICs hada limited set of functions which these couldperform. An electronic circuit design might

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Int. J. Elec&Electr.Eng&Telecoms. 2016

1 M.E Scholar, Department of Electronics & Communication Engineering, NITTTR, Chandigarh, UT, India.2 Associate Professor, Department of Electronics & Communication Engineering, NITTTR, Chandigarh, UT, India.

consist of a CPU, ROM, RAM and other gluelogic. The first semiconductor chips held twotransistors each but, the subsequentadvancements added many more transistors,and as a result, more versatile functions wereintegrated over time. The first few integratedcircuits placed only a few electronics devices,i.e., as many as tens of diodes, transistors,resistors and capacitors, fabrication of one ormore logic gates on a single device is madepossible (Yanan Sun et al., 2015).

Research Paper

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For nearly past 40 years CMOS deviceshave been scaled down to nanometer scale inorder to achieve higher speed, betterperformance and low power consumption. Dueto the higher speed requirements, the Static-RAM based Cache memories and System-On-Chips (SOCs) are commonly used in mostof the applications. Due to device down-scaling there are several design challengesfor nanometer Static-RAM design. Now thedevices with very low threshold voltages andultra-thin gate oxide are used due to whichleakage-energy consumption is gettingincreased. Moreover, the data storagecapacity of the read and write operation is alsogetting affected. The intrinsic parameterfluctuation effects viz., line-edge roughness,Random Dopant Fluctuation (RDF) and gate-oxide-thickness fluctuation also reduces thestability of Static-RAM cell. In order to achievehigher noise-margin along with betterperformance new Static-RAM cells (JiajingWang and Benton Calhoun, 2011; Rajiv Joshiet al., 2011; Micheal Turi and Jose Delgado-Frias, 2014; and Ghasem Pasandi and SiedMehdi Fakhraie, 2015) have been introduced.In most of these cells read and writeoperations are isolated to achieve highernoise-margin. In this paper the detailedanalysis of 13T Static-RAM cell has beencarried out. All the simulations have beencarried on 45 nm CMOS submicron-technology using Cadence Virtuoso tool.

In the recent years, the sub-threshold designfor low power application is thought to be as alow energy solution. However, the memorycircuits operating successfully at such lowvoltage are more challenging since theperformance of the Static-RAM decreases at

the low voltages to a large extent. Many othereffects such as process-variation (PVT),bitline-leakage problem and transistorsmismatches challenge the proper operation ofStatic-RAMs that need a precise design. In thepractical sub threshold region the Static-RAMunit cell plays a important role. A robust celldesign that resists to the process-variation andbit-line leakage increases the total Static-RAMperformance.

STATIC-RAM CELLSThe overall performance of the system isdominated most of the time, by the SRAM thatmakes up a large portion of a system-on-chiparea. Moreover, the rapid growth and thepopularity of mobile, hand-held devices andother emerging applications, such as WSNs(wireless body sensing networks) implantedmedical instruments, necessitates therequirement of low-power SRAMs. Hence,there exist a requirement of a robust low-powerSRAM circuit design and has becomeimportant (Gahsem Pasandi and Sied MehdiFakhraie, 2014; Yanan Sun et al., 2015; andShairfe Muhammad Salahuddin and MansunChan, 2015).

However, a design of robust low-powerSRAM faces many process and performancerelated challenges. This is because, in deepsub micrometer technology, near/sub thresholdoperation is very challenging due to increaseddevice variations and reduced designmargins.

In addition, with each technology node, theshare of leakage power in the total powerdissipated by a circuit is increasing (BalwinderRaj et al., 2011; and Micheal Turi and JoseDelgado-Frias, 2014). Since, most of the time,

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SRAM cells stay in the standby mode, thus,leakage power is very important.

The increasing leakage current along withprocess variations leads to large spread inRead Static Noise Margin (RSNM) andcauses read failures at the tail of thedistribution (Balwinder Raj et al., 2011). Theshort-channel effect and sub threshold leakagecurrents of conventional silicon MOSFETs (Si-MOSFETs) are exacerbated with theminiaturization of device dimensions in eachnew CMOS technology generation (BalwinderRaj et al., 2011; Micheal Turi and JoseDelgado-Frias, 2014; Gahsem Pasandi andSied Mehdi Fakhraie, 2014; Yanan Sun et al.,2015; Shairfe Muhammad Salahuddin andMansun Chan, 2015; and Ghasem Pasandiand Sied Mehdi Fakhraie, 2015). Alternativematerials and devices are needed to be ableto continue scaling the CMOS technology.

The conventional 6T SRAM as shown inFigure 1, suffers from read-currentdisturbance-induced SNM degradation withVdd scaling. Moreover, due to increasedvariations at low supply voltages in advanced

CMOS processes, caused by global and localprocess variations, the read stability and thewrite stability of 6T SRAM cell degrade tounacceptable level. This is further exacerbatedby the half-select disturb and conflicting read/write requirements. To overcome thesechallenges, different configurations of SRAMcells, such as 7T (Jiajing Wang and BentonCalhoun, 2011; and Rajiv Joshi et al., 2011),8T (Khare et al., 2014), 9T (Vandana Sikarwaret al., 2013; and Joshika Sharma et al., 2015),and 10T (Shyam Akashe et al., 2012;Basavaraj Madiwalar and Kariyappa, 2013;Prathamesh Chodankar et al., 2014; andDeeksha Anandani et al., 2015) cells, havebeen proposed. In these circuits, data storingnodes are fully decoupled from read-accesspath to overcome the conflicting read/writerequirements. This approach offers an RSNMthat is almost the same as hold SNM (HSNM),therefore, resulting in better read stability. Theconventional 8T (Khare et al., 2014) uses twoextra transistors in the read path and one extraBit Line (BL) for reading. However, it suffersfrom leakage introduced in read path, whichfurther increases with scaling.

Liu and Kursun proposed a differential 9Tbit cell with read-disturb-free operation. It usesthe same BLs for both reading and writing;however, doubling the number of transistorsconnected to BL increases read-access time.Another 9T SRAM cell proposed in and 10TSRAM cells proposed, independently, in usethe modified versions of buffered read paththat reduces the leakage of read access path,while simultaneously improving RSNM. Changet al. have proposed a read-disturb-freedifferential 10T bit cell (hereafter called Chang10T), which is suitable for bit interleaved

Figure 1: Conventional 6T SRAM Cell(Balwinder Raj et al., 2011)

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architecture. However, it incorporates twoseries connected transistors in its write path,which degrade the write ability of the bit cell.The word line boosting is required to work asthe write-assist circuit, for a successful writeoperation, and so the dynamic power of thecell is increased. These bit cells address theread-disturb problem; nevertheless, havingcross coupled inverter pair topology, similarto conventional 6T cell, offers little immunity toprocess variations at low supply voltages. Thestability of the cross-coupled inverter is veryimportant for the successful SRAM operationunder Process, Voltage, and Temperature(PVT) variations (Dinesh Kumar and NoorMahammad, 2015). Hence, in this paper, a newsingle-ended Schmitt-Trigger (ST)-basedrobust low-power SRAM cell (hereafterreferred to as ST13T) is proposed, whichoffers lower delay, reduced powerconsumption along with high robustness toPVT variations.

PROPOSED ST13T SRAMCELL DESIGNSchmitt-Trigger-Based SRAM CellDesignThe stability of cross-coupled inverter pair inSRAM cell operating at very low supply voltageis not very promising. Furthermore, powerconsumption is high due to degraded invertercharacteristic. Therefore, an ST inverter isused to exploit the improved invertercharacteristic. The basic element for the datastorage in an ST-based SRAM cell uses acrosscoupled ST-based inverter pair shown inFigure 2a (Zhang Turi and Delgado-Frias,2012). ST is like a comparator, which includespositive feedback. Considering the switching

of output voltage, Vout from 1 to 0, in the caseof inverter, the transition starts as soon as theinput voltage reaches the Vt (threshold voltage)of the Pull down transistor, Vthn. On the otherhand, in case of ST-based inverter, for Vout =1, the feedback transistor MNF is ON and thevoltage at node VNX is Vdd – Vthn. In thiscase, for switching at the input the minimumvoltage required will be much higher than Vthn.The inverter characteristics and ST is shownin Figure 2b. Due to the improved invertercharacteristic, the ST-based SRAM offershigher SNM.

Proposed ST13T SRAM CellThe proposed work envisages design andsimulation of an schematic and layout of SRAMCell using Schmitt-trigger based 13Tconfiguration to study its behavior in nano scaletechnology node (45 nm) using simulationsoftware Cadence Virtuoso (Virtuoso V.6.1).The schematic of the proposed design will bebased on modifying the existing SRAM Cellconfigurations.

The various parameters for the design ofSRAM Cell like read and write stability, low

Figure 2: (a) Basic ST Inverter Used forthis Design, (b) Characteristics

of Inverter and ST Inverter for 01Transition at the Input (Vdd = 0.5 V)

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leakage power and performance metric basedon SNM and power delay product will beconsidered for developing the proposedSRAM Cell schematic and Layout. The gateleakage current based power dissipation,multiple threshold voltage and effect oftemperature on performance metric will beanalyzed by making use of simulated model.The optimization of the designed SRAM Cellwill also be carried out for low power low delaydesign.

Figure 3 shows schematic of the proposedST13T SRAM cell. The ST13T Static-RAM cellconsists of a cell core (cross-coupled STinverter), a read path consists the twotransistors, and a Write-Access (WA)transistor. The architectural change in theproposed schematic is the use of transmissiongates in the access path. The transmissiongate passes over the entire voltage range, i.e.,strong ‘0’ and strong ‘1’ which improves thecircuit performance. The write-accesstransistor is controlled by row-based WordLine (WL), and the read-access transistor is

controlled by row-based Read Word Line(RWL). The feedback transistors of ST, MNFL,and MNFR are controlled by internal storagenodes Q and QB, respectively, with their drainsconnected with a control signal Wordline_bar(WLB) (inverted version of write enable signal).

The virtual ground (VGND) is row based,and WLB and BLs (BL and RBL) are column-based. The VGND signal can be easily sharedover a row, if the memory is floor planned, suchthat all the cells of a word are adjacent to eachother. However, for a bit-interleavedarchitecture, a hard-coding technique can beused to generate VGND signal for the cells ofa selected word. The use of WLB and VGNDcontrol signals significantly mitigates the half-select disturb issue in the proposed cell. Themain reasons of the leakage current in aCMOS design are-i) Reverse-biased junctionleakage current, ii) Gate induced drainleakage, iii) Gate direct-tunnelling leakage, andiv) Sub threshold (weak inversion) leakagecurrent.

The sub threshold leakage current is themost predominant of all the leakage currentsources becomes very challenging forresearch in current and future silicontechnologies. For the reduction of the leakagepower in the SRAM Cell, the Sleep transistorspower gating technique is used whichminimizes the power dissipation during thedata retention phase as shown in Figure 4. ThePull-up network is connected to reduced powersupply (Vdd/2) during the data retention phaseas the sleep signal is activated that therebyreduces the power dissipation of the circuit.The power gating techniques are used toreduce the power consumption of the circuitby reducing the power wastage during the

Figure 3: Proposed ST13T SRAM CellCircuit with Transmission Gates

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undesired phases of the circuit operation. Inthis paper, the sleep transistor technique isimplemented for the power gating as shownin Figure 4.

The proposed ST13T SRAM Cell symbolis shown in Figure 5. The symbol can be usedfor the testing of the SRAM Circuit for properworking and the SRAM Cell Array is obtainedby using the symbol for SRAM to avoidcomplexity.

PROPOSED ST13T SRAMCELL SIMULATIONFigure 6 shows timing diagrams for the controlsignals in different modes of operation of theproposed ST13T SRAM cell. During the holdmode, both Word Line (WL) and Read WordLine (RWL) are disabled and VGND is keptgrounded. Therefore, the cross-coupledSchmitt Trigger inverter is isolated from boththe Bit Lines (BLs), and the data-holdingcapability is increased due to the feedbackmechanism. The four different cycles arerepresented in the fig. viz. HOLD, READ,WRITE ‘0’, WRITE ‘1’.

In the read operation, Word Line (WL) isdisabled, whereas Read Word Line (RWL) isenabled, which provides discharging path forRead Bit Line (RBL) through transistors MAR1and MAR2 depending on the data stored atQB. The disabled Word Line (WL) makes datastorage nodes (Q and QB) decoupled from

Figure 4: Proposed ST13T SRAM CellCircuit with Power Gating Sleep

Transistors

Figure 5: Proposed ST13T SRAM CellCircuit Symbol

Figure 6: Proposed ST13T SRAM CellTransient Analysis Waveforms

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bitline (BL) during the read access. Due to thisisolation, the RSNM is almost the same as theHSNM. Since the HSNM is very high in Schmitt-trigger based cell, read stability is remarkablyimproved.

The VGND is again kept at ground, so thatstorage node may not get disturbed duringread operation. It is to be noted that in bothread and hold mode, WLB is at Vdd (becausewrite enable signal is disabled), which helpsthe feedback transistors MNFL and MNFR toprovide a feedback mechanism and to exploitthe feature of ST inverter to have a goodinverter characteristic.

For writing data into the cell, WL is activatedto transfer the data to storage node from BL,which is set/reset according to the data to bewritten. RWL is disabled, whereas the nodeVGND is kept floating. The floating VGNDhelps to overcome significantly write 1 problemof a single BL structure.

The WLB signal, which is inverted versionof write enable signal, is disabled (i.e., WLB =0 V) during the write operation. Consequently,there is no feedback action from any of thefeedback transistors MNFL and MNFR as thevoltage at nodes NL and NR does not rise.Subsequently, the writing speed is significantlyincreased.

The data retention phase is when the databit is held in the cross-coupled inverter pair.During this phase the power requirement ofthe circuit is very less therefore, the SLEEPsignal is activated during this phase for theleakage power reduction. This technique isknown as the power gating technique. Thereare many possible choices for the power gatingtechniques but in this paper the sleep transistortechnique is used.

The dc analysis for the proposed ST13TSRAM Cell is shown in Figure 7. It is used tocalculate the dc power consumption and thedc operating point calculation. The differentphases of SRAM Cell operation, HOLD,READ, WRITE can be seen from the fig.

There are many leakage power reductiontechniques based on various modes ofoperation of systems. The two operationalmodes are a) active mode and b) standby (or)idle mode. Most of the techniques aim atpower reduction by shutting down the powersupply to the system or circuit during standbymode.

The sleep transistors are turned ON duringthe active mode, in such a way that the normaloperation is not affected as there exist a pathbetween the supply and the ground rails. Thesleep transistors are turned off in standbymode, thereby, shutting down the power supplyto the circuit creating virtual supply and ground

Figure 7: Proposed ST13T SRAM Cell DCAnalysis Waveforms

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rails. This technique is popularly known asSLEEP TRANSISTOR.

The Figures 8 and 9 gives the transient anddc analysis waveforms of the power gatedST13T SRAM Cell. As seen from the fig. that

even after using the power gated sleeptransistors, the SRAM cell is operation issame, i.e., the waveforms are nearly similarfor both the circuits.

Figure 9 shows the dc analysis of theproposed SRAM Cell with power gatingtechnique. The power is obtained using the dcanalysis of the schematic outputs Q and QB.

The noise analysis is performed for theProposed SRAM Cell and circuit with powergating technique and the noise voltagewaveform is obtained as shown in the Figures10-11. The noise summary is given later in thispaper in result discussion section.

The area is also a important parameter whiledesigning the VLSI circuit. In this circuit thenumbers of transistors are increased ascompared from the conventional 6T SRAMcircuit but the performance is many timesincreased. The area overhead can becalculated from the cell Layout. When the

Figure 8: Proposed ST13T SRAM Cell withPower Gating Transient Analysis

Waveforms

Figure 9: Proposed ST13T SRAM Cell withPower Gating DC Analysis Waveforms

Figure 10: Proposed ST13T SRAM CellNoise Response Waveforms

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RESULT ANALYSISAs seen from the transient and dc analysis ofthe proposed SRAM cell configuration that theproposed layout provides low powerdissipation, Noise, Delay and Power-DelayProduct values. Table 1 shows theperformance analysis of the proposed ST13TSRAM Cell on the basis on Power dissipation,Noise analysis, Delay and the Power- DelayProduct.

The Figure 13, shows the trend for the powerdissipation for the designed ST13T SRAM Celland then with the implementation of the powergating technique. As seen from the graph, thepower dissipation is greatly reduced with theuse of the sleep transistors. As during the dataretention phase much power is not neededtherefore the sleep transistor is activated duringSRAM Cell array is formed the overall area

overhead would be insignificant as comparedto the performance improvement in the SRAMCell design.

The autogenerated layout of the ST13Tproposed SRAM Layout is shown in Figure 12.

Figure 11: Proposed ST13T SRAM Cellwith Power Gating Noise Response

Waveforms

Figure 12: Proposed ST13T SRAM Cellwith Power Gating Layout

ParametersProposed ST13T

SRAM CellProposed ST13T SRAMCell with Power Gating

Power dissipation 3.568nW 2.367 nW

Noise 8.68392e -̂10 1.2115e -̂09

Delay 10.80ns 9.8ns

PDP 38.534X 10-18

J 11.872 X 10-18

J

Table 1: Proposed ST13T SRAM CellAnalysis

Figure 13: Trend for Power Dissipation

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this phase. The 33.66% power reduction isachieved with the use of sleep transistors.

Figure 14 shows the trend for the noiseanalysis for bothe the configurations of theSRAM Cell. As observed from the graph thatthe noise is also reduced by the use of thepower gating technique. The 62.18% noisereduction is achieved by the use of the powergated sleep transistors.

The Figure 15 shows the trend for the delayfor the ST13T and with the use of the powergated sleep transistors. The delay has to bereduced for the high speed memory design.

The delay is reduced for the power gatedconfiguration to a small extent but as comparedfrom the conventional SRAM circuit the delayis reduced considerably. The 10.20% delayreduction is obtained by the use of powergating configuration.

The power delay product trend is shown inthe Figure 16, there exist a trade-off betweenthe power delay product and it is expected thatit should be reduced for the high performanceof the circuit. The 38.14% reduction is obtainedin the power delay product by the use of powergating technique.

As observed from the table, the proposedcircuit gives the good results with use of thetransmission gates in the access path of theSRAM Cell and the power gating technique,i.e., the use of the sleep transistors. The use

Figure 14: Trend for Noise Analysis

Figure 15: Trend for Delay

Figure 16: Trend for Power Delay Product

Parameters% Reduction in ST 13T with

Power Gating Technique

Power dissipation 0.3366

Noise 0.6218

Delay 0.102

PDP 0.3814

Table 2: Results Analysis for theProposed Design

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of the power gating technique greatly reducesthe total power dissipation as during the dataretention mode the sleep input is activated,thereby, saving the power flowing through thecircuit as the pull-up network is connected tothe VDD/2 supply input. Hence, this proposedcircuit gives the satisfactory read write cyclesand also saves the power dissipation duringthe standby condition and therefore, the SNRimproves for the ST13T SRAM Cell.

As observed from the Table 2, the proposedcircuit gives the good results with use of thetransmission gates in the access path of theSRAM Cell and the power gating technique,i.e., the use of the sleep transistors. The useof the power gating technique greatly reducesthe total power dissipation as during the dataretention mode the sleep input is activated,thereby, saving the power flowing through thecircuit as the pull-up network is connected tothe VDD/2 supply input. Hence, this proposedcircuit gives the satisfactory read write cyclesand also saves the power dissipation duringthe standby condition and therefore, the SNRimproves for the ST13T SRAM Cell.

Figure 17 shows the trend of the percentagereduction in the various performanceparameters viz. power, noise, delay, PDP. Asseen from the fig. that the proposed circuitST13T SRAM Cell with power gatingtechniques provides good results.

CONCLUSIONThis paper includes the design of Static-RAMcell. Performance analysis of the proposedST13T SRAM Cell is done in this paper. Theleakage power dissipation has become oneof the most challenging issues in low powerVLSI circuit designs especially with on-chipdevices as it doubles for every two years. Thescaling down of threshold voltage hascontributed enormously towards increase insub threshold leakage current thereby makingthe static (leakage) power dissipation veryhigh. The proposed design aims at the powerreduction and SNR improvement for the Static-RAM cell configurations. From the result it isclear that optimized proposed ST13T Static-RAM Cell is more power efficient with the useof power gating technique, i.e., Sleeptransistors approach. During active mode thesleep transistors are turned ON, so that thenormal operation is not affected as there is apath between the supply and the ground. Instandby mode the sleep transistors are turnedoff thereby shutting down the power supply tothe circuit creating virtual supply and groundrails.

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Figure 17: Performance ImprovementTrend of the Proposed Circuit

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HIGH PERFORMANCE AND LOW POWER SRAM CELL DESIGN …

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