High-Performance, 16-bit Digital Signal Controllersare for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and

© 2009 Microchip Technology Inc. Preliminary DS70318D

dsPIC33FJ06GS101/X02 anddsPIC33FJ16GSX02/X04

Data SheetHigh-Performance,

16-bit Digital Signal Controllers

Note the following details of the code protection feature on Microchip devices:• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of ourproducts. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such actsallow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates. It is your responsibility toensure that your application meets with your specifications.MICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED, WRITTEN OR ORAL, STATUTORY OROTHERWISE, RELATED TO THE INFORMATION,INCLUDING BUT NOT LIMITED TO ITS CONDITION,QUALITY, PERFORMANCE, MERCHANTABILITY ORFITNESS FOR PURPOSE. Microchip disclaims all liabilityarising from this information and its use. Use of Microchipdevices in life support and/or safety applications is entirely atthe buyer’s risk, and the buyer agrees to defend, indemnify andhold harmless Microchip from any and all damages, claims,suits, or expenses resulting from such use. No licenses areconveyed, implicitly or otherwise, under any Microchipintellectual property rights.

DS70318D-page ii Prelimin

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

© 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

Printed on recycled paper.

ary © 2009 Microchip Technology Inc.

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

dsPIC33FJ06GS101/X02 anddsPIC33FJ16GSX02/X04

High-Performance, 16-Bit Digital Signal Controllers

Operating Range:• Up to 40 MIPS Operation (at 3.0-3.6V):

- Industrial temperature range (-40°C to +85°C)- Extended temperature range (-40°C to +125°C)

High-Performance DSC CPU:• Modified Harvard Architecture• C Compiler Optimized Instruction Set• 16-Bit Wide Data Path• 24-Bit Wide Instructions• Linear Program Memory Addressing up to

4M Instruction Words• Linear Data Memory Addressing up to 64 Kbytes• 83 Base Instructions: Mostly 1 Word/1 Cycle• Two 40-Bit Accumulators with Rounding and

Saturation Options• Flexible and Powerful Addressing modes:

- Indirect- Modulo- Bit-Reversed

• Software Stack• 16 x 16 Fractional/Integer Multiply Operations• 32/16 and 16/16 Divide Operations• Single-Cycle Multiply and Accumulate:

- Accumulator write back for DSP operations- Dual data fetch

• Up to ±16-Bit Shifts for up to 40-Bit Data

Digital I/O:• Peripheral Pin Select Functionality• Up to 35 Programmable Digital I/O Pins• Wake-up/Interrupt-on-Change for up to 30 Pins• Output Pins can Drive Voltage from 3.0V to 3.6V• Up to 5V Output with Open-Drain Configuration• 5V Tolerant Digital Input Pins (except RB5)• 16 mA Source/Sink on All PWM pins

On-Chip Flash and SRAM:• Flash Program Memory (up to 16 Kbytes)• Data SRAM (up to 2 Kbytes)• Boot and General Security for Program Flash

Peripheral Features:• Timer/Counters, up to Three 16-Bit Timers:

- Can pair up to make one 32-bit timer• Input Capture (up to two channels):

- Capture on up, down or both edges- 16-bit capture input functions- 4-deep FIFO on each capture

• Output Compare (up to two channels):- Single or Dual 16-Bit Compare mode- 16-Bit Glitchless PWM mode

• 4-Wire SPI:- Framing supports I/O interface to simple

codecs- 1-deep FIFO Buffer.- Supports 8-bit and 16-bit data- Supports all serial clock formats and

sampling modes• I2C™:

- Supports Full Multi-Master Slave mode - 7-bit and 10-bit addressing- Bus collision detection and arbitration- Integrated signal conditioning- Slave address masking

• UART:- Interrupt on address bit detect- Interrupt on UART error- Wake-up on Start bit from Sleep mode- 4-character TX and RX FIFO buffers- LIN bus support- IrDA® encoding and decoding in hardware- High-Speed Baud mode- Hardware Flow Control with CTS and RTS

Interrupt Controller:• 5-Cycle Latency• Up to 35 Available Interrupt Sources• Up to Three External Interrupts• Seven Programmable Priority Levels• Four Processor Exceptions

© 2009 Microchip Technology Inc. Preliminary DS70318D-page 1

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

High-Speed PWM Module Features:• Up to Four PWM Generators with Four to

Eight Outputs• Individual Time Base and Duty Cycle for each of

the Eight PWM Outputs• Dead Time for Rising and Falling Edges• Duty Cycle Resolution of 1.04 ns• Dead-Time Resolution of 1.04 ns• Phase Shift Resolution of 1.04 ns• Frequency Resolution of 1.04 ns• PWM modes Supported:

- Standard Edge-Aligned- True Independent Output- Complementary- Center-Aligned- Push-Pull- Multi-Phase- Variable Phase- Fixed Off-Time- Current Reset- Current-Limit

• Independent Fault/Current-Limit Inputs for 8 PWM Outputs

• Output Override Control• Special Event Trigger• PWM Capture Feature• Prescaler for Input Clock• Dual Trigger from PWM to ADC• PWMxL, PWMxH Output Pin Swapping• PWM4H, PWM4L Pins Remappable• On-the-Fly PWM Frequency, Duty Cycle and

Phase Shift Changes• Disabling of Individual PWM Generators• Leading-Edge Blanking (LEB) Functionality

High-Speed Analog Comparator• Up to Four Analog Comparators:

- 20 ns response time- 10-bit DAC for each analog comparator- DACOUT pin to provide DAC output- Programmable output polarity- Selectable input source- ADC sample and convert capability

• PWM Module Interface:- PWM duty cycle control- PWM period control- PWM Fault detect

High-Speed 10-Bit ADC• 10-Bit Resolution• Up to 12 Input Channels Grouped into

Six Conversion Pairs• Two Internal Reference Monitoring Inputs

Grouped into a Pair• Successive Approximation Register (SAR)

Converters for Parallel Conversions of Analog Pairs:- 4 Msps for devices with two SARs- 2 Msps for devices with one SAR

• Dedicated Result Buffer for each Analog Channel• Independent Trigger Source Section for each

Analog Input Conversion Pair

Power Management:• On-Chip 2.5V Voltage Regulator• Switch between Clock Sources in Real Time• Idle, Sleep, and Doze modes with Fast Wake-up

CMOS Flash Technology:• Low-Power, High-Speed Flash Technology• Fully Static Design• 3.3V (±10%) Operating Voltage• Industrial and Extended Temperature• Low-Power Consumption

System Management:• Flexible Clock Options:

- External, crystal, resonator, internal RC- Phase-Locked Loop (PLL) with 120 MHz VCO- Primary Crystal Oscillator (OSC) in the range

of 3 MHz to 40 MHz- Internal Low-Power RC (LPRC) oscillator at a

frequency of 32 kHz- Internal Fast RC (FRC) oscillator at a

frequency of 7.37 MHz• Power-on Reset (POR)• Brown-out Reset (BOR)• Power-up Timer (PWRT) • Oscillator Start-up Timer (OST)• Watchdog Timer with its RC Oscillator• Fail-Safe Clock Monitor (FSCM)• Reset by Multiple Sources• In-Circuit Serial Programming™ (ICSP™)• Reference Oscillator Output

DS70318D-page 2 Preliminary © 2009 Microchip Technology Inc.


Application Examples• AC-to-DC Converters• Automotive HID• Battery Chargers• DC-to-DC Converters• Digital Lighting• Induction Cooking• LED Ballast• Renewable Power/Pure Sine Wave Inverters• Uninterruptible Power Supply (UPS)

Packaging:• 18-Pin SOIC• 28-Pin SPDIP/SOIC/QFN-S• 44-Pin TQFP/QFN

Note: See the dsPIC33FJ06GS101/X02 anddsPIC33FJ16GSX02/X04 ControllerFamilies table for the exact peripheralfeatures per device.



dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 PRODUCT FAMILIESThe device names, pin counts, memory sizes andperipheral availability of each device are listed below.The following pages show their pinout diagrams.

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Controller Families

Device Pins

Prog

ram

Fla

sh M

emor

y (K

byte

s)

RA

M (B

ytes

)Remappable Peripherals

DA

C O

utpu

t

I2C

™

ADC

I/O P

ins

Pack

ages

Rem

appa

ble

Pins

16-b

it Ti

mer

Inpu

t Cap

ture

Out

put C

ompa

re

UA

RT

SPI

PWM

(2)

Ana

log

Com

para

tor

Exte

rnal

Inte

rrup

ts(3

)

SAR

s

Sam

ple

and

Hol

d (S

&H

) Circ

uit

Ana

log-

to-D

igita

l Inp

uts

dsPIC33FJ06GS101 18 6 256 8 2 0 1 1 1 2x2(1) 0 3 0 1 1 3 6 13 SOIC

dsPIC33FJ06GS102 28 6 256 16 2 0 1 1 1 2x2 0 3 0 1 1 3 6 21 SPDIPSOIC

QFN-S

dsPIC33FJ06GS202 28 6 1K 16 2 1 1 1 1 2x2 2 3 1 1 1 3 6 21 SPDIPSOIC

QFN-S

dsPIC33FJ16GS402 28 16 2K 16 3 2 2 1 1 3x2 0 3 0 1 1 4 8 21 SPDIPSOIC

QFN-S

dsPIC33FJ16GS404 44 16 2K 30 3 2 2 1 1 3x2 0 3 0 1 1 4 8 35 QFNTQFP

dsPIC33FJ16GS502 28 16 2K 16 3 2 2 1 1 4x2(1) 4 3 1 1 2 6 8 21 SPDIPSOIC

QFN-S

dsPIC33FJ16GS504 44 16 2K 30 3 2 2 1 1 4x2(1) 4 3 1 1 2 6 12 35 QFNTQFP

Note 1: The PWM4H:PWM4L pins are remappable.2: The PWM Fault pins and PWM synchronization pins are remappable.3: Only two out of three interrupts are remappable.



Pin Diagrams

18-Pin SOIC

28-Pin SOIC, SPDIPdsPIC

33FJ06GS101

MCLRAN0/RA0AN1/RA1

VDDVSS

AN2/RA2

TDO/RP5(1)/CN5/RB5 TMS/PGEC2/RP4(1)/CN4/RB4TCK/PGED2/INT0/RP3(1)/CN3/RB3

VCAP/VDDCORE

OSC2/CLKO/AN7/RP2(1)/CN2/RB2OSC1/CLKI/AN6/RP1(1)/CN1/RB1 VSS

PGEC1/SDA1/RP7(1)/CN7/RB7 PGED1/TDI/SCL1/RP6(1)/CN6/RB6

AN3/RP0(1)/CN0/RB0

12

345

678

9

1817

161514

131211

10

PWM1L/RA3PWM1H/RA4

dsPIC33FJ06G

S102

MCLR

PWM1L/RA3PWM1H/RA4PWM2L/RP14(1)/CN14/RB14PWM2H/RP13(1)/CN13/RB13RP12(1)/CN12/RB12RP11(1)/CN11/RB11VSS

VDD

AN0/RA0 AN1/RA1

AVDDAVSS

AN2/RA2

PGED3/RP8(1)/CN8/RB8 PGEC3/RP15(1)/CN15/RB15

TMS/PGEC2/RP4(1)/CN4/RB4TCK/PGED2/INT0/RP3(1)/CN3/RB3

VCAP/VDDCOREOSC2/CLKO/RP2(1)/CN2/RB2OSC1/CLKIN/RP1(1)/CN1/RB1

VSS

TDO/RP5(1)/CN5/RB5

PGEC1/SDA/RP7(1)/CN7/RB7PGED1/TDI/SCL/RP6(1)/CN6/RB6

AN5/RP10(1)/CN10/RB10AN4/RP9(1)/CN9/RB9AN3/RP0(1)/CN0/RB0

1234567891011121314

2827262524232221201918171615

Note 1: The RPn pins can be used by any remappable peripheral. See the “dsPIC33FJ06GS101/X02 anddsPIC33FJ16GSX02/X04 Controller Families” table for the list of available peripherals

28-Pin SPDIP, SOIC

dsPIC33FJ06G

S202

MCLR

PWM1L/RA3PWM1H/RA4PWM2L/RP14(1)/CN14/RB14PWM2H/RP13(1)/CN13/RB13TCK/RP12(1)/CN12/RB12TMS/RP11(1)/CN11/RB11VSS

VDD

AN0/CMP1A/RA0 AN1/CMP1B/RA1

AVDDAVSS

AN2/CMP1C/CMP2A/RA2

PGED3/RP8(1)/CN8/RB8 PGEC3/RP15(1)/CN15/RB15

PGEC2/EXTREF/RP4(1)/CN4/RB4PGED2/DACOUT/INT0/RP3(1)/CN3/RB3

VCAP/VDDCOREOSC2/CLKO/RP2(1)/CN2/RB2OSC1/CLKIN/RP1(1)/CN1/RB1

VSS

TDO/RP5(1)/CN5/RB5


AN5/CMP2D/RP10(1)/CN10/RB10AN4/CMP2C/RP9(1)/CN9/RB9

AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0

1234567891011121314

2827262524232221201918171615

= Pins are up to 5V tolerant





Pin Diagrams (Continued)

28-Pin SPDIP, SOIC

28-Pin SPDIP, SOIC

dsPIC33FJ16G

S402

MCLR

PWM1L/RA3PWM1H/RA4PWM2L/RP14(1)/CN14/RB14PWM2H/RP13(1)/CN13/RB13TCK/PWM3L/RP12(1)/CN12/RB12TMS/PWM3H/RP11(1)/CN11/RB11VSS

VDD

AN0/RA0AN1/RA1

AVDDAVSS

AN2/RA2

PGED3/RP8(1)/CN8/RB8 PGEC3/RP15/CN15/RB15

PGEC2/RP4(1)/CN4/RB4PGED2/INT0/RP3(1)/CN3/RB3

VCAP/VDDCOREOSC2/CLKO/AN7/RP2(1)/CN2/RB2OSC1/CLKIN/AN6/RP1(1)/CN1/RB1

VSS

TDO/RP5(1)/CN5/RB5


AN5/RP10(1)/CN10/RB10AN4/RP9(1)/CN9/RB9AN3/RP0(1)/CN0/RB0

1234567891011121314

2827262524232221201918171615


dsPIC33FJ16G

S502

MCLR

PWM1L/RA3PWM1H/RA4PWM2L/RP14(1)/CN14/RB14PWM2H/RP13(1)/CN13/RB13TCK/PWM3L/RP12(1)/CN12/RB12TMS/PWM3H/RP11(1)/CN11/RB11VSS

VDD

AN0/CMP1A/RA0AN1/CMP1B/RA1

AVDDAVSS

AN2/CMP1C/CMP2A/RA2

CN8/RB8/PGED3/RP8(1)/CN8/RB8 PGEC3/RP15(1)/CN15/RB15

PGEC2/EXTREF/RP4(1)/CN4/RB4PGED2/DACOUT/INT0/RP3(1)/CN3/RB3

VCAP/VDDCOREOSC2/CLKO/AN7/CMP3D/CMP4B/RP2(1)/CN2/RB2OSC1/CLKIN/AN6/CMP3C/CMP4A/RP1(1)/CN1/RB1

VSS

TDO/RP5(1)/CN6/RB5


AN5/CMP2D/CMP3B/RP10(1)/CN10/RB10AN4/CMP2C/CMP3A/RP9(1)/CN9/RB9AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0

1234567891011121314

2827262524232221201918171615






28-Pin QFN-S(2)

10 11

23

6

1

18192021

22

12 13 1415

87

1617

232425262728

9

dsPIC33FJ06GS102

PGE

D2/

INT0

/RP3

(1) /C

N3/

RB3

54

AVD

DAV

SS

PW

M1L

/RA

3P

WM

1H/R

A4

PWM2L/RP14(1)/CN14/RB14PWM2H/RP13(1)/CN13/RB13TCK/RP12(1)/CN12/RB12TMS/RP11(1)/CN11/RB11

VSSVCAP/VDDCORE

PGEC1/SDA/RP7(1)/CN7/RB7

PG

ED

1/TD

I/SC

L/R

P6(

1)/C

N6/

RB

6TD

O/R

P5(1

) /CN

5/R

B5P

GE

C3/

RP

15(1

) /CN

15/R

B15

MC

LRA

N0/

RA

0A

N1/

RA

1

AN2/RA2AN3/RP0(1)/CN0/RB0AN4/RP9(1)/CN9/RB9

AN5/RP10(1)/CN10/RB10VSS

OSC1/CLKIN/RP1(1)/CN1/RB1OSC2/CLKO/RP2(1)/CN2/RB2

PGE

C2/

RP

4(1)

/CN

4/R

B4

VD

DPG

ED

3/R

P8(

1)/C

N8/

RB

8

10 11

23

6

1

18192021

22

12 13 1415

87

1617

232425262728

9

dsPIC33FJ06GS202

PG

ED

2/D

AC

OU

T/IN

T0/R

P3(

1)/C

N3/

RB

3

54

AVD

DAV

SS

PW

M1L

/RA

3P

WM

1H/R

A4

PWM2L/RP14(1)/CN14/RB14PWM2H/RP13(1)/CN13/RB13TCK/RP12(1)/CN12/RB12TMS/RP11(1)/CN11/RB11

VSSVCAP/VDDCORE


PG

ED

1/TD

I/SC

L/R

P6(

1)/C

N6/

RB

6TD

O/R

P5(

1)/C

N5/

RB

5PG

EC

3/R

P15

(1) /C

N15

/RB

15

MC

LRA

N0/

CM

P1A

/RA

0A

N1/

CM

P1B

/RA

1

AN2/CMP1C/CMP2A/RA2AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0

AN4/CMP2C/RP9(1)/CN9/RB9AN5/CMP2D/RP10(1)/CN10/RB10

VSSOSC1/CLKIN/RP1(1)/CN1/RB1OSC2/CLKO/RP2(1)/CN2/RB2

PGE

C2/

EX

TRE

F/R

P4(

1)/C

N4/

RB

4V

DD

PG

ED3/

RP

8(1)

/CN

8/R

B8

Note 1: The RPn pins can be used by any remappable peripheral. See the “dsPIC33FJ06GS101/X02 anddsPIC33FJ16GSX02/X04 Controller Families” table for the list of available peripherals.

2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected toVSS externally.


= Pins are up to 5V tolerant 28-Pin QFN-S(2)




28-Pin QFN-S(2)

10 11

23

6

1

18192021

22

12 13 1415

87

1617

232425262728

9

dsPIC33FJ16GS402

PG

ED

2/IN

T0/R

P3(

1)/C

N3/

RB

3

54

AVD

DAV

SS

PW

M1L

/RA

3P

WM

1H/R

A4

PWM2L/RP14(1)/CN14/RB14PWM2H/RP13(1)/CN13/RB13TCK/PWM3L/RP12(1)/CN12/RB12TMS/PWM3H/RP11(1)/CN11/RB11

VSSVCAP/VDDCORE


PG

ED

1/TD

I/SC

L/R

P6(

1)/C

N6/

RB

6TD

O/R

P5(

1)/C

N5/

RB

5P

GEC

3/R

P15

(1) /C

N15

/RB

15

MC

LRA

N0/

RA

0A

N1/

RA

1

AN2/RA2AN3/RP0(1)/CN0/RB0AN4/RP9(1)/CN9/RB9

AN5/RP10(1)/CN10/RB10VSS

OSC1/CLKIN/AN6/RP1(1)/CN1/RB1OSC2/CLKO/AN7/RP2(1)/CN2/RB2

PG

EC2/

RP

4(1)

/CN

4/R

B4

VD

DP

GED

3/R

P8(

1)/C

N8/

RB

8

10 11

23

6

1

18192021

22

1213 1415

87

1617

232425262728

9

dsPIC33FJ16GS502

PG

ED

2/D

AC

OU

T/IN

T0/R

P3(

1)/C

N3/

RB

3

54

AVD

DAV

SS

PW

M1L

/RA

3P

WM

1H/R

A4

PWM2L/RP14(1)/CN14/RB14PWM2H/RP13(1)/CN13/RB13TCK/PWM3L/RP12(1)/CN12/RB12TMS/PWM3H/RP11(1)/CN11/RB11

VSSVCAP/VDDCORE


PG

ED

1/TD

I/SC

L/R

P6(

1)/C

N6/

RB

6TD

O/R

P5(1

) /CN

5/R

B5P

GEC

3/R

P15

(1) /C

N15

/RB

15

MC

LRA

N0/

CM

P1A

/RA

0A

N1/

CM

P1B

/RA

1

AN2/CMP1C/CMP2A/RA2AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0AN4/CMP2C/CMP3A/RP9(1)/CN9/RB9

AN5/CMP2D/CMP3B/RP10(1)/CN10/RB10VSS

OSC1/CLKIN/AN6/CMP3C/CMP4A/RP1(1)/CN1/RB1OSC2/CLKO/AN7/CMP3D/CMP4B/RP2(1)/CN2/RB2

PGE

C2/

EX

TREF

/RP

4(1)

/CN

4/R

B4

VD

DP

GE

D3/

RP

8(1)

/CN

8/R

B8



28-Pin QFN-S(2)






44-Pin QFN(2)

44

dsPIC33FJ16GS404

43 42 41 40 39 38 37 36 35

12 13 14 15 16 17 18 19 20 21

33029282726252423

45

789

1011

12 32

31

6

22

33

34

AN4/RP9(1)/CN9/RB9AN5/RP10(1)/CN10/RB10

OSC1/CLKI/AN6/RP1(1)/CN1/RB1OSC2/CLKO/AN7/RP2(1)/CN2/RB2

AN8/CMP4C/RP17(1)/CN17/RC1

RP26(1)/CN26/RC10VDD

RP25(1)/CN25/RC9

VSS

PG

ED1/

TDI/S

CL/

RP6

(1) /C

N6/

RB6

RP1

8(1)

/CN

18/R

C2

PG

EC3/

RP

15(1

) /CN

15/R

B15

VD

D

PG

EC2/

RP

4(1)

/CN

4/R

B4

RP2

4(1)

/CN

24/R

C8

VS

S

TDO

/RP5

(1) /C

N5/

RB

5

PG

ED3/

RP

8(1)

/CN

8/R

B8

RP2

3(1)

/CN

23/R

C7

PG

ED2/

INT0

/RP3

(1) /C

N3/

RB3

PWM2H/RP13(1)/CN13/RB13TCK/PWM3L/RP12(1)/CN12/RB12TMS/PWM3H/RP11(1)/CN11/RB11

VCAP/VDDCOREVSS

RP20(1)/CN20/RC4

RP19(1)/CN19/RC3RP22(1)/CN22/RC6RP21(1)/CN21/RC5


PWM2L/RP14(1)/CN14/RB14AN3/RP0(1)/CN0/RB0AN2/RA2

AN

1/R

A1

AN

0/R

A0

MC

LR

RP

29(1

) /CN

29/R

C13

AVD

D

AVS

S

PW

M1L

/RA

3P

WM

1H/R

A4

RP

16(1

) /CN

16/R

C0

RP

28(1

) /CN

28/R

C12

R

P27

(1) /C

N27

/RC

11







44-Pin QFN(2)

44

dsPIC33FJ16GS504

43 42 41 40 39 38 37 36 35

12 13 14 15 16 17 18 19 20 21

33029282726252423

45

7891011

12 32

31

6

22

33

34

AN4/CMP2C/CMP3A/RP9(1)/CN9/RB9AN5/CMP2D/CMP3B/RP10(1)/CN10/RB10

OSC1/CLKI/AN6/CMP3C/CMP4A/RP1(1)/CN1/RB1OSC2/CLKO/AN7/CMP3D/CMP4B/RP2(1)/CN2/RB2

AN8/CMP4C/RP17(1)/CN17/RC1

AN10/RP26(1)/CN26/RC10VDD

AN11/RP25(1)/CN25/RC9

VSS

PG

ED

1/TD

I/SC

L/R

P6(

1)/C

N6/

RB

6

AN

9/E

XTR

EF/C

MP

4D/R

P18

(1) /C

N18

/RC

2

PG

EC

3/R

P15

(1) /C

N15

/RB1

5

VDD

PG

EC

2/R

P4(

1)/C

N4/

RB4

RP

24(1

) /CN

24/R

C8

VSS

TDO

/RP

5(1)

/CN

5/R

B5

PG

ED

3/R

P8(

1)/C

N8/

RB

8

RP

23(1

) /CN

23/R

C7

PGE

D2/

DA

CO

UT/

INT0

/RP

3(1)

/CN

3/R

B3


VCAP/VDDCOREVSS

RP20(1)/CN20/RC4

RP19(1)/CN19/RC3RP22(1)/RN22/RC6RP21(1)/CN21/RC5


PWM2L/RP14(1)/CN14/RB14AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0AN2/CMP1C/CMP2A/RA2

AN

1/C

MP1

B/R

A1

AN

0/C

MP1

A/R

A0

MC

LR

RP

29(1

) /CN

29/R

C13

AVD

D

AVS

S

PW

M1L

/RA

3P

WM

1H/R

A4

RP

16(1

) /CN

16/R

C0

RP

28(1

) /CN

28/R

C12

RP

27(1

) /CN

27/R

C11


2: The metal plane at the bottom of the device is not connected to any pins and is recommended to connect to VSSexternally.





44-Pin TQFP

1011

23456

118 19 20 21 2212 13 14 15

38

87

44 43 42 41 40 3916 17

2930313233

232425262728

36 3435

9

37

PG

ED

1/TD

I/SC

L/R

P6(

1)/C

N6/

RB

6

RP

18(1

) /CN

18/R

C2

PG

EC

3/R

P15

(1) /C

N15

/RB

15

V DD

PG

EC

2/R

P4(

1)/C

N4/

RB

4

RP

16(1

) /CN

16/R

C0

VSS

TDO

/RP

5(1)

/CN

5/R

B5

PG

ED

3/R

P8(

1)/C

N8/

RB

8

RP

23(1

) /CN

23/R

C7

AN3/RP0(1)/CN0/RB0AN2/RA2

AN

1/R

A1

AN

0/R

A0

MC

LR

RP

29(1

) /CN

29/R

C13

AVD

D

AVS

S

PW

M1L

/RA

3P

WM

1H/R

A4


VSSVCAP/VDDCORE



AN4/RP9(1)/CN9/RB9AN5/RP10(1)/CN10/RB10

OSC1/CLKI/AN6/RP1(1)/CN1/RB1OSC2/CLKO/AN7/RP2(1)/CN2/RB2

RP17(1)/CN17/RC1RP20(1)/CN20/RC4

VDDVSS

RP

27(1

) /CN

27/R

C11

RP

28(1

) /CN

28/R

C12

PG

ED

2/IN

T0/R

P3(

1)/C

N3/

RB

3

dsPIC33FJ16GS404

PWM2L/RP14(1)/CN14/RB14

RP

24(1

) /CN

24/R

C8

RP25(1)/CN25/RC9RP26(1)/CN26/RC10






44-Pin TQFP

1011

23456

1

18 19 20 21 2212 13 14 15

38

87

44 43 42 41 40 39

16 17

2930313233

232425262728

36 3435

9

37

PG

ED

1/TD

I/SC

L/R

P6(

1)/C

N6/

RB

6

AN

9/E

XTR

EF/C

MP

4D/R

P18

(1) /C

N18

/RC

2

PG

EC

3/R

P15

(1) /C

N15

/RB1

5

VD

D

PG

EC

2/R

P4(

1)/C

N4/

RB

4

RP

16(1

) /CN

16/R

C0

VS

S

TDO

/RP5

(1) /C

N5/

RB5

PG

ED

3/R

P8(

1)/C

N8/

RB

8

RP

23(1

) /CN

23/R

C7

AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0AN2/CMP1C/CMP2A/RA2

AN

1/C

MP1

B/R

A1

AN

0/C

MP1

A/R

A0

MC

LR

RP

29(1

) /CN

29/R

C13

AVD

D

AVS

S

PW

M1L

/RA

3P

WM

1H/R

A4


VSSVCAP/VDDCORE



AN4/CMP2C/CMP3A/RP9(1)/CN9/RB9AN5/CMP2D/CMP3B/RP10(1)/CN10/RB10

OSC1/CLKI/AN6/CMP3C/CMP4A/RP1(1)/CN1/RB1OSC2/CLKO/AN7/CMP3D/CMP4B/RP2(1)/CN2/RB2

AN8/CMP4C/RP17(1)/CN17/RC1RP20(1)/CN20/RC4

VDDVSS

RP

27(1

) /CN

27/R

C11

RP

28(1

) /CN

28/R

C12

PG

ED

2/D

AC

OU

T/IN

T0/R

P3(

1)/C

N3/

RB

3

dsPIC33FJ16GS504

PWM2L/RP14(1)/CN14/RB14

RP

24(1

) /CN

24/R

C8

AN11/RP25(1)/CN25/RC9AN10/RP26(1)/CN26/RC10





Table of ContentsdsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Product Families .......................................................................................... 41.0 Device Overview ........................................................................................................................................................................ 152.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers .......................................................................................... 193.0 CPU............................................................................................................................................................................................ 294.0 Memory Organization ................................................................................................................................................................. 415.0 Flash Program Memory.............................................................................................................................................................. 816.0 Resets ....................................................................................................................................................................................... 877.0 Interrupt Controller ..................................................................................................................................................................... 958.0 Oscillator Configuration ......................................................................................................................................................... 1359.0 Power-Saving Features............................................................................................................................................................ 14710.0 I/O Ports .................................................................................................................................................................................. 15511.0 Timer1 ...................................................................................................................................................................................... 18312.0 Timer2/3 features .................................................................................................................................................................... 18513.0 Input Capture............................................................................................................................................................................ 19114.0 Output Compare....................................................................................................................................................................... 19315.0 High-Speed PWM..................................................................................................................................................................... 19716.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 21717.0 Inter-Integrated Circuit (I2C™) ................................................................................................................................................. 22318.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 23119.0 High-Speed 10-bit Analog-to-Digital Converter (ADC) ............................................................................................................. 23720.0 High-Speed Analog Comparator .............................................................................................................................................. 25921.0 Special Features ...................................................................................................................................................................... 26322.0 Instruction Set Summary .......................................................................................................................................................... 27123.0 Development Support............................................................................................................................................................... 27924.0 Electrical Characteristics .......................................................................................................................................................... 28325.0 Packaging Information.............................................................................................................................................................. 317Appendix A: Revision History............................................................................................................................................................. 329Index ................................................................................................................................................................................................. 337The Microchip Web Site ..................................................................................................................................................................... 341Customer Change Notification Service .............................................................................................................................................. 341Customer Support .............................................................................................................................................................................. 341Reader Response .............................................................................................................................................................................. 342Product Identification System ............................................................................................................................................................ 343



TO OUR VALUED CUSTOMERSIt is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchipproducts. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined andenhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department viaE-mail at [email protected] or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. Wewelcome your feedback.

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ErrataAn errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for currentdevices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revisionof silicon and revision of document to which it applies.To determine if an errata sheet exists for a particular device, please check with one of the following:• Microchip’s Worldwide Web site; http://www.microchip.com• Your local Microchip sales office (see last page)When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you areusing.

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1.0 DEVICE OVERVIEW

This document contains device-specific information forthe following dsPIC33F Digital Signal Controller (DSC)devices:

• dsPIC33FJ06GS101• dsPIC33FJ06GS102• dsPIC33FJ06GS202• dsPIC33FJ16GS402• dsPIC33FJ16GS404• dsPIC33FJ16GS502• dsPIC33FJ16GS504

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices contain extensive Digital Signal Processor(DSP) functionality with a high-performance, 16-bitmicrocontroller (MCU) architecture.

Figure 1-1 shows a general block diagram of the coreand peripheral modules in the dsPIC33FJ06GS101/X02and dsPIC33FJ16GSX02/X04 devices. Table 1-1 liststhe functions of the various pins shown in the pinoutdiagrams.

Note: This data sheet summarizes the featuresof the dsPIC33FJ06GS101/X02 anddsPIC33FJ16GSX02/X04 families ofdevices. It is not intended to be acomprehensive reference source. Tocomplement the information in this datasheet, refer to the “dsPIC33F FamilyReference Manual”. Please see theMicrochip web site (www.microchip.com)for the latest “dsPIC33F Family ReferenceManual” sections.



FIGURE 1-1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 BLOCK DIAGRAM

16

OSC1/CLKIOSC2/CLKO

VDD, VSS

TimingGeneration

MCLR

Power-upTimer

OscillatorStart-up Timer

Power-onReset

WatchdogTimer

Brown-outReset

Precision

ReferenceBand Gap

FRC/LPRCOscillators

RegulatorVoltage

VCAP/VDDCORE

IC1,2 I2C1

PORTA

InstructionDecode &

Control

PCH PCL

16

Program Counter

16-Bit ALU

23

23

24

23

Instruction Reg

PCU

16 x 16W Register Array

ROM Latch

16

EA MUX

16

16

8

InterruptController

PSV & TableData AccessControl Block

StackControl

Logic

LoopControlLogic

Data Latch

AddressLatch

Address Latch

Program Memory

Data Latch

L

itera

l Dat

a 16 16

16

16

Data Latch

AddressLatch

16

X RAM Y RAM

16

Y Data Bus

X Data Bus

DSP Engine

Divide Support

16

Control Signals to Various Blocks

ADC1Timers

PORTB

Address Generator Units

1-3

CNx

UART1PWM

4 x 2

RemappablePins

PORTC

SPI1

OC1OC2

AnalogComparators 1-4

Note: Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and featurespresent on each device.



TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Name PinTypeBufferType

PPS Capable Description

AN0-AN11 I Analog No Analog input channelsCLKI

CLKO

I

O

ST/CMOS

—

No

No

External clock source input. Always associated with OSC1 pin function.Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function.

OSC1

OSC2

I

I/O

ST/CMOS

—

No

No

Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise.Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes.

CN0-CN29 I ST No Change notification inputs. Can be software programmed for internal weak pull-ups on all inputs.

IC1-IC2 I ST Yes Capture inputs 1/2OCFAOC1-OC2

IO

ST—

YesYes

Compare Fault A input (for Compare Channels 1 and 2)Compare Outputs 1 through 2

INT0INT1INT2

III

STSTST

NoYesYes

External Interrupt 0External Interrupt 1External Interrupt 2

RA0-RA4 I/O ST No PORTA is a bidirectional I/O portRB0-RB15 I/O ST No PORTB is a bidirectional I/O portRC0-RC13 I/O ST No PORTC is a bidirectional I/O portRP0-RP29 I/O ST No Remappable I/O pinsT1CKT2CKT3CK

III

STSTST

YesYesYes

Timer1 external clock inputTimer2 external clock inputTimer3 external clock input

U1CTSU1RTSU1RXU1TX

IOIO

ST—ST—

YesYesYesYes

UART1 clear to sendUART1 ready to sendUART1 receiveUART1 transmit

SCK1SDI1SDO1SS1

I/OIO

I/O

STST—ST

YesYesYesYes

Synchronous serial clock input/output for SPI1SPI1 data inSPI1 data outSPI1 slave synchronization or frame pulse I/O

SCL1SDA1

I/OI/O

STST

NoNo

Synchronous serial clock input/output for I2C1Synchronous serial data input/output for I2C1

TMSTCKTDITDO

IIIO

TTLTTLTTL—

NoNoNoNo

JTAG Test mode select pinJTAG test clock input pinJTAG test data input pinJTAG test data output pin

Legend: CMOS = CMOS compatible input or output Analog = Analog input I = InputST = Schmitt Trigger input with CMOS levels P = Power O = OutputTTL = Transistor-Transistor Logic PPS = Peripheral Pin Select



CMP1ACMP1BCMP1CCMP1DCMP2ACMP2BCMP2CCMP2DCMP3ACMP3BCMP3CCMP3DCMP4ACMP4BCMP4CCMP4D

IIIIIIIIIIIIIIII

AnalogAnalogAnalogAnalogAnalogAnalogAnalogAnalogAnalogAnalogAnalogAnalogAnalogAnalogAnalogAnalog

NoNoNoNoNoNoNoNoNoNoNoNoNoNoNoNo

Comparator 1 Channel AComparator 1 Channel BComparator 1 Channel CComparator 1 Channel DComparator 2 Channel AComparator 2 Channel BComparator 2 Channel CComparator 2 Channel DComparator 3 Channel AComparator 3 Channel BComparator 3 Channel CComparator 3 Channel DComparator 4 Channel AComparator 4 Channel BComparator 4 Channel CComparator 4 Channel D

DACOUT O — No DAC output voltageACMP1-ACMP4 O — Yes DAC trigger to PWM moduleEXTREF I Analog No External voltage reference input for the reference DACsREFCLKO O — Yes REFCLKO output signal is a postscaled derivative of the system

clock

FLT1-FLT8SYNCI1-SYNCI2SYNCO1PWM1LPWM1HPWM2LPWM2HPWM3LPWM3HPWM4LPWM4H

IIOOOOOOOOO

STST—————————

YesYesYesNoNoNoNoNoNoYesYes

Fault Inputs to PWM moduleExternal synchronization signal to PWM Master Time BasePWM master time base for external device synchronizationPWM1 low outputPWM1 high outputPWM2 low outputPWM2 high outputPWM3 low outputPWM3 high outputPWM4 low outputPWM4 high output

PGED1PGEC1

PGED2PGEC2

PGED3PGEC3

I/OI

I/OI

I/OI

STST

STST

STST

NoNo

NoNo

NoNo

Data I/O pin for programming/debugging communication Channel 1Clock input pin for programming/debugging communication Channel 1Data I/O pin for programming/debugging communication Channel 2Clock input pin for programming/debugging communication Channel 2Data I/O pin for programming/debugging communication Channel 3Clock input pin for programming/debugging communication Channel 3

MCLR I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the device.

AVDD P P No Positive supply for analog modules. This pin must be connected at all times.

AVSS P P No Ground reference for analog modulesVDD P — No Positive supply for peripheral logic and I/O pinsVCAP/VDDCORE P — No CPU logic filter capacitor connectionVSS P — No Ground reference for logic and I/O pins

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name PinTypeBufferType

PPS Capable Description

Legend: CMOS = CMOS compatible input or output Analog = Analog input I = InputST = Schmitt Trigger input with CMOS levels P = Power O = OutputTTL = Transistor-Transistor Logic PPS = Peripheral Pin Select



2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT DIGITAL SIGNAL CONTROLLERS

2.1 Basic Connection RequirementsGetting started with the dsPIC33FJ06GS101/X02 anddsPIC33FJ16GSX02/X04 family of 16-bit Digital SignalControllers (DSC) requires attention to a minimal set ofdevice pin connections before proceeding withdevelopment. The following is a list of pin names, whichmust always be connected:

• All VDD and VSS pins (see Section 2.2 “Decoupling Capacitors”)

• All AVDD and AVSS pins (regardless if ADC module is not used) (see Section 2.2 “Decoupling Capacitors”)

• VCAP/VDDCORE (see Section 2.3 “Capacitor on Internal Voltage Regulator (VCAP/VDDCORE)”)

• MCLR pin (see Section 2.4 “Master Clear (MCLR) Pin”)

• PGECx/PGEDx pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see Section 2.5 “ICSP Pins”)

• OSC1 and OSC2 pins when external oscillator source is used (see Section 2.6 “External Oscillator Pins”)

2.2 Decoupling CapacitorsThe use of decoupling capacitors on every pair ofpower supply pins, such as VDD, VSS, AVDD andAVSS is required.

Consider the following criteria when using decouplingcapacitors:

• Value and type of capacitor: Recommendation of 0.1 μF (100 nF), 10-20V. This capacitor should be a low-ESR and have resonance frequency in the range of 20 MHz and higher. It is recommended that ceramic capacitors be used.

• Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length.

• Handling high frequency noise: If the board is experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 μF to 0.001 μF. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 μF in parallel with 0.001 μF.

• Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing PCB track inductance.

Note: This data sheet summarizes the featuresof the dsPIC33FJ06GS101/X02 anddsPIC33FJ16GSX02/X04 family ofdevices. It is not intended to be acomprehensive reference source. Tocomplement the information in this datasheet, refer to the dsPIC33F FamilyReference Manual, which is available fromthe Microchip website(www.microchip.com).


http://www.microchip.comhttp://www.microchip.com


FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION

2.2.1 TANK CAPACITORSOn boards with power traces running longer than sixinches in length, it is suggested to use a tank capacitorfor integrated circuits including DSCs to supply a localpower source. The value of the tank capacitor shouldbe determined based on the trace resistance that con-nects the power supply source to the device, and themaximum current drawn by the device in the applica-tion. In other words, select the tank capacitor so that itmeets the acceptable voltage sag at the device. Typicalvalues range from 4.7 μF to 47 μF.

2.3 Capacitor on Internal Voltage Regulator (VCAP/VDDCORE)

A low-ESR (< 5 Ohms) capacitor is required on theVCAP/VDDCORE pin, which is used to stabilize thevoltage regulator output voltage. The VCAP/VDDCOREpin must not be connected to VDD, and must have acapacitor between 4.7 μF and 10 μF, 16V connected toground. The type can be ceramic or tantalum. Refer toSection 24.0 “Electrical Characteristics” foradditional information.

The placement of this capacitor should be close to theVCAP/VDDCORE. It is recommended that the tracelength not exceed one-quarter inch (6 mm). Refer toSection 21.2 “On-Chip Voltage Regulator” fordetails.

2.4 Master Clear (MCLR) PinThe MCLR pin provides for two specific devicefunctions:

• Device Reset• Device programming and debugging.

During device programming and debugging, theresistance and capacitance that can be added to thepin must be considered. Device programmers anddebuggers drive the MCLR pin. Consequently,specific voltage levels (VIH and VIL) and fast signaltransitions must not be adversely affected. Therefore,specific values of R and C will need to be adjustedbased on the application and PCB requirements.

For example, as shown in Figure 2-2, it isrecommended that the capacitor C, be isolated fromthe MCLR pin during programming and debuggingoperations.

Place the components shown in Figure 2-2 withinone-quarter inch (6 mm) from the MCLR pin.

FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS

dsPIC33FV

DD

VSS

VDD

VSS

VSS

VDD

AVD

D

AVS

S

VDD

VSS

0.1 μFCeramic

0.1 μFCeramic

0.1 μFCeramic

0.1 μFCeramic

C

R

VDD

MCLR

0.1 μFCeramic

VC

AP/V

DD

CO

RE

10 Ω

R1

Note 1: R ≤ 10 kΩ is recommended. A suggestedstarting value is 10 kΩ. Ensure that theMCLR pin VIH and VIL specifications are met.

2: R1 ≤ 470Ω will limit any current flowing intoMCLR from the external capacitor C, in theevent of MCLR pin breakdown, due toElectrostatic Discharge (ESD) or ElectricalOverstress (EOS). Ensure that the MCLR pinVIH and VIL specifications are met.

C

R1R

VDD

MCLR

dsPIC33FJP



2.5 ICSP PinsThe PGECx and PGEDx pins are used for In-CircuitSerial Programming™ (ICSP™) and debuggingpurposes. It is recommended to keep the trace lengthbetween the ICSP connector and the ICSP pins on thedevice as short as possible. If the ICSP connector isexpected to experience an ESD event, a series resistoris recommended, with the value in the range of a fewtens of Ohms, not to exceed 100 Ohms.

Pull-up resistors, series diodes, and capacitors on thePGECx and PGEDx pins are not recommended as theywill interfere with the programmer/debuggercommunications to the device. If such discretecomponents are an application requirement, theyshould be removed from the circuit during program-ming and debugging. Alternatively, refer to the AC/DCcharacteristics and timing requirements information inthe respective device Flash programming specificationfor information on capacitive loading limits and pin inputvoltage high (VIH) and input low (VIL) requirements.

Ensure that the “Communication Channel Select”(i.e., PGECx/PGEDx pins) programmed into the devicematches the physical connections for the ICSP toMPLAB® ICD 2, MPLAB® ICD 3, or MPLAB® REALICE™.

For more information on ICD 2, ICD 3, and REAL ICEconnection requirements, refer to the followingdocuments that are available on the Microchip website.

• “MPLAB® ICD 2 In-Circuit Debugger User's Guide” DS51331

• “Using MPLAB® ICD 2” (poster) DS51265• “MPLAB® ICD 2 Design Advisory” DS51566• “Using MPLAB® ICD 3” (poster) DS51765• “MPLAB® ICD 3 Design Advisory” DS51764• “MPLAB® REAL ICE™ In-Circuit Debugger

User's Guide” DS51616• “Using MPLAB® REAL ICE™” (poster) DS51749

2.6 External Oscillator PinsMany DSCs have options for at least two oscillators: ahigh-frequency primary oscillator and a low-frequencysecondary oscillator (refer to Section 8.0 “OscillatorConfiguration” for details). The oscillator circuit should be placed on the sameside of the board as the device. Also, place theoscillator circuit close to the respective oscillator pins,not exceeding one-half inch (12 mm) distancebetween them. The load capacitors should be placednext to the oscillator itself, on the same side of theboard. Use a grounded copper pour around theoscillator circuit to isolate them from surroundingcircuits. The grounded copper pour should be routeddirectly to the MCU ground. Do not run any signaltraces or power traces inside the ground pour. Also, ifusing a two-sided board, avoid any traces on theother side of the board where the crystal is placed. Asuggested layout is shown in Figure 2-3.

FIGURE 2-3: SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT

13Main Oscillator

Guard Ring

Guard Trace

SecondaryOscillator

14

15

16

17

18

19

20



2.7 Oscillator Value Conditions on Device Start-up

If the PLL of the target device is enabled andconfigured for the device start-up oscillator, themaximum oscillator source frequency must be limitedto 4 MHz < FIN < 8 MHz to comply with device PLLstart-up conditions. This means that if the externaloscillator frequency is outside this range, theapplication must start up in the FRC mode first. Thedefault PLL settings after a POR with an oscillatorfrequency outside this range will violate the deviceoperating speed.

Once the device powers up, the application firmwarecan initialize the PLL SFRs, CLKDIV, and PLLDBF to asuitable value, and then perform a clock switch to theOscillator + PLL clock source. Note that clock switchingmust be enabled in the device Configuration word.

2.8 Configuration of Analog and Digital Pins During ICSP Operations

If MPLAB ICD 2, ICD 3 or REAL ICE is selected as adebugger, it automatically initializes all of the A/D inputpins (ANx) as “digital” pins, by setting all bits in theADPCFG register.

The bits in the registers that correspond to the A/D pinsthat are initialized by MPLAB ICD 2, ICD 3, or REALICE, must not be cleared by the user application firm-ware; otherwise, communication errors will resultbetween the debugger and the device.

If your application needs to use certain A/D pins asanalog input pins during the debug session, the userapplication must clear the corresponding bits in theADPCFG register during initialization of the ADC mod-ule.

When MPLAB ICD 2, ICD 3, or REAL ICE is used as aprogrammer, the user application firmware mustcorrectly configure the ADPCFG register. Automaticinitialization of these registers is only done duringdebugger operation. Failure to correctly configure theregister(s) will result in all A/D pins being recognized asanalog input pins, resulting in the port value being readas a logic '0', which may affect user application func-tionality.

2.9 Unused I/OsUnused I/O pins should be configured as outputs anddriven to a logic-low state.

Alternatively, connect a 1k to 10k resistor to VSS onunused pins and drive the output to logic low.

2.10 Typical Application Connection Examples

Examples of typical application connections are shownin Figure 2-4 through Figure 2-11.



FIGURE 2-4: DIGITAL PFC

FIGURE 2-5: BOOST CONVERTER IMPLEMENTATION

VAC

IPFC

VHV_BUS

ADC Channel ADC Channel ADC Channel PWM Output

|VAC|

k1

k2

k3

FET

dsPIC33FJ06GS101

Driver

IPFC

VOUTPUT

ADC Channel ADC ADC Channel PWM

k1

k2

k3

FET

dsPIC33FJ06GS101

VINPUT

Channel Output

Driver



FIGURE 2-6: SINGLE-PHASE SYNCHRONOUS BUCK CONVERTER

FIGURE 2-7: MULTI-PHASE SYNCHRONOUS BUCK CONVERTER

k1

Analog Comp.

k2k7P

WM

PW

M ADC Channel

ADC Channel

5V Output

I5V

12V Input

FET Driver

dsPIC33FJ06GS202

k5

k4

k3

k6k7

Analog Comparator

Analog Comparator

ADC Channel

Analog Comparator

ADC Channel P

WM

PW

M

PWMPWM

PW

MP

WM

3.3V Output12V Input

FET Driver

FET Driver

FET Driver

dsPIC33FJ06GS502



FIGURE 2-8: OFF-LINE UPS

ADC

ADC

ADC

ADC

ADC

PWM PWMPWM

dsPIC33FJ16GS504

PWM PWM PWM

FET Driver

FET Driver k2 k1

FET Driver

FET Driver

FET Driver

FET Driver k4 k5

VBAT

GND

+VOUT+

VOUT-

Full-Bridge InverterPush-Pull ConverterVDC

GND

FET Driver

ADC PWM

k3

k6

orAnalog Comp.

Battery Charger

+



FIGURE 2-9: INTERLEAVED PFC

VAC

VOUT+

ADC Channel PWM ADCPWM

|VAC|

k4 k3

FET

dsPIC33FJ06GS202

Driver

VOUT-

ADC Channel

FET Driver

ADC

k1 k2

Channel Channel ADC

Channel



FIGURE 2-10: PHASE-SHIFTED FULL-BRIDGE CONVERTER

VIN+

VIN-

S1

Gate 4

Gate 2

Gate 3Gate 1

AnalogGround

VOUT+

VOUT-

dsPIC33FJ06GS202

PWM

PWM ADCChannel

PWM ADCChannel

k2FET Driver

k1

FET Driver

FET Driver

Gate 1

Gate 2

S1 Gate 3

Gate 4

S3

S3

Gate 6

Gate 5

Gat

e 6Gate 5



FI

GU

RE

2-11

:A

C-T

O-D

C P

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UPP

LY W

ITH

PFC

AN

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UTP

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X

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PWM

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V_B

US

VO

UT

Isol

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n B

arrie

r

AD

C

Cha

nnel

PWM

PWM

PWM

FET

Driv

erFE

TD

river

FET

Driv

er

dsPI

C33

FJ16

GS5

04k 6

Ana

log

Com

p.

UAR

T TX

k 10

k 7

k 9k 8

k 11

k 5

PWMPWM

ADC

C

hann

el

Ana

log

Com

para

tor

Ana

log

Com

para

tor

AD

C C

hann

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Ana

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ADC

C

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PWMPWM

PW

MP

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PWMPWM

3.3V

Out

put

5V O

utpu

t

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12V

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t

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Driv

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T D

river

FET

Driv

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FET

Driv

er

I 3.3

V_3

I 3.3

V_2

I 3.3

V_1

dsPI

C33

FJ16

GS5

04

VAC

IPFC

VH

V_B

US

|VA

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k 1

k 2

k 3

FET

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3.0 CPU

The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 CPU module has a 16-bit (data) modified Harvardarchitecture with an enhanced instruction set, includingsignificant support for DSP. The CPU has a 24-bitinstruction word with a variable length opcode field. TheProgram Counter (PC) is 23 bits wide and addresses upto 4M x 24 bits of user program memory space. Theactual amount of program memory implemented variesfrom device to device. A single-cycle instruction prefetchmechanism is used to help maintain throughput andprovides predictable execution. All instructions execute ina single cycle, with the exception of instructions thatchange the program flow, the double-word move (MOV.D)instruction and the table instructions. Overhead-freeprogram loop constructs are supported using the DO andREPEAT instructions, both of which are interruptible atany point.

The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices have sixteen, 16-bit working registers in theprogrammer’s model. Each of the working registers canserve as a data, address or address offset register. Thesixteenth working register (W15) operates as a softwareStack Pointer (SP) for interrupts and calls.

There are two classes of instruction in thedsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices: MCU and DSP. These two instructionclasses are seamlessly integrated into a single CPU.The instruction set includes many addressing modesand is designed for optimum C compiler efficiency.For most instructions, the dsPIC33FJ06GS101/X02and dsPIC33FJ16GSX02/X04 is capable of execut-ing a data (or program data) memory read, a work-ing register (data) read, a data memory write and aprogram (instruction) memory read per instructioncycle. As a result, three parameter instructions canbe supported, allowing A + B = C operations to beexecuted in a single cycle.

A block diagram of the CPU is shown in Figure 3-1,and the programmer’s model for thedsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 is shown in Figure 3-2.

3.1 Data Addressing OverviewThe data space can be addressed as 32K words or64 Kbytes and is split into two blocks, referred to as Xand Y data memory. Each memory block has its ownindependent Address Generation Unit (AGU). TheMCU class of instructions operates solely throughthe X memory AGU, which accesses the entirememory map as one linear data space. Certain DSPinstructions operate through the X and Y AGUs tosupport dual operand reads, which splits the dataaddress space into two parts. The X and Y data spaceboundary is device-specific.

Overhead-free circular buffers (Modulo Addressingmode) are supported in both X and Y address spaces.The Modulo Addressing removes the softwareboundary checking overhead for DSP algorithms.Furthermore, the X AGU circular addressing can beused with any of the MCU class of instructions. The XAGU also supports Bit-Reversed Addressing to greatlysimplify input or output data reordering for radix-2 FFTalgorithms.

The upper 32 Kbytes of the data space memory mapcan optionally be mapped into program space at any16K program word boundary defined by the 8-bitProgram Space Visibility Page (PSVPAG) register. Theprogram-to-data space mapping feature lets anyinstruction access program space as if it were dataspace.

3.2 DSP Engine OverviewThe DSP engine features a high-speed, 17-bit by 17-bitmultiplier, a 40-bit ALU, two 40-bit saturatingaccumulators and a 40-bit bidirectional barrel shifter.The barrel shifter is capable of shifting a 40-bit value upto 16 bits, right or left, in a single cycle. The DSPinstructions operate seamlessly with all otherinstructions and have been designed for optimal real-time performance. The MAC instruction and other asso-ciated instructions can concurrently fetch two dataoperands from memory while multiplying two Wregisters and accumulating and optionally saturatingthe result in the same cycle. This instructionfunctionality requires that the RAM data space be splitfor these instructions and linear for all others. Dataspace partitioning is achieved in a transparent andflexible manner through dedicating certain workingregisters to each address space.

Note: This data sheet summarizes the featuresof the dsPIC33FJ06GS101/X02 anddsPIC33FJ16GSX02/X04 families ofdevices. It is not intended to be acomprehensive reference source. Tocomplement the information in this datasheet, refer to the “dsPIC33F FamilyReference Manual”, Section 2. “CPU”(DS70204), which is available from theMicrochip web site (www.microchip.com).


http://www.microchip.comhttp://www.microchip.com


3.3 Special MCU FeaturesThe dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 features a 17-bit by 17-bit single-cycle multiplier thatis shared by both the MCU ALU and DSP engine. Themultiplier can perform signed, unsigned and mixed signmultiplication. Using a 17-bit by 17-bit multiplier for 16-bitby 16-bit multiplication not only allows you to performmixed sign multiplication, it also achieves accurateresults for special operations, such as (-1.0) x (-1.0).

The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 supports 16/16 and 32/16 divide operations, bothfractional and integer. All divide instructions are iterativeoperations. They must be executed within a REPEATloop, resulting in a total execution time of 19 instructioncycles. The divide operation can be interrupted duringany of those 19 cycles without loss of data.

A 40-bit barrel shifter is used to perform up to a 16-bitleft or right shift in a single cycle. The barrel shifter canbe used by both MCU and DSP instructions.

FIGURE 3-1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 CPU CORE BLOCK DIAGRAM

InstructionDecode &

Control

PCH PCLProgram Counter

16-Bit ALU

24

23

Instruction Reg

PCU

16 x 16W Register Array

ROM Latch

EA MUX

InterruptController

StackControlLogic

LoopControlLogic

Data Latch

AddressLatch

Control Signalsto Various Blocks

L

itera

l Dat

a

16 16

16

To Peripheral Modules

Data Latch

AddressLatch

16

X RAM Y RAM

Address Generator Units

16

Y Data Bus

X Data Bus

DSP Engine

Divide Support

16

16

23

23

168

PSV & TableData AccessControl Block

16

16

16

16

Program Memory

Data Latch

Address Latch



FIGURE 3-2: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 PROGRAMMER’S MODEL

PC22 PC0

7 0

D0D15

Program Counter

Data Table Page Address

STATUS Register

Working Registers

DSP OperandRegisters

W1

W2

W3

W4

W5

W6

W7

W8

W9

W10

W11

W12/DSP Offset

W13/DSP Write Back

W14/Frame Pointer

W15/Stack Pointer

DSP AddressRegisters

AD39 AD0AD31

DSPAccumulators

ACCA

ACCB

7 0Program Space Visibility Page Address

Z

0

OA OB SA SB

RCOUNT15 0

REPEAT Loop Counter

DCOUNT15 0

DO Loop Counter

DOSTART 22 0

DO Loop Start Address

IPL2 IPL1

SPLIM Stack Pointer Limit Register

AD15

SRL

PUSH.S Shadow

DO Shadow

OAB SAB

15 0Core Configuration Register

Legend

CORCON

DA DC RA N

TBLPAG

PSVPAG

IPL0 OV

W0/WREG

SRH

DO Loop End AddressDOEND 22

C



3.4 CPU Control Registers

REGISTER 3-1: SR: CPU STATUS REGISTER

R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R -0 R/W-0OA OB SA(1) SB(1) OAB SAB(1,4) DA DC

bit 15 bit 8

R/W-0(2) R/W-0(3) R/W-0(3) R-0 R/W-0 R/W-0 R/W-0 R/W-0IPL(2) RA N OV Z C

bit 7 bit 0

Legend:C = Clearable bit R = Readable bit U = Unimplemented bit, read as ‘0’S = Settable bit W = Writable bit -n = Value at POR‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 OA: Accumulator A Overflow Status bit1 = Accumulator A overflowed0 = Accumulator A has not overflowed

bit 14 OB: Accumulator B Overflow Status bit1 = Accumulator B overflowed0 = Accumulator B has not overflowed

bit 13 SA: Accumulator A Saturation ‘Sticky’ Status bit(1)

1 = Accumulator A is saturated or has been saturated at some time0 = Accumulator A is not saturated

bit 12 SB: Accumulator B Saturation ‘Sticky’ Status bit(1)

1 = Accumulator B is saturated or has been saturated at some time0 = Accumulator B is not saturated

bit 11 OAB: OA || OB Combined Accumulator Overflow Status bit1 = Accumulators A or B have overflowed0 = Neither Accumulators A or B have overflowed

bit 10 SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit(1,4)

1 = Accumulators A or B are saturated or have been saturated at some time in the past0 = Neither Accumulator A or B are saturated

bit 9 DA: DO Loop Active bit1 = DO loop in progress0 = DO loop not in progress

bit 8 DC: MCU ALU Half Carry/Borrow bit1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)

of the result occurred0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized

data) of the result occurred

Note 1: This bit can be read or cleared (not set).2: The IPL bits are concatenated with the IPL bit (CORCON) to form the CPU Interrupt Priority

Level (IPL). The value in parentheses indicates the IPL if IPL = 1. User interrupts are disabled whenIPL = 1.

3: The IPL Status bits are read-only when NSTDIS = 1 (INTCON1).4: Clearing this bit will clear SA and SB.



bit 7-5 IPL: CPU Interrupt Priority Level Status bits(2)

111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled110 = CPU Interrupt Priority Level is 6 (14)101 = CPU Interrupt Priority Level is 5 (13)100 = CPU Interrupt Priority Level is 4 (12)011 = CPU Interrupt Priority Level is 3 (11)010 = CPU Interrupt Priority Level is 2 (10)001 = CPU Interrupt Priority Level is 1 (9)000 = CPU Interrupt Priority Level is 0 (8)

bit 4 RA: REPEAT Loop Active bit1 = REPEAT loop in progress0 = REPEAT loop not in progress

bit 3 N: MCU ALU Negative bit1 = Result was negative0 = Result was non-negative (zero or positive)

bit 2 OV: MCU ALU Overflow bitThis bit is used for signed arithmetic (2’s complement). It indicates an overflow of a magnitude thatcauses the sign bit to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation)0 = No overflow occurred

bit 1 Z: MCU ALU Zero bit1 = An operation that affects the Z bit has set it at some time in the past0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)

bit 0 C: MCU ALU Carry/Borrow bit1 = A carry-out from the Most Significant bit of the result occurred0 = No carry-out from the Most Significant bit of the result occurred

REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED)

Note 1: This bit can be read or cleared (not set).2: The IPL bits are concatenated with the IPL bit (CORCON) to form the CPU Interrupt Priority

Level (IPL). The value in parentheses indicates the IPL if IPL = 1. User interrupts are disabled whenIPL = 1.

3: The IPL Status bits are read-only when NSTDIS = 1 (INTCON1).4: Clearing this bit will clear SA and SB.



REGISTER 3-2: CORCON: CORE CONTROL REGISTER

U-0 U-0 U-0 R/W-0 R/W-0 R-0 R-0 R-0— — — US EDT(1) DL

bit 15 bit 8

R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0SATA SATB SATDW ACCSAT IPL3(2) PSV RND IF

bit 7 bit 0

Legend: C = Clearable bitR = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’

bit 15-13 Unimplemented: Read as ‘0’bit 12 US: DSP Multiply Unsigned/Signed Control bit

1 = DSP engine multiplies are unsigned 0 = DSP engine multiplies are signed

bit 11 EDT: Early DO Loop Termination Control bit(1)

1 = Terminate executing DO loop at end of current loop iteration0 = No effect

bit 10-8 DL: DO Loop Nesting Level Status bits111 = 7 DO loops active•••001 = 1 DO loop active000 = 0 DO loops active

bit 7 SATA: ACCA Saturation Enable bit1 = Accumulator A saturation enabled0 = Accumulator A saturation disabled

bit 6 SATB: ACCB Saturation Enable bit1 = Accumulator B saturation enabled0 = Accumulator B saturation disabled

bit 5 SATDW: Data Space Write from DSP Engine Saturation Enable bit1 = Data space write saturation enabled0 = Data space write saturation disabled

bit 4 ACCSAT: Accumulator Saturation Mode Select bit1 = 9.31 saturation (super saturation)0 = 1.31 saturation (normal saturation)

bit 3 IPL3: CPU Interrupt Priority Level Status bit 3(2)

1 = CPU Interrupt Priority Level is greater than 70 = CPU Interrupt Priority Level is 7 or less

bit 2 PSV: Program Space Visibility in Data Space Enable bit1 = Program space visible in data space0 = Program space not visible in data space

bit 1 RND: Rounding Mode Select bit1 = Biased (conventional) rounding enabled0 = Unbiased (convergent) rounding enabled

bit 0 IF: Integer or Fractional Multiplier Mode Select bit1 = Integer mode enabled for DSP multiply ops0 = Fractional mode enabled for DSP multiply ops

Note 1: This bit will always read as ‘0’.2: The IPL3 bit is concatenated with the IPL bits (SR) to form the CPU Interrupt Priority Level.



3.5 Arithmetic Logic Unit (ALU)The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 ALU is 16 bits wide and is capable of addition,subtraction, bit shifts and logic operations. Unlessotherwise mentioned, arithmetic operations are 2’scomplement in nature. Depending on the operation, theALU can affect the values of the Carry (C), Zero (Z),Negative (N), Overflow (OV) and Digit Carry (DC) Statusbits in the SR register. The C and DC Status bits operateas Borrow and Digit Borrow bits, respectively, forsubtraction operations.

The ALU can perform 8-bit or 16-bit operations,depending on the mode of the instruction that is used.Data for the ALU operation can come from the Wregister array or data memory, depending on theaddressing mode of the instruction. Likewise, outputdata from the ALU can be written to the W register arrayor a data memory location.

Refer to the “dsPIC30F/33F Programmer’s ReferenceManual” (DS70157) for information on the SR bitsaffected by each instruction.

The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 CPU incorporates hardware support for both multipli-cation and division. This includes a dedicated hardwaremultiplier and support hardware for 16-bit-divisor division.

3.5.1 MULTIPLIERUsing the high-speed, 17-bit x 17-bit multiplier of theDSP engine, the ALU supports unsigned, signed ormixed sign operation in several MCU multiplicationmodes:

• 16-bit x 16-bit signed• 16-bit x 16-bit unsigned• 16-bit signed x 5-bit (literal) unsigned• 16-bit unsigned x 16-bit unsigned• 16-bit unsigned x 5-bit (literal) unsigned• 16-bit unsigned x 16-bit signed• 8-bit unsigned x 8-bit unsigned

3.5.2 DIVIDERThe divide block supports 32-bit/16-bit and 16-bit/16-bitsigned and unsigned integer divide operations with thefollowing data sizes:

• 32-bit signed/16-bit signed divide• 32-bit unsigned/16-bit unsigned divide• 16-bit signed/16-bit signed divide• 16-bit unsigned/16-bit unsigned divide

The quotient for all divide instructions ends up in W0 andthe remainder in W1. 16-bit signed and unsigned DIVinstructions can specify any W register for both the 16-bitdivisor (Wn) and any W register (aligned) pair(W(m + 1):Wm) for the 32-bit dividend. The dividealgorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the samenumber of cycles to execute.

3.6 DSP EngineThe DSP engine consists of a high-speed, 17-bit x17-bit multiplier, a barrel shifter and a 40-bit adder/subtracter (with two target accumulators, round andsaturation logic).

The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 is a single-cycle instruction flow architecture; there-fore, concurrent operation of the DSP engine with MCUinstruction flow is not possible. However, some MCU ALUand DSP engine resources can be used concurrently bythe same instruction (for example, ED, EDAC).

The DSP engine can also perform inherentaccumulator-to-accumulator operations that require noadditional data. These instructions are ADD, SUB andNEG.

The DSP engine has options selected through bits inthe CPU Core Control register (CORCON), as listedbelow:

• Fractional or integer DSP multiply (IF)• Signed or unsigned DSP multiply (US)• Conventional or convergent rounding (RND)• Automatic saturation on/off for ACCA (SATA)• Automatic saturation on/off for ACCB (SATB)• Automatic saturation on/off for writes to data

memory (SATDW)• Accumulator Saturation mode selection

(ACCSAT)

A block diagram of the DSP engine is shown inFigure 3-3.



TABLE 3-1: DSP INSTRUCTIONS SUMMARY

FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM

Instruction Algebraic Operation ACC Write BackCLR A = 0 YesED A = (x – y)2 NoEDAC A = A + (x – y)2 NoMAC A = A + (x * y) YesMAC A = A + x2 NoMOVSAC No change in A YesMPY A = x * y NoMPY A = x 2 NoMPY.N A = – x * y NoMSC A = A – x * y Yes

Zero Backfill

Sign-Extend

BarrelShifter

40-bit Accumulator A40-bit Accumulator B Round

Logic

X D

ata

Bus

To/From W Array

Adder

Saturate

Negate

32

3233

16

16 16

16

40 40

4040

Saturate

Y D

ata

Bus

40

Carry/Borrow Out

Carry/Borrow In

16

40

Multiplier/Scaler17-Bit



3.6.1 MULTIPLIERThe 17-bit x 17-bit multiplier is capable of signed orunsigned operation and can multiplex its output using ascaler to support either 1.31 fractional (Q31) or 32-bitinteger results. Unsigned operands are zero-extendedinto the 17th bit of the multiplier input value. Signedoperands are sign-extended into the 17th bit of themultiplier input value. The output of the 17-bit x 17-bitmultiplier/scaler is a 33-bit value that is sign-extendedto 40 bits. Integer data is inherently represented as asigned 2’s complement value, where the MostSignificant bit (MSb) is defined as a sign bit. The rangeof an N-bit 2’s complement integer is -2N-1 to 2N-1 – 1.

• For a 16-bit integer, the data range is -32768 (0x8000) to 32767 (0x7FFF) including 0.

• For a 32-bit integer, the data range is -2,147,483,648 (0x8000 0000) to 2,147,483,647 (0x7FFF FFFF).

When the multiplier is configured for fractionalmultiplication, the data is represented as a 2’scomplement fraction, where the MSb is defined as asign bit and the radix point is implied to lie just after thesign bit (QX format). The range of an N-bit 2’scomplement fraction with this implied radix point is -1.0to (1 – 21-N). For a 16-bit fraction, the Q15 data rangeis -1.0 (0x8000) to 0.999969482 (0x7FFF) including 0and has a precision of 3.01518x10-5. In Fractionalmode, the 16 x 16 multiply operation generates a1.31 product that has a precision of 4.65661 x 10-10.

The same multiplier is used to support the MCUmultiply instructions, which include integer 16-bitsigned, unsigned and mixed sign multiply operations.

The MUL instruction can be directed to use byte orword-sized operands. Byte operands will direct a 16-bitresult, and word operands will direct a 32-bit result tothe specified register(s) in the W array.

3.6.2 DATA ACCUMULATORS AND ADDER/SUBTRACTER

The data accumulator consists of a 40-bit adder/subtracter with automatic sign extension logic. It canselect one of two accumulators (A or B) as its pre-accumulation source and post-accumulationdestination. For the ADD and LAC instructions, the datato be accumulated or loaded can be optionally scaledusing the barrel shifter prior to accumulation.

3.6.2.1 Adder/Subtracter, Overflow and Saturation

The adder/subtracter is a 40-bit adder with an optionalzero input into one side, and either true or complementdata into the other input.

• In the case of addition, the Carry/Borrow input is active-high and the other input is true data (not complemented).

• In the case of subtraction, the Carry/Borrow input is active-low and the other input is complemented.

The adder/subtracter generates Overflow Status bits,SA/SB and OA/OB, which are latched and reflected inthe STATUS register:

• Overflow from bit 39: this is a catastrophic overflow in which the sign of the accumulator is destroyed.

• Overflow into guard bits, 32 through 39: this is a recoverable overflow. This bit is set whenever all the guard bits are not identical to each other.

The adder has an additional saturation block thatcontrols accumulator data saturation, if selected. Ituses the result of the adder, the Overflow Status bitsdescribed previously and the SAT(CORCON) and ACCSAT (CORCON) modecontrol bits to determine when and to what value tosaturate.

Six STATUS register bits support saturation andoverflow:

• OA: ACCA overflowed into guard bits • OB: ACCB overflowed into guard bits• SA: ACCA saturated (bit 31 overflow and

saturation)orACCA overflowed into guard bits and saturated (bit 39 overflow and saturation)

• SB: ACCB saturated (bit 31 overflow and saturation)orACCB overflowed into guard bits and saturated (bit 39 overflow and saturation)

• OAB: Logical OR of OA and OB• SAB: Logical OR of SA and SB

The OA and OB bits are modified each time datapasses through the adder/subtracter. When set, theyindicate that the most recent operation has overflowedinto the accumulator guard bits (bits 32 through 39).The OA and OB bits can also optionally generate anarithmetic warning trap when set and the correspond-ing Overflow Trap Flag Enable bits (OVATE, OVBTE) inthe INTCON1 register are set (refer to Section 7.0“Interrupt Controller”). This allows the user applica-tion to take immediate action, for example, to correctsystem gain.



The SA and SB bits are modified each time datapasses through the adder/subtracter, but can only becleared by the user application. When set, they indicatethat the accumulator has overflowed its maximumrange (bit 31 for 32-bit saturation or bit 39 for 40-bitsaturation) and will be saturated (if saturation isenabled). When saturation is not enabled, SA and SBdefault to bit 39 overflow and thus, indicate that a cata-strophic overflow has occurred. If the COVTE bit in theINTCON1 register is set, SA and SB bits will generatean arithmetic warning trap when saturation is disabled.The Overflow and Saturation Status bits can optionallybe viewed in the STATUS Register (SR) as the logicalOR of OA and OB (in bit OAB) and the logical OR of SAand SB (in bit SAB)

High-Performance, 16-bit Digital Signal Controllersare for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and

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