Jack Erickson and Mark Warren Cadence Design Systems, Inc. IEDEC March 4, 2013 Modern System-on-Chip Challenges Require New Skills in Electronic Engineering Graduates
High-Level Synthesis Skill Development Needs - IEDEC
Apr 22, 2015
Presentation at the March 2013 IEDEC conference in Santa Clara, CA. Outlines the need for hardware design to move up in abstraction to SystemC and high-level synthesis, and the main barrier left preventing this - a rare combination of skills. The best place to address this skill set gap is in university curricula.
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Jack Erickson and Mark WarrenCadence Design Systems, Inc.IEDECMarch 4, 2013
Modern System-on-Chip Challenges Require New Skills in Electronic Engineering Graduates
2 © 2013 Cadence Design Systems, Inc. All rights reserved.
The design productivity gap
Design Productivity (20-25% CAGR)
Gates / cm2 Moore’s Law (59% CAGR)
0.35 μm 0.25μm 0.18μm 0.15μm 0.13μm 0.09 μm 0.065μm 0.045μm 0.032μm
Source: Semico Research Corp.
DesignGAP
Pro
du
ctiv
ity
/ Co
mp
lexi
ty
3 © 2013 Cadence Design Systems, Inc. All rights reserved.
One solution: more IP blocks
Source: IBS, Inc.
4 © 2013 Cadence Design Systems, Inc. All rights reserved.
Another solution: more engineers per project
Source: IBS, Inc.
5 © 2013 Cadence Design Systems, Inc. All rights reserved.
Abstraction must be raised to close the gap!Why hasn’t it happened yet?
10000
1000
100
10
1
20102000199019801970's
0.5 device~500K-1M gates
65nm device~50M-100M gates
Des
ign
Pro
duct
ivity
(ga
tes/
per)
RTL(Logic Synthesis)
Gates(Schematic
Capture)
Switches(SPICE)
System-Level(High LevelSynthesis)
GAP
Abstraction delivers designs more quickly, with less effort
6 © 2013 Cadence Design Systems, Inc. All rights reserved.
Cadence’s approach
Synthesize and verify entire design in IEEE SystemC with transaction-level models (TLM)
Embedded RTL Compiler synthesis and connected design, verification, and implementation to ensure closure
Extend metric-driven verification methodology to start at TLM
ECOAnytime
Incisive Metric-Driven Verification
SystemC
C-to-Silicon Compiler
SoC FPGA
RTL
Deliver the next quantum leap in productivity
7 © 2013 Cadence Design Systems, Inc. All rights reserved.
• SystemC is now an IEEE standard• Modern HLS supports the full datapath-control spectrum
Challenges in moving to higher-abstraction design and verification
Robust Design Support
• Embedded logic synthesis guides some HLS tools• Still work to do – physical, flow development, etc.
Quality of Results
• Multi-level metric-driven verification methodology• Adoption just starting – seeing good returns
Verification Methodology
• Rare combination of skills today• Need to develop new breed of engineerSkills
8 © 2013 Cadence Design Systems, Inc. All rights reserved.
New combination of skills required
Block Initial design
Refined design
Gain
ECC 17.637 mm2 1.035 mm2 17 X
Encoder 0.160 mm2 0.065 mm2 2.46 X
Decoder 17.477 mm2 0.970 mm2 18 X
SystemC Constraints
Hardware architecture designHardware micro-architecture for
QoRC++SystemCHLS tool operationRTL synthesis optimization
conceptsSource: ITRI, “Building a NAND flash controller with high-level synthesis”
9 © 2013 Cadence Design Systems, Inc. All rights reserved.
Difficult for engineers to find time for training in the commercial sector…
Source: IBS, Inc.
10 © 2013 Cadence Design Systems, Inc. All rights reserved.
Courses and curricula available today
11 © 2013 Cadence Design Systems, Inc. All rights reserved.
Courses and curricula available today
12 © 2013 Cadence Design Systems, Inc. All rights reserved.
Courses and curricula available today
13 © 2013 Cadence Design Systems, Inc. All rights reserved.
Resources availableEnabling HLS course development
14 © 2013 Cadence Design Systems, Inc. All rights reserved.
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