High-level Synthesis and System Synthesis SOURCES- Mark Manwaring Kia Bazargan Giovanni De Micheli Gupta Youn-Long Lin Camposano, J. Hofstede, Knapp, MacMillen.

High-level Synthesis and

System SynthesisSOURCES- Mark ManwaringKia BazarganGiovanni De Micheli GuptaYoun-Long Lin

Camposano, Camposano, J. Hofstede, J. Hofstede, Knapp,Knapp,MacMillenMacMillenLinLin

Why the level of automation must go up Why the level of automation must go up and up?and up?

What Went Wrong with early What Went Wrong with early approaches to design automation ?approaches to design automation ?

1. Too much emphasis on incremental work on algorithms and point tools

2. Unrealistic assumption on component capability, architectures, timing, etc

3. Lack of quality-measurement from the low level

4. Too many promises on fully automated system (silicon compiler??)

È¸·ÎÀÇ µ¿ÀÛÀû±â¼ú

IN

+ +DDOUT

Flow graph TransformationSimulation

D

OUT

IN D D

Flow graph Database

+

reg

reg

shift+reg

Hardware Mapping

Assignment / Scheduling

Time

Adder2Adder1

Shift

1 2 3 4 5 6 7

* * * * ** * * * ** * *

EstimationMin Bounds On Hardware

2 Adders 6 Registers 2 Buses

Silicon Compilation

Example of a Silicon Compiler SystemExample of a Silicon Compiler System

Initial specification

Benchmarks for a silicon compiler

benchmark mult(*) add(+) sub(- ) critical pathcascade 7 7 . 6

fir 11 11 10 . 11iir5 10 10 . 8

wavel e t 7 8 3 8

VLSI Design ToolsVLSI Design Tools• Design Capturing/Entry• Analysis and Characterization• Synthesis/Optimization

• Physical (Floor planning, Placement, Routing)• Logic (FSM, Retiming, Sizing, DFT)• High Level(RTL, Behavioral)

• Management

Design Methodology Progress

Capture and Simulate

Describe and Synthesize

Specify and ???

Productivity

Re-Targetability

Correctness

Why Synthesis?

Unsynthesizability

Performance Loss

Inertial

Why not Synthesis?

Structural Behavioral

Physical

X’tor

Gate

RTL

Block

Boolean

FSM

Algorithm

GDSII

Placement

Floorplan

Y-ChartDan D Gajski


Physical

X’tor

Gate

RTL

Block

Boolean

FSM

Algorithm

GDSII

Placement

Floorplan

LayoutSynthesis


Physical

X’tor

Gate

RTL

Block

Boolean

FSM

Algorithm

GDSII

Placement

Floorplan

LogicSynthesis


Physical

X’tor

Gate

RTL

Block

Boolean

FSM

Algorithm

GDSII

Placement

Floorplan

High-LevelSynthesis

Target ArchitecturesTarget Architectures• Bus-based

• Multiplexer-based

• Register file

• Pipelined

• RISC, VLIW

• Interface Protocol

Goal of synthesis for future Goal of synthesis for future systemssystems

FromBehavioral specification at ‘System Level’

(Algorithms)To

Structural implementation at ‘Register Transfer Level’ of Data path (ALU’s, REG’s, MUX’s) and

Controller

• Generally restricted to a single process• Generally data path is optimized; controller is by-

product

Levels of Abstraction

In Camposano• Behavioral• Register-Transfer

(RTL)• Logic

Our Abstraction levels• System• Register• Logic

Abstraction levels

Level Behavior StructureSpecification System specification

System Algorithms CPU’s, MEM’sBUS’s

Register (RTL) Registertransfers

REG’s, ALU’s, MUX’s

Logic Booleanexpressions

Gates,flip-flops

Circuit Transferfunctions

Transistors

SystemSystem

High-level

Logic

Physical

Synthesisstep

Level Behavior Structure

Intermediate Representation

* *+

Control Flow Graph

Data Flow Graph

What are possible levels of What are possible levels of synthesis?synthesis?

What are possible styles?What are possible styles?

How to automate big How to automate big tasks?tasks?

Layout SynthesisLayout Synthesis

Compass Placement & Routing ( 0.6µm gate array)

Layout Level

LogicLogic Synthesis Synthesis

Reminder about Reminder about blocks and blocks and

connections in connections in data pathdata path

Variants of simple FSMD architectures

StuursignalenBesturing Data-pad

Statussignalen


control

Controlling /activation pulses

Data Path


Status signals

control Data Path

IRInstructie

Statussignalen


Variants of simple FSMD architectures

control


Data Path

Status signals

Instructions

FSM with Data Path (FSMD)

FSMDataPath

FSMDataPath

FSMDataPath

Interactive FSMDs

Details of control signals

controls:

Reg_EO Enable Output

Reg_EI Enable Input

RegFile_EI RegFile_SI 

Register; a) RTL level b) with control signal details

Control of register files

p = l og(k)2

*

012

k-1

*

012

k-1

RegFile

RegFile_SI

RegFile_SO1

RegFile_EI

RegFile_EO1

Clock

a) b)

* *

RegFile_EO2

RegFile_SO2p

p

p

nn

n

n

n

n

Figuur 6.9: Register-file met twee uitgangen a) RTL-niveau b) Met stuursignalen

Door de besturing te sturen signalen:

RegFile_EO1 RegFile_SO1 

RegFile_EO2 RegFile_SO2 

RegFile_EI RegFile_SI 

control signals:

RegFile_EO1

RegFile_SO1 

RegFile_EO2

RegFile_SO2 

RegFile_EI

RegFile_SI Register; a) RTL level b) with control signal

details

The role of tri-state signals

* * *

Clock

Reg1 Reg2 Reg3Reg1_EO Reg2_EO Reg3_EO

n n

n

n

n

Clock

n n nIn1 In2 In3

Figuur 6.10a: 3 bronnen met 'tri-state' uitgangen Tri-state signals in buses instead of multiplexing

Scheduling and allocation problems are

similar

Multiplexing

Clock

Reg1 Reg2 Reg3

MUX

n n n

n n n

n n

Clock

In2 In3In1

Reg1_EO

Reg2_EO

Reg3_EO0 1 2

0

1

2

Communication with a memory

External data-busExternal address-bus

Internal bus

Pipeline Design IssuesPipeline Design Issues• Pipelined processor design

• Pipeline is an implementation issue.

• A behavioral representation should not specify the pipeline.

• Most processor instruction sets are conceived with an implementation in mind.

• The behavior is defined to fit an implementation model.

Semantics of variablesSemantics of variables

• Variables are implemented in hardware by:• Registers.• Wires.

• The hardware can store information or not.

• Cases:• Combinational circuits.• Sequential circuits.

Semantics of variables

• Combinational circuits.

• Multiple-assignment to a variable.

• Conflict resolution.• Oring.• Last assignment.


Semantics of variables

• Sequential circuits.• Multiple-assignment to a variable.• Variable retains its value until reassigned.• Problem:

• Variable propagation and observability.


Example

• Multiple reassignments:• x= 0 ; x = 1 ; x = 0 ;

• Interpretations:• Each assignment takes a cycle. --> pulse.• x assumes value 0.• x assumes value 0 after a short glitch.


Timing semantics

• Most procedural HDLs specify a partial order among operations.

• What is the timing of an operation?• A posteriori model:

• Delay annotation.

• A priori model:• Timing constraints.• Synthesis policies.


Timing semantics(event-driven semantics)

• Digital synchronous implementation.

• An operation is triggered by some event:• If the inputs to an operation change

--> the operation is re-evaluated.

• Used by simulators for efficiency reasons.

Synthesis policyfor VHDL and Verilog

• Operations are synchronized to a clock by using a wait (or @) command.

• Wait and @ statements delimit clock boundaries.• Clock is a parameter of the model:

• model is updated at each clock cycle.

Verilog examplebehavior of sequential logic circuit

module DIFFEQ (x, y, u , dx, a, clock, start);

input [7:0] a, dx;

inout [7:0] x, y, u;

input clock, start;

reg [7:0] xl, ul, yl;

always

beginbegin

wait ( start);

while ( x < a )

begin

xl = x + dx;

ul = u - (3 * x * u * dx) - (3 * y * dx);

yl = y + (u * dx);

@(posedge clock);

x = xl; u = ul ; y = yl;

end

endmodule

Abstract models• Models based on graphs.

• Useful for:• Machine-level processing.• Reasoning about properties.

• Derived from language models by compilation.

Abstract modelsExamples

• Netlists:• Structural views.

• Logic networks• Mixed structural/behavioral views.

• State diagrams• Behavioral views of sequential logic models.

• Dataflow and sequencing graphs.• Abstraction of behavioral models.

Data flow graphs

• Behavioral views of architectural models.

• Useful to represent data-paths.

• Graph:• Vertices = operations.• Edges = dependencies.

Dataflow graph Dataflow graph ExampleExample

xl = x + dxul = u - (3 * x * u * dx) - (3 * y * dx)yl = y + u * dxc = xl < a

Example of Data Flow Graph continued

xl = x + dxul = u - (3 * x * u *

dx) - (3 * y * dx)yl = y + u * dxc = xl < a

Sequencing graphsSequencing graphs

• Behavioral views of architectural models.• Useful to represent data-path and control.• Extended data flow graphs:

• Operation serialization.• Hierarchy.• Control- flow commands:

• branching and iteration.• Polar: source and sink.

Example of sequencing graph

Example of HierarchyExample of Hierarchy

Example of branching

Example of iteration

diffeq {read (x; y; u; dx; a); repeat { xl = x +dx; ul = u - (3 * x * u* dx) - (3 * y * dx); yl = y +u dx; c = x < a; x = xl; u = ul; y = yl; } until ( c ) ;write (y);}

Example of iteration

Semantics of sequencing graphs

• Marking of vertices:• Waiting for execution.• Executing.• Have completed execution.

• Execution semantics:• An operation can be fired as soon as all its

immediate predecessors have completed execution

Vertex attributes• Area cost.• Delay cost:

• Propagation delay.• Execution delay.

• Data-dependent execution delays:• Bounded (e.g. branching).• Unbounded (e.g. iteration, synchronization).

Properties of sequencing graphs

• Computed by visiting hierarchy bottom-up.• Area estimateArea estimate:

• Sum of the area attributes of all vertices.• Worst-case - no sharing.

• Delay estimateDelay estimate (latency):• Bounded-latency graphs.• Length of longest path.

Summary on specification modelsSummary on specification models• Hardware synthesis requires specialized language support.

• VHDL and Verilog HDL are mainly used today:• Similar features.• Simulation-oriented.

• Synthesis from programming languages is also possible.• Hardware and software models of computation are different.

• Appropriate hardware semantics need to be associated with programming languages.

• Abstract models:• Capture essential information.

• Derivable from HDL models. • Useful to prove properties.

Control Control DesignDesign

Control 1

Control of• Registers• Functional units• Multiplexers and 3-state drivers• Memory

Control designControl design

Simple micro-programmed controllerSimple micro-programmed controller

MUX

INCRProgramcounter

MicrocodeROM Mode registers

Jump address

Control signals fromROM or data path

Control linesControl lines

Control 2

1. To avoid false combinational cycles, either the inputs or the outputs of the controller are registered.

2. Note the one cycle delay between a condition and the resulting reaction in the controller.

3. Controller can even be pipelined, • which can remove the controller from the critical path, • but increases the delay for the conditions.

Control design issuesControl design issues

Overview of Hardware Synthesis

converts the program text file into strings of tokens. Tokens can be specified by regular

expressions. In the UNIX world, the “lex” tools are popular for this.

•The syntax of a programming language is specified by a grammar. (A grammar defines the order and types of tokens.) This analysis organized streams of tokens into

an abstract syntax tree.

Overview of Hardware Synthesis

analyze the semantics, or meanings, of the program.

Generate a symbol table. Check for uniqueness of symbols and information about them.

determine the order and organization of operations

High-level Synthesis and System Synthesis SOURCES- Mark Manwaring Kia Bazargan Giovanni De Micheli Gupta Youn-Long Lin Camposano, J. Hofstede, Knapp, MacMillen.

Documents

level of automation

rtl level b

highlevel synthesisexample

possible levels of synthesis

design automation

possible styles

optimized controller

eoenable outputreg