hierarchical test tutorial - DATE-Conference · Source: Cisco Systems, VNI Global Mobile Data Traffic Forecast Update 2013 4 Mobile Source: Business Insider, December 2013. 2/19/2016

2/19/2016

1

Hierarchical Test for Today’s SOC and IoT

Yervant Zorian,

2

Agenda

Trends & Challenges

Hierarchical Test Solution

IP-Level TestPreparation

SOC-Level TestOptimization

Beyond SOC:IEEE Test Stnds.

Life-Cycle Test & Diagnosis

New Topics

Conclusion

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3

Data, Data, Data Higher Capacity, Faster Transfer, and Lower Cost

Traffic from wireless and mobile devices will exceed traffic from wired devices by 2016.

By 2017, the annual global IP traffic will surpass the zettabyte threshold (1.4 zettabytes).

Source: Cisco Systems, VNI Global Mobile Data Traffic Forecast Update 2013

43,570

55,553

68,892

83,835

101,055

120,643

0

20,000

40,000

60,000

80,000

100,000

120,000

140,000

2012 2013 2014 2015 2016 2017

IP T

raff

ic, P

eta

byt

es

pe

r M

on

th

Global IP Traffic

Source: Cisco Systems, VNI Global Mobile Data Traffic Forecast Update 2013

4

Mobile

Source: Business Insider, December 2013

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5

The Emerging Scene!

Infrastructuralcore

Internet of Things

Mobileaccess

Courtesy: J. Rabaey

The Cloud!

6

• Business Apps

• Enterprise Resource Management (ERP) Financials

• TechApps (design, eng, R&D)

• ERP HR

• Collaboration Apps

• Email

• Data analysis/mining apps

• Data Backup/archive

• Help Desk/IT Service Management

• Storage Capacity on-demand

• Application development

• IT Management (server network)

• Mobile Device management

What’s Moving to the Cloud

Cloud Computing Driving Growth of Mega Data

Centers

36% CAGR

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7

Cloud 2.0 for the Internet of Things Central Cloud for Ubiquitous Connectivity

Wo

rk C

lou

d

Personal CloudAway or on the move

Central Cloud H

om

e C

lou

d

source: IEEE ISSCC Conference, 2014

WiFi Mobile

8

Reducing Power in Data Centers: System Integration Enables New Micro Servers

Server Power Breakdown

CPU Power~1/3

Other ServerH/W~2/3

CPU architecture

Integration & Innovation

Traditional Server

Micro Server

Traditional Micro Server

64-bit CPUSoC

Micro server SoCs integrate 64-bit CPU, networking, security, storage with targeted workload application

acceleration & high-speed I/Os

64bit CPUSoC

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9

(iPhone, ’07)(Galaxy S, ’10)

(Nokia 9000, ’96)

Wireless Phone

• Voice →Voice communication with some applications

→Multimedia applications with voice communication

SmartphoneSmartphone

(DynaTAC 800x, ’73)

Voice OnlyVoice Only

(K610im, ’99)

i‐mode Phonei‐mode Phone

(J‐SH04, ’00)

Cam. PhoneCam. Phone

10

Products: SMART Everything

1980 1990 2000 2010 2020

Pro

duct

Com

plex

ity /

Cap

abili

ties

“SMART”

Convergence

2/19/2016

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11

352405 437

540594

607

815 834969

1,155

934

200 250 250340 400 400 442

500 500 533600

0

300

600

900

1,200

1,500

2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014

MHz

Mean

Median

Clock Frequency TrendsClock Frequencies Increase to Keep Up with Bandwidth and Functionality

Source: 2014 Synopsys Global User Survey

12

Coping with Moore’s Law

CMOSBipolar, NMOS ?

100nm

Fea

ture

siz

e (

nano

met

ers

)

PentiumProPentiumIII

Intel8080

Intel386

Pentium

1000nm

10nm

1nm1970 1980 1990 2001 2010 2020 2030 2040 2050

Intel486

IA-64

Courtesy: Pat Gelsinger

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13

IC Design Expensive and Difficult

32/28nm node 22/10nm node

Fab costs $3B $4B – 7B

Process R&D costs $1.2B $2.1B – 3B

Design costs $50M – 90M $120M – 500M

Mask costs $2M – 3M $5M – 8M

EDA costs $400M – 500M $1.2 – 1.5B

• Intensive customer/partner collaborative developments

Source: IBS, May 2011

14

Nothing New: Power Challenge

Page 14

Source: Intel

Multi-Core

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15

IP Re-Use

Challenge 2: Productivity Gap

Source: SEMATECH

Page 15

16

IP-based designEnabling system companies to design chips(Apple, Microsoft, Amazon, Google….)

• Assemble componentsfrom parameterized library

– Including

• Integrate

– Configurable processor core

– Memories (RAM, ROM)

– Special-purpose standardblocks (ASSPs)

– Glue logic

• Third-party special-purposelogic / MEMS / MEOS

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17

Drivers of Hierarchical Test

• Growing volume of IP in an SOC

• Increasing design complexity w multiple levels of hierarchy

• Exploding digital logic size

• Increasing types of IP blocks to realize standard functions

• Growing use of 3rd party IP

• Increasing use of advanced technologies

• Dispersing design teams globally

• Tight time-to-volume schedules

• Improving test & debug access throughout life cycle

18

• IP test based on direct access increases test time and cost• Ad hoc IP test access not scalable• Reduced pin access, flexible test scheduling & concurrent test needed

1. Growing Use of IP

0

100

200

300

400

500

600

700

800

900

65nm 40nm 28nm 20nm

145

245

455

882

IBS, 2012 July

Number of IP Blocks per Design

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19

1. Ad-hoc IP/Core Test Access Can’t Scale

Rely on direct I/O accessRely on direct I/O access

How to Access?

Limited I/O access for larger designs with many IP/cores and hierarchy

Direct I/O access is feasible only for small designs

20

2. Multi-Level Hierarchical Design

- Flat DFT approaches and centralized test management are expensive in area and design time

- Hierarchical DFT access and pattern reuse/ porting required

- Automated hierarchical level test sign-off required

GPU GraphicCore(s)

USB

HD-RAM

PCIe

CPUSub-Chip

Sub-Chip

* Small boxes are Self-Testable Interface IP

ATPGMemory Interface IP, Calibration & Repair

Design Centric Yield Analysis

Silicon Debug & Diagnostics

Memory Self-Test & Repair

Off

-Chi

pO

n-C

hip

AMS IP AMS IP

SRAM

SRAM

SRAM

SRAM Test-time and cost

optimization

CompressionCompression

Interface IPSelf-Test & Calibration

Memory Self-Test & Repair

SRAM

SRAM

Core

SRAMSRAM

Core

SRAMSRAM

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21

3. Exploding Digital Logic Size

• Increased test time and power consumption during test• Long test development time for flat designs• Divide & conquer: design partitioning and wrapping needed

1-100K

101-500K

501K-1M

1-2M

2-5M

5-10M

10-20M

20-50M

50-100M>100M

0%

20%

40%

60%

80%

100%

2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012

Synopsys Global User Survey, 2012

Design Size (in M gates) %

22

3. Exploding Digital Logic Size (cont.)

Longer ATPG runtimes

SoC not designed to handle power

during full chip test

Complex DFT and design planning

Controllability & observability at

core level needed

UDLScan

UDLScan

MemoryScan Wrapper

Hard IPMux I/O Wrapper

MemoryBIST Wrapper

Mem

oryB

IST + Mux I/O

Wrapper


Hard IPScan Wrapper

UDLScan

UDLScan

Hard

IPB

IST + Scan Wrapper

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23

UART

AMBA 2.0 AHB -> AMBA 3 AXI -> Network on Chip (NoC)

AMBA APB

GPIO

USBcontroller

Ethernetcontroller

SATAcontroller

PCIecontroller

4. Numerous Heterogeneous IP Types

DDRPHY

DDRcontroller

USBPHY

PCIePHY

SD/MMCcontroller

XAUIPHY

SATAPHYI2C

HDMIcontroller

HDMIPHY

AudioCodec

Audioprocessor

ADCsDACs

Signalprocessor

VideoFront End

Videoprocessor

Hard IP

MIPIcontrollers

D-PHYM-PHY

Soft IP

Embedded Memories

EmbeddedMemories

(SRAM, ROM,NVM)

Datapath

Logic Libraries

multi coreCPUGPU

Processor IP

24

4. Heterogeneous IP Market Segments

Microprocessors41%

DSP5%

Fixed Function(GPUs, Security)

14%

Wired and Wireless Interfaces

19%

Memory Cells/Blocks

10%

GP Analog/MS3%

Block Libraries1%

Physical Library3%

Other4%

Source: Gartner, 2013

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25

Functional I/O-only access

makes it difficult to develop test

SoC test integration is

done manually

BIST Engines & Debug Modes

Uncontrollable I/O impacts test

quality

4. Heterogeneous IP Test Challenges –Memory/AMS/Legacy IP

UDLScan

UDLScan

MemoryScan Wrapper


MemoryBIST Wrapper

Mem

oryB

IST + Mux I/O

Wrapper


Hard IPScan Wrapper

UDLScan

UDLScan

Hard

IPB

IST + Scan Wrapper

26

4. Heterogeneous IP Challenges –Embedded Measurement IP

• Power Management Controllers

• Temperature Sensors

• Radio Tuners

• Measurement Probes

• Clock Generators

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27

Functional I/O-only access

makes it difficult to develop test

Temperature Sensors

No standard test Interfaces

Uncontrollable Instruments impacts test

quality

4. Embedded Measurement IP

UDLScan

UDLScan

MemoryScan Wrapper


MemoryBIST Wrapper

Mem

oryB

IST + Mux I/O

Wrapper


Hard IPScan Wrapper

UDLScan

UDLScan

Hard

IPB

IST + Scan Wrapper

28

5. Growth in 3rd Party IP Usage to Double

Strong Growth in 3rd Party IP Usage

Shorter Time Window for

New Product Launch

Escalating Design Costs

Increasing Design

Complexity

Source: Gartner, 2013

0% 15% 30% 45% 60% 75% 90%

WiredCommunication

Industrial

Automotive

Data Processing

WirelessCommunication

Consumer

2017

2012

Overall 3rd

party design IP use in 2012

Overall 3rd

party design IP use in 2017

Percentage of 3rd party IP blocks used in SoC design

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29

2000 2002 2004 2006 2008 2010 20142012

• Before 32nm, new process was introduced every other year

p‐SiON

HK/MG

* Source : ITRS, Samsung Electronics Co.

Integration

180nm

130nm

90nm

65nm

45nm

28nm32nm

20nm

14nm

Since then, a new process every year

30

IDF – Silicon Leadership

• Manufacturing & Test Quality are critical

• Modeling new types of defects (FinFET)

• Programmable test infrastructure, yield optimization and calibration techniques needed

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31

7. Globally Dispersed Design Teams

• Ad-hoc hand-off is error prone and time consuming• Automated sub-chip level integration and hierarchical sign-off

needed

0

50

100

150

200

250

5 816

38

81

165

190

220

IBS, 2012 August

Number of IP Blocks per Design

32

8. Shorter TTM and TTV

• Long development Time for ad-hoc bring up and silicon debug

• Uniform access and use of IEEE test standards reduce bring-up complexity and simplifies silicon debug

UDLScan

UDLScan

MemoryScan Wrapper


MemoryBIST Wrapper

Mem

oryBIST + M

ux I/O W

rapper


Hard IPScan Wrapper

UDLScan

UDLScan

Hard

IPBIST + Scan W

rapper

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33

0

10

20

30

40

50

60

70

80

90

100

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

Design Production Ramp-up Volume

YieldLearning Curve

Fab Yield Optimization

Yield Life Cycle CurveYield Life Cycle Curve

Yie

ld A

sses

smen

t (%

)

34

0

10

20

30

40

50

60

70

80

90

100

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18


New YieldLearningCurve

YieldLearning Curve

Design Yield Optimization



Yie

ld A

sses

smen

t (%

)

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35

0

10

20

30

40

50

60

70

80

90

100

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18



YieldLearning Curve




Yie

ld A

sses

smen

t (%

)

36

0

10

20

30

40

50

60

70

80

90

100

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18



YieldLearning Curve




Yie

ld A

sses

smen

t (%

)

2/19/2016

19

37

0

10

20

30

40

50

60

70

80

90

100

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18



YieldLearning Curve




Yie

ld A

sses

smen

t (%

)

38

Expect Many Types of “Things” Highly Fragmented Market

• By 2016, 50% of Internet of Things solutions will originate in startups less than three years old.

– Expect 10 billion shipments in 2020

– Many smart versions of existing product markets

– Key challenge: where to focus?

Source: Gartner, Preliminary, Sep 2013

2/19/2016

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39

Significant Growth in SensorsSensors Are Everywhere

Sensor Units to Grow to 30 Billion Units in 2017

0

5000

10000

15000

20000

25000

30000

2009 2010 2011 2012 2013 2014 2015 2016 2017

Consumer

Automotive

Computing

Smartphones

Feature Phones

Industrial

Other Communications

Source: Semico Research, 2013

30B Units

10B Units

40

How the Billions of “Things” are Connected…

IoT Edge DevicesAggregation Layers

(Hubs/Gateways)Remote Processing

(Cloud Based)

“Things” with sensors & actuators that monitor

and control

Connectivity & Interfaces to aggregate the edge data to

send to the cloud

Applications to analyze the data and offer cloud

services

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41

The IoT Opportunity GapThe IoT Opportunity is much largerAnalysts predictions forconnected devices (2020):

30 billion?50 billion?75 billion?

Rea

ch

Time

The IoT Market is growingNot new concept , it’s been around for >20 years1

Connected things > world population (6.8B)

Today

Silos of Things

1 Weiser, Mark (1991) “the Computer for the 21st Century”The term Internet of Things was proposed by Kevin Ashton in 1998

1 Weiser, Mark (1991) “the Computer for the 21st Century”The term Internet of Things was proposed by Kevin Ashton in 1998

42

Relationship: Users, Devices & ServicesFunctional Becomes IOT Data /Leveraging data enabled services revolution

Functional Data

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43

IoT Edge DevicesA Market Segmentation

SmartAppliances

Smart CitiesMetering

Safety &Security

Commerce

WearableInfotainment

Health &Fitness

Wea

rab

leD

evic

esM

ach

ine

to M

ach

ine

44

Wearable Devices

Google Glass 570mAh Li Polymer 1 days

Samsung Gear S Smart Watch 300mAh Li-Ion 2 days

Samsung Gear Fit Smart Watch 210mAh Li Polymer 4-5 days

Starkey Hearing Aid 91 - 630mAh Zinc Air 3-22 days

source: IEEE CS & ComSoc Joseph A. Paradiso, Thad Starner 2005

Laptop Computing Technology Improvements

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45

A Better Source Of PowerWe Have Potential!

Implanted Glucose Cells + Body Heat

Shoe Insert + Walking Motion

source: Joseph A. Paradiso, Massachusetts Institute of Technology Media Lab,Thad Starner, Georgia Institute of Technology, GVU Center

46

Bodies In Motion…

Walking the streetsEnergy harvested: 1 square generates up to 2.1 watts

Stepping in your shoesEnergy harvested 7- 67W possible but practically around 1W

Wearing clothesEnergy harvested: uW

Shaking that thingEnergy harvested: 5-12 W

source: postscapes.com

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47

Implanted Device RF/Thermal/Piezo Powered

Ear implants

• Energy requirements– active 500 μs per minute ~ 60 μJ

• Energy content of an implantable Li-ion battery is ~200mAh (Quallion)– would last 1*E+5 hrs = 11.4 years!!

48

Implanted Device RF/Thermal/Piezo Powered

• Exploring MIM Cap capabilities

• MIM Cap: 38 fF / μm2– 4 mm x 4 mm -> C = 0.6 μF

– Total Energy = 2.7 μJ @ 3V

• Energy requirements– active 500 μs per minute ~ 60 μJ

– NOT feasible with MIM

– BUT easy with SuperCaps

• Harvesting Piezoelectric (blood pressure) or thermal energy– Blood pressure @.37W can easily

sustain energy needed

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49

Wearable Systems Thermally Powered

Source: Skinny player URL. Designers: Chih-Wei Wang and Shou-His Fu http://www.energyharvestingjournal.com/articles/body-heat-powered-music-player-00002892.asp?sessionid=1

• Low power embedded processors, along with innovative energy harvesting and storage technologies will make many autonomous, connected "Things" possible

50

Table of Contents

6%

15%

17%

29%

33%

0% 20% 40%

Other

Smartglass

Activity Tracker (Lifelog)

Smart/MobileHeadset/Headphone

Smartwatch

Portable Medical Devices

Wearable Devices/Fitness/Portable Medical Devices

20146%

6%

9%

11%

13%

19%

35%

0% 10% 20% 30% 40%

Other

Smart City, such asDigital Lighting

Machine-to-Machine

Smartmeter

EmbeddedVision/Sensor

Smart Home/ SmartAppliances

WearableDevices/Fitness/Portable

Medical Devices

Internet of Things

2014

What is the PRIMARY application of your design?GLOBAL 2014

Synopsys Global User Survey 2014

2014 N = 161 2014 N = 52

No historical data as these are new questions starting 2014

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51

Problems to solve for Market Acceleration

Interoperable Data and Objects

Internet Of Things

Rea

ch

SaaSM2M

Applications

Internet / broadband

Mobile Telephony

Secure and Trustworthy

Fixed Telephony Networks

Mobile internet

Internet of Things

TodaySilos of ThingsEverything nearly connects

Scale needs interoperability Interoperability needs StandardsSharing needs TrustTrust needs Identities & Security

Internet model

52

IoT – The Big Picture

“Normal” ThingteractionsOwn, share, use directly

User ServiceSecurity, privacy, ownership

Device ServiceConnectManage

Application developmentSecurity End to End

Services

Users

Things

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53

IoT Integration TrendsProcessor, Wireless, Power Management, Sensors…

High-End IntegrationHigh-end wireless (WiFi, Celluar, GPS), vision,

audio, voice, etc.

Low-End Microcontroller IntegrationBluetooth Smart, 802.15.4, and ISM wireless

CMOS Sensors (Cap Touch)

Sensor IntegrationIntegration of “Smarts” (Processor & NVM)

28nm

55nm

180nm

54

IoT: Extremely Challenging Design Constraints

54

Radio +

Front-End

ADC

32 bit Micro Controller

DAC

IoT node chipset

Power Mgmt

BB

MEMS

Design Constraints1. Signal Chain as complicated as a cell phone

2. Cost < 1/100th of a cell phone

3. Size < 1/1000th of a cell phone

4. Power Consumption < 1/1000th of a cell phone

Past Future

Time to Market <3-4yr <1-2yr

Cost of end chipset >> $1 << $1

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55

Automotive Electrification Drives the Use of ECUs

• Dozens of additional ECUs per car

• Functional qualification becoming more critical for safety

• Millions of lines of software code

• Validation and test needs to start as early as possible

Rapid Growth in New Electronic Systems

56

Automotive Electrification Drives the Use of ADAS

• ADAS design requires flexible, scalable, integrated development platforms

• A complete ecosystem of software, IP and design tools yields necessary design productivity

Advanced Driver Assistance Systems

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57

The Connected Automobile

Body / Comfort Systems

Chassis / SafetySystems

Infotainment Systems

Powertrain Systems

Camera (ADAS) Systems

Secure Cloud Access

Gateway

The Cloud:Data services,

reporting and tracking

Variety of IP• Ethernet QOS• USB 2.0 / 3.0• Floating-point and datapath• Audio Subsystem

CANCAN

58

Evolving Interface StandardsDriving IP Portfolio Evolution

2013 2014 / 20152012

PCIe 4.016Gb/s

v.1

PCIe 4.016Gb/s

v.1

PCIe 4.0V1.0

PCIe 4.0V1.0

DDR41600-2400

DDR41600-2400

DDR42400-2933

DDR42400-2933

DDR42933-3200

DDR42933-3200

LPDDR3LPDDR3

USBSSIC USBSSIC

HDMI 2.06.0 Gb/s

HDMI 2.06.0 Gb/s

MHL1.2

MHL1.2

HDMI 1.4bHDMI 1.4b HDMI 2.1HDMI 2.1

PCIe 3.0PCIe 3.0SATA 3.1

Portable AppsSATA 3.1

Portable AppsSATA ExpressSATA Express

Energy Efficient Ethernet

Energy Efficient Ethernet

802.3ba40G Base KR4

802.3ba40G Base KR4

802.3ap10GBASEKR4

802.3ap10GBASEKR4

D–PHY1.5G/sD–PHY1.5G/s

M–PHYGear4, 12G/s

M–PHYGear4, 12G/s

M–PHYGear3, 6G/s

M–PHYGear3, 6G/s

NVM ExpressNVM Express

Next-Generation USBNext-Generation USB

New IEEE standards forAutomotive NetworkingNew IEEE standards forAutomotive Networking

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59

Automotive Challenges

Reliability • Design for Six Sigma (DFSS)• Traceability of system requirements• Design for Six Sigma (DFSS)• Traceability of system requirements

Safety & Quality • ISO 26262 • Fault injection• ISO 26262 • Fault injection

Time to Market • Design iteration time• IP integration• Design iteration time• IP integration

DevelopmentCosts

• Supply chain optimization• HW/SW integration and verification• Supply chain optimization• HW/SW integration and verification

60

Automotive Solution

Improve Functional Safety, Robustness, Reliability and Quality of their Automotive Systems

Early SW Development

MechatronicsPower SystemsWire Harness

High Reliability IC and FPGA Design

Semiconductor IP

System and IC Level Fault Solutions

Virtual IC Modeling and Simulation

LED Lighting Design and Simulation

LBIST and MBIST

Complete Verification Environment

MCU Architecture Design

SW Security and Quality

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61

9. Cradle-to-Grave Life-Cycle Approach

• What is changing in the world of hierarchical design, and how can we adapt to these changes

• How do we leverage IEEE Test Standards to design, manufacture, and take care of systems

• What standards are getting real use

• What does the “developing world” look like in terms of IEEE standards

62

Test Stages

• Wafer sort

• Laser repair

• Silicon debug

• Package test (final test)

• Burn-in

• Field operation

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63

Agenda

Trends & Challenges






New Topics

Conclusion

64

Hierarchical Test Solution- Simple Two-Level Hierarchy: IP to SOC- Unified Test Access

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65

Subchip-Level Test Management

66

Top-Level Test Management

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67

Communication via IEEE Test Standards

68

Hierarchical Design & Verification

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69

IEEE Test Standards Projects

• 1149.1

• 1149.4

• 1149.5

• 1149.6

• 1149.7

• 1149.8.1

• 1450

• 1450.1

• 1450.2

• 1450.3

• P1450.4

• P1450.5

• 1450.6

• 1450.6.1

• P1450.6.2

• P1450.7

• P1450.8

• 1500

• 1532

• 1581

• 1687

• P1804

• P1838

70

Applications• IEEE Std 1500 – Core Wrapping

• IEEE Std 1450.6 – Core Test Language

• IEEE Std 1450 – STIL

• IEEE Std 1450.1 – Scan additions to STIL

• IEEE Std 1149.1 – Boundary Scan (JTAG)

• IEEE Std 1149.6 – High-speed Interconnect

• IEEE Std P1838 – 3D-IC

• IEEE Std 1687 – Instrument Access

AMS IP

Memory BIST

Digital Cores

Die Stacks

ManufacturingTest

Field Access

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71

Hierarchical Test Solution AdvantagesAccelerate SoC Testing, Improve Test QoR

• Unified hierarchical test solution for memory, digital logic and AMS IP cores, enables reduced pin count test

• Increased design productivity and ease of use due to test resource partitioning

• Improved portability enables IP test reuse and ensures quality

• Subchip-level test closure

• Flexible test scheduling enables concurrent testing, and thus, reduced test cost

• Improved quality due to test programmability, yield and calibration

72

Hierarchical Test Capabilities

• Hierarchical Test Solution to allow the following– IP-Level Test Preparation

– IP-Level Wrapping

– Multi-Level Test Management

– Pattern Porting: from IP to hierarchical-levels

– SOC Test Integration & Scheduling

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73

Agenda

Trends & Challenges




Beyond SOC:IEEE Test Stnds


New Topics

Conclusion

74

Benefits of IP/Core Wrapping

• Test Access/Isolation for IP/Cores in SoC allows– Test Access to core terminals

– Higher coverage for UDL via scan test

– Fast and easy reuse of IP Validated Test Programs providing major benefits in SoC development

• Additional BIST options allow– Extra savings in ATE costs through trade-off between ATE cost

and silicon area

– Major Test Program development cycle to become a simple BIST run

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75

IEEE Std 1500: Core Wrapping

• Hardware standard for core wrapping

• Defines wrapper and test-mode control

• Mandates specification in IEEE Std 1450.6 (CTL)

• Supported by IEEE Std 1450.x (STIL) for test patterns

76

Wrapping

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77

Wrapping

Each core with 100s or 1000s of

I/Os

78

Wrapping Features

Dedicated or Shared Maximize Register Reuse

= dedicated = shared = non-wrapper

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79

IEEE Std 1500 Hardware

WSP

Wrapper Serial Port

80


WIR

WSO

WSI

SelectWIR

WSP

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81


WIR

WBY

WBR

Decode

WSO

WSI

SelectWIR

WSP

82


WIR

WBY

WBR

Decode

WSO

WSI

SelectWIR

WSP

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83


WIR

WBY

WBR

Decode

WSO

WSI

SelectWIRWRSTN

CaptureWRShiftWR

UpdateWRWRCK

WSP

84


WIR

WBY

WBR

Decode

WSO

WSI

SelectWIRWRSTN

CaptureWRShiftWR

UpdateWRWRCK

WPI WPO

WPP

WSP

Wrapper Parallel Port

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85

Wrapper

IEEE 1500 Wrapper Overview

Core

WPI WPOtest

stimulitest

responses

functionalinputs

functionaloutputs

testin/outputs

functionalin/outputs

WSC

WSI WSOtest control

+ test stimulitest control

+ test responses

WBY

WIR

WB

R

WB

R

SelectWIR

86

1500 Wrapper General Structure

WIR

WBY

WBR

WDR0

WDRj

WRCK

WRSTN

WSI

SelectWIR

UpdateWR

CaptureWR

ShiftWR

WSOR

WSO

WPC1

WPCn

WPI0

WPIm

WPO0

WPOi

STAR 1500 Wrapper

Mandatory ports, registersOptional ports, registers

ID Register

CORE_IN1

CORE_INk

CORE_OUT1

CORE_OUTm

Core

CDR0

CDRp

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1500 Wrapper Instructions• Standard Instructions

Required– WS_BYPASS – Allows normal (functional) mode and puts the wrapper into bypass mode. – WS_INTEST – Allows internal testing using a single chain configuration in the WBR.– WS_EXTEST – Allows external test using a single chain configuration in the WBR.Optional– WP_EXTEST – Allows external test using a multiple scan chain configuration in the WBR.– WS_SAFE – Puts the core into a quiet mode and outputs a predefined static (safe) state from

all output ports. It also puts the WBR into bypass mode.– WS_CLAMP – Outputs a programmable static (safe) state from all output ports. It also puts

the wrapper into bypass mode.– WS_PRELOAD – Loads data into the single silent shift path of the WBR.– WP_PRELOAD – Loads data into the multiple silent shift path of the WBR.– WS_INTEST_SCAN – Allows internal testing by concatenation of the wrapper chain with a

single internal chain.• Specific Instructions

– WS_WBR_SEL - Selects wrapper boundary registers between WSI and WSO.– WH_DIRECT - Configures the cells to use parallel test inputs/outputs during a test.– WS_MODE_SEL – Configures the configuration of the cell.– WS_STATIC_SEL - Selects the static register for forcing values to user pins.– WS_STATIC – Configures the cells to force the content of the static register to corresponding

user pins.– WS_SCAN_SHIFT - Configures the cells to be automatically updated during shift.– WS_ID_SEL – Selects the unique ID of the wrapper.– WS_<CORE_CHAIN_ID>_SEL – Selects the core’s test chain between WSI and WSO.

88

Two Compliance Levels

• IEEE 1500 Prepared– Core does not have a complete IEEE 1500 wrapper function

– Core has a complete IEEE Information Model, which accurately describes the core’s tests, as well as provide all information on the basis of which the core could be made ‘IEEE 1500 Wrapped’ (either manually or automatically by tools)

• IEEE 1500 Wrapped– Core incorporates complete IEEE 1500 wrapper function

– Core has a complete Information Model, which accurately describes the core’s tests, as well as the wrapper and how to operate it

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89

IP-Level Test Preparationfor IEEE 1500 Wrapping

• Core (ports)– core at RTL level

• Specification (standard format)

– Specify the ports to be wrapped

– Specify WIR width

• Outputs– WBR, WIR and WBY

components in RTL format

Core

IEEE 1500 Wrapper

WBRWIRWBY

Core

90

IP-Level Test PreparationIEEE 1500 Access

• Cores (ports)– Core at RTL level

• Specification (standard format)

– Standard file with ports not to be wrapped

– Specify WIR width

• Outputs– WIR and WBY components in

RTL format

Core

IEEE1500Wrapper

WIRWBY

Core

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91

• Port information – digital, analog, clocks, resets, supplies, tie-offs, frequency, active level, direction, range, expand factor

• Chain information – test and DFT chains. IEEE 1500 access provided to test chains. DFT stitching script is generated for DFT chains.

• Chain order – physical ordering of pins included in test chains

• Analog stimulus – parameters of predefined analog stimulus (triangle, sin, constant)

• Test patterns – description of test mode, analog stimuli and input-output patterns for test chains

IP/Core Wrapping Specification

92

Memory IP Wrapping with BIST

• Advanced Self Test and Repair (STAR) engine for each group of lowest-level memory IP

• IEEE 1500 wrapper and standard interface to communicate all test, diagnosis, and repair info

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93

AMS IP Wrapping w BIST

ADC BIST contains

• SRAM – for storing the code appearance numbers

• User registers – for input data specified by user (number of samples, ideal number of codes, etc.)

• Internal registers – for storing the calculated parameter values (ROFFSET, RINL, PASS, etc.)

• Analyzer block – parameter evaluation for PASS/FAIL report

ADC BIST

Internalregisters

An

aly

zer

SRAM

User registersADC

Triangle-wave

ADCoutputs

PASS/FAILbit

Memory pins

Registers inputs

94

ADC Integration with Hierarchical Test

SoC

STAR Processor

Embedded Memory

JTAG TAP

IEEE 1500

STAR Server

1500 Wrapper

Analog Mixed Signal IP

1500 Wrapper

ADC

Server

ADC BIST

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95

Interface IP Ready for Hierarchical Test

• USB

• MIPI

• HDMI

• SATA

• PCIe

• DDR

• Ethernet

Faster test integration and re-use of IP patterns saves time and resourcesFaster test integration and re-use of IP patterns saves time and resources

96

AMS IP Test Preparation

• Embedded AMS/IP may be in three variants– “Lite”: no or minimal DfT problem for later

– “Integrated Test”: e.g. Interface IP with BIST/Loopback)

– “Self Test and Repair”: repair features included, e.g. trimming

• Generate IEEE1500 Wrapper for AMS/IP– IEEE1500 compliant

– Allows easy reuse of IP test patterns at SoC level

– Solves SoC test access issues

• Provide AMS/IP measurement / test / diagnostics / calibration / repair libraries– Developed by IP providers, reused by IP users

– Alignment of measurement and test methods

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97

IEEE Std 1450.6 (Core Test Language)

• A broad language supporting test hardware definition and specification

• Supports hierarchical DFT synthesis operations

• Maps pattern data to test access mechanism (TAM)

• Supports protocol porting (up the hierarchy)

Broad Acceptance and Successful Use Since 2005

Netlist

Protocols

Models

RTL

SynthesisRTL

RTL

Netlists,CTL Models

Netlists,CTL Models

Synthesis

Synthesis

98

CTL Required to Support DFT Synthesis

• “Parallel” scan chains (normal scan, for example)• Head synchronization (flop, latch)• Head clock source• Head clock polarity• Head clock timing• Tail synchronization (latch, flop)• Tail clock source• Tail clock polarity• Tail clock timing• Scan chain content and clock associations• Scan enable pipe-lining support and enablement• Compression• Protocols other than “capture – shift – update”• Clock connectivity information (e.g. OCC)• Semantic meaning behind clock chain (control) bits• Definition of synchronous clock domains

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99

IEEE Std 1450.0 and 1450.1 (STIL)• STIL defines pattern data

• IEEE Std 1450.0 defines simple pattern data

• IEEE Std 1450.1 defines extensions for scan

• CTL can port these patterns via protocol manipulation

100

Hierarchical Design Flow

TOP

CTL 2

STIL

STIL 2

Design Integration Validation

Simulation

Simulation

ATE

PassFail

PassFail

Diag

FA

FA

Core

CTL

STIL

1500Core

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101

Agenda

Trends & Challenges






New Topics

Conclusion

102

SoC Level Test Integration

Server is 1149.1 compliant, where:

• Wrappers are connected to Server

• WIRs are controlled by Server

• Patterns are ported from IP level to TAP level

IP2

Wrapper

SoC

IP1

Wrapper

Server

TAP

Patternporting

Patternporting

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103

Multi-Hierarchy Support

Complex hierarchies of designs with different types of IPs can be handled within the proposed infrastructure.

SoC

Sub-Server

TAP

Sub-Server

Sub-Server

Sub-Server

104

Save Development Time and ResourcesRe-use IP/core Patterns at SoC Level

Patterns Patterns

Patterns can be ported and validated at any design hierarchy levelPatterns can be ported and validated at any design hierarchy level

PatternsPatterns Patterns

IP

TA

PServer

Wrapper

IP

Wrapper

IP

Wrapper

IP

eFuse

Wrapper

IP

Wrapper

IP

Wrapper

IP

Sub-Server

IP Sub-chip SoC

Wrapper

IP

Sub-Server

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105

IoT Nodes Block Diagram

105

MEMS ADC

DAC

MicroController&

Base Band

Radio&

FE

Power Management / Energy Harvesting

Small devices with minimal processing capabilities

Four major components: Sensor Micro Controller Radio Energy Management

106

Variation of IoT Devices

106

MEMS ADC

DAC

MicroController&

Base Band

Radio&

FE


Very wide range of applications drive many types of IoT nodes

Solar, EM, Vibration, Air flow, Liquid flow, ….

Gyroscope, Accelerometer,Pressure/Temperature/Humidity/Altitude/… Sensor

WiFi, Zigbee, GSM, GPRS, Blue Tooth…..

AC Power, Short Burst battery, ….

From sophisticated to no data processing

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107

The Market Will Demand Integration

107

MEMS ADC

DAC

MicroController&

Base Band

Radio&

FE


Most IoT nodes start with discrete components Fast prototype for system and software development Fast TTM and design win

However, volume production will demand integration Smaller size, footprint Lower power Lower cost

108

Example IoT SoC Architectures

UART

GPIO

USB Host

OTG w/ Charge Detect

ARC EMxx

DAC / PWM / Timers

Internal Flash

ADC /Comparator

ARC EM Processor

I2C SPI

ROM

Radio (Bluetooth Smart / 802.15.4)

Sensor Subsystem

SRAM

MTP / EEPROMUART

GPIO

USB 2.0 Host

OTG w/ Charge Detect

System Logic

PWM / Timers

SRAM

ADC

ARC EMCo-Processor

I2C SPI

ROM

Radio (WiFi, Bluetooth)

LPDDR2/3

Application ProcessorARC HS38

Ext Flash Memory

Controller

10/100/1G Enet

GPU

Sensor Subsystem

MIPI SDMMC

NVM

Sensor

Power

System Logic NVM

ADC /Comparator

ARC EM Processor

I2C SPI

Sensor Subsystem

Radio (ISM, 802.15.4, Bluetooth Smart)

Audio

ROM

SRAM

High-End Edge Device Low-End Edge Device Smart Analog Device

• DDR, App Proc w/MMU, LCD/GPU, USB, Ethernet, MIPI

• 65nm to 28nm (some 40nm)

• Linux, Android

• WiFi, Bluetooth Smart Ready, 2G/3G

• IP: eFlash, NVM, USB, ADC

• 90nm 55nm & 40nm

• RTOS: FreeRTOS, Contiki, MQX

• Bluetooth Smart, 802.15.4

• IP: Power, Audio, Sensor

• 180nm some 130/110/90nm

• RTOS: None, Limited RTOS

• Bluetooth Smart, 802.15.4, etc

Corral the Market Fragmentation

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109

Improve Test QoRHigher Test Coverage, Lower Pattern Count

• Increased access at IP/core periphery

• Higher test quality and pattern efficiency

• Faster development of new tests with hierarchical access

IP Test User Defined Logic Test

110

Reduce Test CostOptimize Test Time and Power with Flexible Test Scheduling

Test Schedule 1 Test Schedule 2

User configurable test scheduling minimizes test time and cost User configurable test scheduling minimizes test time and cost

* IP/cores with same color are tested in parallel

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111

Increase ProductivityReduce Test Integration Time by Weeks

• Scalable hierarchical architecture

• Standard interface for all IP/cores

• Rings minimize signal routes and congestion

• Sub-server enables efficient interface and test closureT

AP

eFUSE

ServerSub-

serverSub-

server

112

Concurrent Test: SoC Test SchedulingProvide optimal test time by concurrent test taking into account the SoCdesign/test/resource limitations.

Idle timeSession 1 Session 2 Session 3

Time

Overall test time

Session 1 Session 2 Session 3Time

Idle time

Overall test time

Better Scheduling

PoorScheduling

Limitation

Limitation

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113

Concurrent Test: Types of Constraints and Limitations

• Resource conflict (use of shared TAMs or BISTs)

• Precedence constraints (e.g., IP2 should be run after completing the run on IP1)

• Power and area constraints (e.g., for a BIST run there is a limit on power consumption)

114

Ramp-up Production Faster – TTVTest Patterns, Silicon Repair and Diagnostics

• Creates tester-ready patterns

• Supports tester-based and interactive silicon debug

• Provides eFuse programming for calibration

• Compliant with 1687 for system level debugSilicon

DebuggerTester

Diagnostic Report

Board Silicon Browser

SoC withSTAR HierarchicalSystem

Diagnostic Report

USB-to-JTAG Dongle

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115

Hierarchical Test Solution Benefits

Address SoC test bottleneck of large designs/cores-reuse

Provide uniform interface to users w reduced pin count

Enable subchip level test closure

Accelerate Time-to-Volume w ease of silicon debug

Improve portability for both IP developers and IP users

Reduce test cost by flexible scheduling and concurrent test

Increase test quality by porting IP developers’ test solutions

116

Agenda

Trends & Challenges






New Topics

Conclusion

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117

1149.1Standard Test Access Port and Boundary-Scan Architecture

• Circuit architecture and protocol allowing easy board-and system-level interconnect testing to be automated and applied with limited tester access

• Very widely used test standard

• Basis for “off-shoot” standards

• Defines a BSDL

• Easy chip-level access leveraged for other things

• Recently revised

118

• Chip hardware and language standard

• Defines TAP (Test Access Port) of 4-5 wires with protocol for scan access

• Defines a boundary-scan register at chip top

• Defines a BSDL for board-level test

• Targeting chip and board test applications– Used for system-level access to many chip resources

IEEE Std 1149.1

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119

IEEE Std 1149.1 Connectivity

TestAccess

Port

DataRegisters

ClockIRUpdateIRShiftIRReset*SelectEnableShiftDRUpdateDRClockDR

TMS

TCK

TRST*

TDI

TDO

MSB LSB

MSB LSB

InstructionRegister

Selects

120

• Instruction Register selects scan path

• Supports multiple serial data scan paths

• Selected scan path coupled between TDI and TDO pins

• Boundary and Bypass Data Registers are required

Data Register Selection

TDOTDI

From InstructionRegister Decode

Selects

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121

What is IJTAG (IEEE 1687)?

• IEEE 1687: Standard for Access and Control of Instrumentation Embedded Within a Semiconductor Device

• Hardware Description Language– Defines Status/Control registers (memory mapping)

• “Function” Description Language– Primitives (Read/Write) and Flow Control

• What 1687 is not:– NOT BIST

– NOT a tool

– NOT a program

122

IEEE 1687 Target Objective

• 1687 describes access and control of on-chip “instruments”– ICL describes the hardware

– PDL describes the tests

ICL

PDL

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123

Language Components of IEEE 1687

123

Instrumentprocedures

Networkdescription

InstrumentConnectivityLanguage

Information Language Purpose

ProcedureDescriptionLanguage

Documents theprocedures to operatean instrument.

Documents the logicalnetwork which connectsthe instruments to thechip interfaces.

124

SOC Test Infrastructure Access –ATE/Board/System

SOC Test Infrastructure

ATE BScan Diags

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125

Benefits of 1687

• Enables REUSE of pattern/test– Instruments/Blocks / Sub-module / Chip / Board / System– ATE, BSCAN, ICT, Diagnosis

• Enables Automation– Verification, Test and Debug– Test Mapping– Test Data Collection

• Consistent/Complete documentation

126

1500 + 1149.1 = 1687

• 1500 addresses scanned and compression-based cores

• 1500 will support a 1687 application needing small amounts of test data

1500 P1687

1149.1

Tem

p

Sen

sor

Mem

ory

B

IST

TD

RT

DR

1149.1

Tem

p

Sen

sor

Mem

ory

B

IST

TD

RT

DR

Memory

Memory

Memory

Memory

1500

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127

Signaling

IEEE Std 1500• WRCK

• WRSTN

• CaptureWR

• ShiftWR

• UpdateWR

• WSI

• WSO

• Implied Select

• SelectWIRSelecting between WIR/DR

IEEE Std 1687• TCK

• Reset

• CaptureEn

• ShiftEn

• UpdateEn

• ScanIn

• ScanOut

• SelectEnabling access

128

1687 Connectivity

TDR = JTAG Test Data Register

Inst

rum

ent

Inst

rum

ent

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129

MUX In and Out Segments

SIB

TDOTDO

SIB

TDOTDO

130

The 1687 SIB

D QU

D QSC

TCK

TDI

fromScanOutTDO

toScanIn

Select

0

1

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131

The 1687 SIB

D QU

D QSC

TCK

TDI

fromScanOutTDO

toScanIn

Select

0

1

0

132

The 1687 SIB

D QU

D QSC

TCK

TDI

fromScanOutTDO

toScanIn

Select

0

1

1

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133

The 1687 SIB

SIB

ScanOutfromScanOut

Reset

ShiftEn

UpdateEn

TCK

ScanIn

toSelect

toScanIn

Test Data Register Segment

TDITDO

134

Scan Connectivity

TAP

TRST*

TMS

TCK

CaptureIR

ShiftIR

UpdateIR

Reset*

Select

CaptureDR

ShiftDR

UpdateDR

FSM SIB

ScanOutfromScanOut

Reset

ShiftEn

UpdateEn

TCK

ScanIn

toSelect

toScanIn

SIB

ScanOutfromScanOut

Reset

ShiftEn

UpdateEn

TCK

ScanIn

toSelect

toScanIn

1500

WIRWBYWBR

WSOWSI

SelectWIR

WRSTN

CaptureWR

ShiftWR

UpdateWR

WRCK

WPI WPO

1500

WIRWBYWBR

WSOWSI

SelectWIR

WRSTN

CaptureWR

ShiftWR

UpdateWR

WRCK

WPI WPO

Instruction Register grows longer with every WIR added to scan path

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135

1500 Connectivity

TAP

TRST*

TMS

TCK

CaptureIR

ShiftIR

UpdateIR

Reset*

Select

CaptureDR

ShiftDR

UpdateDR

FSM SIB

ScanOutfromScanOut

Reset

ShiftEn

UpdateEn

TCK

ScanIn

toSelect

toScanIn

1500

WIRWBYWBR

WSOWSI

SelectWIR

WRSTN

CaptureWR

ShiftWR

UpdateWR

WRCK

WPI WPO

NIB

ScanOut

Reset

ShiftEn

UpdateEn

TCK

ScanIn

toDataIn

136

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137

• CTL can describe the DFT architecture– Required for synthesis

• ICL can describe “instrument” access architecture

• New BSDL can describe “instrument” access architecture

• STIL can describe the patterns with embedded protocol

• PDL can describe the patterns with implied protocol– PDL is in 1687 and 1149.1

Current Language Choices

138138 Nov 4, 2009

Uses for languages across life cycle

Returns/Repair

Field

System Level

PCB

IC ATE

IC Silicon Debug

IC Simulation

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139

Total Hierarchical SOC Test Solution

1500

1450.6

1450

1149.1

BSDL

PDL

P1687

ICL

PDL

140

Agenda

Trends & Challenges






New Topics

Conclusion

2/19/2016

71

141

• Field failure diagnosis

142

• What’s really broken

2/19/2016

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143

• What’s really broken

• Board?• Package?• Die?

144

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145

• Different DFT structures

• Digital Logic• Memory• AMS • Embedded

Measurement

ET&RWrapper

ET&RWrapper

Memory

Memory

ET&R

Processor

ET&R

Processor

ET&RWrapper

Memory

ET&RWrapper

Memory

146

Agenda

Trends & Challenges






New Topics

Conclusion

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147

Reliability Faults

• Intermittent Faults:– unstable hardware activated by environmental changes (lower

voltage, temperature)

– often become permanent faults

– identifying requires characterization

– process variation – main cause of IF

• Transient Faults:– occur because of temporary environmental conditions

– neutrons and -particles

– power supply and interconnect noise

– electromagnetic interference

– electrostatic discharge

148

Reliability Faults (cont.)

• Infant Mortality– rate worsens due to transistor scaling effects and new process

technology and material

• Aging Induced Hard Failures– performance degradation over time (burn-in shows)

– degradation varies over chip-chip and core-core

• Soft Errors– Random logic still at risk

– RAM decreasing SEU per bit

• Low Vmin increases bit failures in memories

• Transient Errors, such as timing faults, crosstalk are major signal integrity problems

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149

Design for Reliability

• Technology– Leakage induced power mitigation

• Chip– Power mitigation

– Redundant elements

• System– Memory ECC

– Logic fault tolerance

150

MCU Growth Over Technology Nodes

0

200

400

600

800

1000

1200

1400

0100200300400

SBU Average/node

MCU Average/node

Expon. (SBUAverage/node)

Expon. (MCUAverage/node)

Source: iRoC

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151

SER Growth at SOC Level

0

0

0

1

10

100

1000

02004006008001000

Memory SER

Logic SER (Seq + Comb)

Expon. (Memory SER)

Expon. (Logic SER (Seq + Comb))

Source: iRoC

152

Robustness IP for ECC

• Standard ECC architecture provides single bit repair• RAM multi-bit upset probability depends on cell to cell distance

MemoryIPECC

generatorSyndromeGenerator

ErrorLogic

CorrectionBlock

code

bits

Data Bus

ErrorIndication

code

bits

Data Bus

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153

Advanced Transient Error Fault Tolerance

• Highly automated flow

• Multi-bit error detection and correction

• Configurable performance versus area trade-off

• User-defined minimum distance for memory bit interleaving

• Memory banking for wide instances

• Memory correlation with write mask

Define and generate the embedded memory configuration

Insert embedded test & repair wrapper

Replace Memory with ECC

• Transient errors not just limited to space applications

• More likely at 28nm and below process technology nodes

154

The Aging Problem

Today’s applications require large amount of

embedded memories that occupy the largest ratio

of SOC surface

It is crucial to guarantee the reliability of such ICs

over lifetime

One of the most important phenomena degrading

Nano-scale SRAMs reliability over time is related

to Negative bias temperature instability (NBTI),

which accelerates memory bit cell aging

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155

Agenda

Trends & Challenges


Lower-Level IPPreparation




New Topics

Conclusion

156

Hierarchical Test Solution Accelerate SoC Testing, Improve Test QoR, Reduce Cost

Automated test integration of all IP/cores in SoCRe-use of IP/core-level patterns

Increases Productivity

Higher test quality due to IP pattern efficiencyTest programmability with hierarchical access

ImprovesTest QoR

Reduced test time with flexible scheduling Improved yield with eFuse based calibration

ReducesCost