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Hiep Hong CS 147 Spring 2009 1 Intel Core 2 Duo
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Hiep Hong CS 147 Spring 2009 1 Intel Core 2 Duo. CPU Chronology 2.

Dec 23, 2015

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Page 1: Hiep Hong CS 147 Spring 2009 1 Intel Core 2 Duo. CPU Chronology 2.

Hiep HongCS 147Spring 2009

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Intel Core 2 Duo

Page 2: Hiep Hong CS 147 Spring 2009 1 Intel Core 2 Duo. CPU Chronology 2.

CPU Chronology

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CPU Chronology

Intel 4004 108 KHz 2300 transistors

Intel 8008 500-800 KHz 3500 transistors

Intel 8080 2 MHz 4500 transistors

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Pre-Intel 8086:

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CPU Chronology

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CPU Chronology

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CPU Chronology

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Dual-Core or Core 2 Duo

Core 2 Duo is a brand name by Intel. Dual-Core is a generic description

meaning two separate physical cores in one chip package.

Example: Pentium Dual Core, Core Duo and Core 2 Duo.

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Intel Core 2 Duo

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Page 9: Hiep Hong CS 147 Spring 2009 1 Intel Core 2 Duo. CPU Chronology 2.

Intel Core 2 Duo 64 bit computing. x86-64 instruction set. The second generation of dual-core

processors from Intel. Two independent processor cores. Share up to 6MB of L2 cache. Developed with a new Architecture

called Core Microarchitacture.

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Page 10: Hiep Hong CS 147 Spring 2009 1 Intel Core 2 Duo. CPU Chronology 2.

Inside Intel Core 2 Duo Die

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Intel Core 2 Duo

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Page 12: Hiep Hong CS 147 Spring 2009 1 Intel Core 2 Duo. CPU Chronology 2.

Sequence of processing

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Core Microarchitecture

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Core Microarchitecture

Advanced smart cache. Macro-fusion. Advanced digital media boost. Memory disambiguation. Advanced power gating.

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Core Microarchitecture

Advanced smart cache. Macro-fusion. Advanced digital media boost. Memory disambiguation. Advanced power gating.

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Advanced smart cache

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Advanced smart cache continued

If one core has minimal cache requirements, the other core can dynamically increase its share of L2 cache

Reduce cache misses. Improve performance.

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Page 18: Hiep Hong CS 147 Spring 2009 1 Intel Core 2 Duo. CPU Chronology 2.

Core Microarchitecture

Advanced smart cache. Macro-fusion. Advanced digital media boost. Memory disambiguation. Advanced power gating.

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Macro-Fusion

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Macro-Fusion continued

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Macro-Fusion continued

Enable common pair of instructions to be combined into a single instruction during decoding.

Reduce the total of executed instructions.

Allow processor to execute more instructions in less time.

Increase performance.

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Macro-Fusion continued

Without macro-fusion With macro-fusion

1 load eax, [mem1]

2 cmp eax, [mem2]

3 jne target

1 load eax, [mem1]

2 cmp eax, [mem2] + jne target

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Core Microarchitecture

Advanced smart cache. Macro-fusion. Advanced digital media boost. Memory disambiguation. Advanced power gating.

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Advanced Digital Media Boost

Improve performance when executing Streaming SIMD Extension (SSE, SSE2, SEE3) instructions.

Accelerate video, speech, image, speech and image, photo processing, encryption, financial, engineering and scientific applications.

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Advanced Digital Media Boost

128-bit Streaming SIMD Extension (SSE, SSE2, SEE3) instructions.

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Page 26: Hiep Hong CS 147 Spring 2009 1 Intel Core 2 Duo. CPU Chronology 2.

Core Microarchitecture

Advanced smart cache. Macro-fusion. Advanced digital media boost. Memory disambiguation. Advanced power gating.

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Memory Disambiguation

Accelerate the execution of memory-related instructions.

Load data for instructions about to be executed before all previous store instructions were executed.

Memory-related instructions that can be executed out of order.

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Memory Disambiguation continued

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Memory Disambiguation continued

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Core Microarchitecture

Advanced smart cache. Macro-fusion. Advanced Digital Media Boost. Memory disambiguation. Advanced power gating.

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Advanced Power Gating

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Advanced Power Gating continued

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Newer and better!

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References

http://www.intel.com http://wikipedia.org http://www.zdnet.com

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