Hi-performance Regulator IC Series for PCs Main Power ... · HG1 BOOT1+0.3 *1*2 V HG2 BOOT2+0.3 *1*2 V PGND1, PGND2 AGND±0.3 *1*2 V Power Dissipation1 Pd1 0.38 *3 W Power Dissipation2
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Hi-performance Regulator IC Series for PCs Main Power Supply ICs for Note PC (Linear Regulator Integrated) BD9528MUV
Description
BD9528MUV is a 2ch switching regulator controller with high output current which can achieve low output voltage (1.0V~5.5V) from a wide input voltage range (5.5V~28V). High efficiency for the switching regulator can be realized by utilizing an external N-MOSFET power transistor. A new technology called H3RegTM(High speed, High efficiency, High performance) is a Rohm proprietary control method to realize ultra high transient response against load change. SLLM (Simple Light Load Mode) technology is also integrated to improve efficiency in light load mode, providing high efficiency over a wide load range. For protection and ease of use, 2ch LDO (5V/100mA, 3.3V/100mA), the soft start function, variable frequency function, short circuit protection function with timer latch, over voltage protection, and Power good function are all built in. This switching regulator is specially designed for Main Power Supply of laptop PC.
*1 Do not however exceed Pd. *2 Instantaneous surge voltage, back electromotive force and voltage under less than 10% duty cycle. *3 Reduced by 3.0mW for each increase in Ta of 1 over 25 (when don’t mounted on a heat radiation board ) *4 Reduced by 7.0mW for increase in Ta of 1 over 25. (when mounted on a board 74.2mm×74.2mm×1.6mm Glass-epoxy PCB which has 1 layer.
(Copper foil area : 20.2mm2) *5 Reduced by 26.1mW for increase in Ta of 1 over 25. (when mounted on a board 74.2mm×74.2mm×1.6mm Glass-epoxy PCB which has 4 layers.
(1st and 4th copper foil area : 20.2mm2, 2nd and 3rd copper foil area : 5505mm2) *6 Reduced by 36.5mW for increase in Ta of 1 over 25. (when mounted on a board 74.2mm×74.2mm×1.6mm Glass-epoxy PCB which has 4 layers.
(All copper foil area : 5505mm2)
Operating conditions(Ta=25)
Parameter Symbol MIN. MAX. Unit
Terminal Voltage
VIN 5.5 28 V CTL -0.3 28 V
EN1, EN2, MCTL1, MCTL2 -0.3 5.5 V BOOT1, BOOT2 4.5 33 V
SW1, SW2 -0.3 28 V BOOT1-SW1, BOOT2-SW2, HG1-SW1, HG2-SW2 -0.3 5.5 V
Vo1, Vo2, PGOOD1, PGOOD2 -0.3 5.5 V MIN ON TIME TONmin - 150 nsec
This product should not be used in a radioactive environment.
Input Output CTL EN1 EN2 REG1(5V) REG2(3.3V) DC/DC1 DC/DC2 Low Low Low OFF OFF OFF OFF Low Low High OFF OFF OFF OFF Low High Low OFF OFF OFF OFF Low High High OFF OFF OFF OFF High Low Low ON ON OFF OFF High Low High ON ON OFF ON High High Low ON ON ON OFF High High High ON ON ON ON
※ CTL pin is connected to VIN pin with 1MΩ resistor(pull up) internal IC. ※ EN pin is connected to AGND pin with 1MΩ resistor(pull down) internal IC.
・VIN (30 pin) This is the main power supply pin. The input supply voltage range is 5.5V to 25V. The duty cycle of BD9528MUV is determined by input voltage and control output voltage. Therefore, when VIN voltage fluctuated, the output voltage also becomes unstable. Since VIN line is also the input voltage of switching regulator, stability depends on the impedance of the voltage supply. It is recommended to establish bypass capacitor and CR filter suitable for the actual application.
・CTL (9 pin) When CTL pin voltage is at least 2.3V, the status of the linear regulator output becomes active (REG1=5V, REG2=3.3V). Conversely, the status switches off when CTL pin voltage goes lower than 0.8V. The switching regulator doesn’t become active when the status of CTL pin is low, if the status of EN pin is high. (※CTL pin is connected to VIN pin with 1MΩ resistor(pull up) internal IC)
・EN1, 2 (21 pin, 4 pin) When EN pin voltage is at least 2.3V, the status of the switching regulator becomes active. Conversely, the status switches off when EN pin voltage goes lower than 0.8V. (※EN pin is connected to AGND pin with 1MΩ resistor(pull down) internal IC)
・REG1 (29 pin) This is the output pin for 5V linear regulator and also active in power supply for driver and control circuit of the inside. The standby function for REG1 is determined by CTL pin. The voltage is 5V, with 100mA current ability. It is recommended that a 10μF capacitor (X5R or X7R) be established between REG1 and GND.
・REG2 (28 pin) This is the output pin for 3.3V linear regulator. The standby function for REG2 is determined by CTL. The voltage is 3.3V, with 50mA current ability. It is recommended that a 10μF capacitor (X5R or X7R) be established between REG2 and GND.
・REF (12 pin) This is the setting pin for output voltage of switching regulator. This IC controls the voltage in the status of REF≒FB.
・FB 1, 2 (14 pin, 11 pin) This is the feedback pin from the output of switching regulator. This IC controls the voltage in the status of REF≒FB.
・Vo1 (27 pin) This is the output discharge pin, and output voltage feedback pin for frequency setting. When the voltage is beyond 4.4V
from the external power supply during operation, it supplies REG1. ・Vo2 (7 pin) This is the output discharge pin, and output voltage feedback pin for frequency setting.
・SS1, 2 (19 pin, 6 pin) This is the setting pin for soft start. The rising time is determined by the capacitor connected between SS and GND, and the fixed current inside IC after it is the status of low in standby mode. It controls the output voltage till SS voltage catch up the REF pin to become the SS terminal voltage.
・FS1, 2 (15 pin, 10 pin) This is the input pin for setting the frequency. It is available to set it in frequency range is 200KHz to 500kHz.
・ILIM1, 2 (17 pin, 8 pin) BD9528MUV detects voltage differential between SW and PGND, and set OCP. OCP setting current value is determined by the resistance value of ILIM pin. FET of various Ron is available.
・PGOOD 1, 2 (20 pin, 5 pin)
This is the open drain pin for deciding the output of switching regulator.
・MCTL1, 2 (18 pin, 16 pin) This is the switching shift pin for SLLM (Simple Light Load Mode). MCTL pin is at low level when it goes lower than 0.8V, and at high level when it goes higher than 2.3V.
(※MCTL pin is connected to AGND pin with 500kΩ resistor(pull down) internal IC)
This is the power supply pin for high side FET driver. The maximum voltage range to GND pin is to 35V, to SW pin is to 7V. In switching operations, the voltage swings from (VIN+REG1) to REG1 by BOOT pin operation.
・HG1, 2 (23 pin, 2 pin) This is the highside FET gate drive pin. It is operated in switching between BOOT to SW. In case the output MOS is 3ohm /the status of Hi, 2ohm/the status of Low, it is operated hi-side FET gate in high speed.
・SW1, 2 (24 pin, 1 pin) This is the ground pin for high side FET drive. The maximum voltage range to GND pin is to 30V. Switching operation swings from the status of BOOT to the status of GND.
・LG1, 2 (26 pin, 31 pin) This is the lowside FET gate drive pin. It is operated in switching between REG1 to PGND. In case the output MOS is 2ohm /the status of Hi, 0.5ohm/the status of Low, it is operated low-side FET gate in high speed.
・PGND1, 2 (25 pin, 32 pin) This is the ground pin for low side FET drive.
Explanation of Operation The BD9528MUV is a 2ch synchronous buck regulator controller incorporating ROHM’s proprietary H3REG CONTROLLA control system. Because controlling of output voltage by a comparator, high response is realized with not relying on the switching frequency. And, when VOUT drops due to a rapid load change, the system quickly restores VOUT by extending the TON time interval. Thus, it serves to improve the regulator’s transient response. Activating the Light Load Mode will also exercise Simple Light Load Mode (SLLM) control when the load is light, to further increase efficiency.
H3RegTM control
(Normal operation)
(VOUT drops due to a rapid load change)
(when VIN drops)
If VIN voltage drops because of the battery voltage fall, ontime tON and offtime tOFF is determined by the following formula: tON=VOUT/VIN×I/f and tOFF=(VIN-VOUT)/VIN×f so that tON lengthen and tOFF shorten to keep output voltage constant. However,
if VIN still drops and tOFF equals to tminoff (tminoff:Minimum OFF time, regulated inside IC) , because tOFF cannot shorten any
more, as a result output voltage drops. In H3RegTM system, lengthening tON time than regulated tON (lengthen tON time until FB>REF)
HG output is determined by the formula above.
After the status of HG is OFF, LG go on outputting until
output voltage become FB=REF.
When FB falls to a reference voltage (REF), the drop is
detected, activating the H3REG CONTROLLA
system.<Route A>
( )
When VOUT drops due to a rapid load change, and the
voltage remains below reference voltage after the
programmed tON time interval has elapsed (Output of a
comparator for output voltage control =H), the system
quickly restores VOUT by extending the tON time,
improving the transient response.<Route B> After VOUT
restores (FB=REF), HG turns to be OFF, and it goes back
enables to operate stable not to drop the output voltage even if VIN turns to be low. With the reason above, it is suitable for 2-cell battery.
Light Load Control
(SLLM)
(QLLM)
MCTL1 MCTL2 Control mode Running
L L SLLM PWM
L H QLLM PWM
H X PWM PWM
Timing Chart
• Soft Start Function
EN
SS
VOUT
IIN
TSS
Soft start time
Tss= REF×Css 2.3μA(typ)
[sec]
Incoming current
IIN= Co×VOUT Tss
[A]
Soft start is exercised with the EN pin set high. Current
control takes effect at startup, enabling a moderate
output voltage “ramping start.” Soft start timing and
incoming current are calculated with formulas (2) and
(3) below.
(Css: Soft start capacitor; Co: Output capacitor)
・・・(2)
・・・(3)
In SLLM, when the status of LG is OFF and the coilcurrent is within 0A (it flows to SW from VOUT.), SLLMfunction is operated to prevent output next HG. Thestatus of HG is ON, when FB falls below reference voltageagain.
In QLLM, when the status of LG is OFF and the coilcurrent is within 0A (it flows to SW from VOUT.), QLLMfunction is operated to prevent output next HG. Then, FB falls below the output programmed voltagewithin the programmed time (typ=40μs), the status of HGis ON. In case FB doesn’t fall in the programmed time, thestatus of LG is ON forcedly and VOUT falls. As a result,he status of next HG is ON.
FB
HG
LG
0A
REF
FB
HG
LG
0A
REF
LoadCOUT
*Attention: H3RegTMCONTROLLA monitors the supplying current from capacitor to load, using the ESR of output capacitor, and realize the rapid response. Bypass capacitor used at each load (Ex. Ceramic capacitor) exercises the effect with connecting to each load side. Do not put a ceramic capacitor on COUT side of power supply.
The BD9528MUV operates in PWM mode until SS pin reaches cramp voltage (2.5V), regardless of the control mode setting, in order to operate stable during the operation. .
Notes when waking up with CTL pin or VIN pin If EN pin is High or short (or pull up resistor) to REG1 pin, IC starts up by switching CTL pin, the IC might fail to start up (SCP function) with the reason below, please be careful of SS pin and REF pin capacitor capacity.
Delay SCP
PWM (Switching control signal)
1ms(typ.)
SCP circuit
BG
SCP_REF
SCP
CTL
REF
SS
REG1 REG2 FB
CTL(VIN)
REG1, REG2
BG
SCP_REF
REF
SSFB
REFFB
SS
(REF start-up time<SS start-up time)
(REF start-up time>SS start-up time)
REG1 UVLO cancellation
REG1 REG2
0.49V(typ)
SCP mask cancellation
SS
FB
SCP mask cancellation
FB starts up as SS reference
FB starts up as REF reference
After the end of SS wake-up,within SCP delay time (1ms), ifREF voltage does not reachSCP_REF(0.49V), SCP turnsON and shut down.
Inner reference
circuit
VIN
SCP function masked
SCP mask
SCP function is masked until SS pin reaches cramp voltage (2.5V).
※Passing a current larger than the inductor’s rated current will cause magnetic saturation in the inductor and decrease system efficiency. In selecting the inductor, be sure to allow enough margin to assure that peak current does not exceed the inductor rated current value. ※To minimize possible inductor damage and maximize efficiency, choose a inductor with a low (DCR, ACR) resistance.
2.Output Capacitor (CO) Selection
Please give due consideration to the conditions in formula (8) below for output capacity, bear in mind that output rise time must be established within the soft start time frame. Capacitor for bypass capacitor is connected to Load side which connect to output in output capacitor capacity (CEXT, figure above). Please set the soft start time or over current detecting value, regarding these capacities.
Note: Improper capacitor may cause startup malfunctions.
3. Input Capacitor (Cin) Selection
A low ESR capacitor is recommended to reduce ESR loss and maximize efficiency.
The inductor value is a major influence on the output ripplecurrent. As formula (4) below indicates, the greater the inductor orthe switching frequency, the lower the ripple current.
ΔIL=(VIN-VOUT)×VOUT
L×VIN×f[A]・・・(4)
The proper output ripple current setting is about 30% of maximumoutput current.
ΔIL=0.3×IOUTmax. [A]・・・(5)
L=(VIN-VOUT)×VOUT
ΔIL×VIN×f[H]・・・(6)
(ΔIL: output ripple current; f: switch frequency)
When determining the proper output capacitor, be sure to factor in theequivalent series resistance required to smooth out ripple volume and maintaina stable output voltage range. Output ripple voltage is determined as in formula (7) below.
(ΔIL: Output ripple current; ESR: CO equivalent series resistance)
※ In selecting a capacitor, make sure the capacitor rating allows sufficientmargin relative to output voltage. Note that a lower ESR can minimize outputripple voltage.
Co≦ Tss×(Limit-IOUT)
VOUT ・・・(8)
Tss: Soft start time Limit: Over current detection
Input Capacitor
The input capacitor selected must have low enough ESR resistance to fullysupport large ripple output, in order to prevent extreme over current. Theformula for ripple current IRMS is given in (9) below.
If load current 5A want to be realized with VIN=6~19V, VOUT=5V, f=400kHZ, L=2.5uH, RON=20mΩ, the formula would be below.
When VIN=6V, Iocp will be minimum(this is because the ripple current is also minimum) so that if each condition is input,
the formula will be the following: RILIM<109.1[kΩ]. ※To design the actual board, please consider enough margin for FET ON resistor dispersion, Coil inductor dispersion, IC over current reference value dispersion, frequency dispersion.
7. Relation between output voltage and TON time
The BD9528MUV, both 1ch and 2ch, are high efficiency synchronous regulator controller with frequency variable. TON time varies with Input voltage [VIN], output voltage [VOUT], and RFS of FS pin resistance. TON time is calculated with the following formula:
TON =k From TON time above, frequency on application condition is following:
Frequency = However, real-life considerations (such as the external MOSFET gate capacitor and switching speed) must be factored in as they affect the overall switching rise and fall time, so please confirm in reality by the instrument.
Detecting the ON resistance (between SW and PGNDvoltage) of MOSFET at low side, it set the over currentvoltage protection. Over current reference voltage (ILIM_ref) is determined as informula(12) below.
RILIM[KΩ]×RON[mΩ]
10×103
VIN
L
Co
VOUT
PGND
SW
RILIM
[nsec]・・・(14)
VOUT
VIN×
1
Ton[kHz]・・・(15)
0
0.5
1
1.5
2
2.5
0 20 40 60 80 100 120
RFS[kΩ]
ontim
e[u
s]
VIN=7V
VIN=12V
VIN=21V
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0 20 40 60 80 100 120
RFS[kΩ]
ontim
e[u
s]
VIN=7V
VIN=12V
VIN=21V
0
0.5
1
1.5
2
2.5
3
3.5
0 20 40 60 80 100 120
RFS[kΩ]
ontim
e[u
s]
VIN=7V
VIN=12V
VIN=21V
VOUT・RFS
VIN
However, the value, which set the over current protection actually, isdetermined by the formula (13) below.
①Because high pulse current rush into power loop, consisted of input capacitor Cin, Output inductor L, and Output capacitor Co, this part layout should be built, including GND pattern, at parts side (upper side). Also ,please avoid to draw via formation in power loop line. (The reason is that it will be a factor of noise because via oneself holds some nH parasitic inductance) ②FB pin has comparatively high impedance, so floating capacity should be minimum as possible. And feedback wiring from output should be taken properly, and put on shield, not going through around L (because of magnetic). Please be careful in drawing) ③Trace from SW node pin to inductor should be cut short . And both inductor element pattern should be kept away. (Closer wiring has SW node noise influence Vo by parasitic capacity between wiring ). This layout example shows that SW node is outside, but if the application board will be like that , SW node should be shielding, and consider the influence to other circuit. ④Input capacitor Cin should be placed cloase to IC with low inductance and low impedance . If that is difficult, please place a capacitor for high frequency removal with PKG size small like 0.1uF (ESL small). ⑤2 layer and 3 layer are plain GND, so connect from parts side GND to plain GND by low impedance with many via as possible. Inner GND is only for shielding, so that not to form loop for high current . ⑥Please take GND pattern space widely, and design layout to be able to increase radiation efficiency. ⑦FS pin nad ILIM pin has high impedance. External resistor should be connected to “Silent GND”.
1. This integrated circuit is a monolithic IC, which (as shown in the figure below), has P+ isolation in the P substrate and
between the various pins. A P-N junction is formed from this P layer and N layer of each pin, with the type of junction
depending on the relation between each potential, as follows:
When GND> element A> element B, the P-N junction is a diode.
When element B>GND element A, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual interference
among circuits, as well as operating malfunctions and physical damage. Therefore, be careful to avoid methods by which
parasitic diodes operate, such as applying a voltage lower than the GND (P substrate) voltage to an input pin.
2. In some modes of operation, power supply voltage and pin voltage are reversed, giving rise to possible internal circuit
damage. For example, when the external capacitor is charged, the electric charge can cause a VCC short circuit to the
GND. In order to avoid these problems, inserting a VCC series countercurrent prevention diode or bypass diode between
the various pins and the VCC is recommended.
3. Absolute maximum rating Although the quality of this IC is rigorously controlled, the IC may be destroyed when applied voltage or operating temperature exceeds its absolute maximum rating. Because short mode or open mode cannot be specified when the IC is destroyed, it is important to take physical safety measures such as fusing if a special mode in excess of absolute rating limits is to be implemented.
4.GND potential
Make sure the potential for the GND pin is always kept lower than the potentials of all other pins, regardless of the operating
mode.
5. Thermal design
In order to build sufficient margin into the thermal design, give proper consideration to the allowable loss (Power Dissipation)
in actual operation.
6. Short-circuits between pins and incorrect mounting position
When mounting the IC onto the circuit board, be extremely careful about the orientation and position of the IC. The IC may
be destroyed if it is incorrectly positioned for mounting. Do not short-circuit between any output pin and supply pin or ground,
or between the output pins themselves. Accidental attachment of small objects on these pins will cause shorts and may
damage the IC.
7. Operation in strong electromagnetic fields
Use in strong electromagnetic fields may cause malfunctions. Use extreme caution with electromagnetic fields.
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