© 2014 ANSYS, Inc. November 12, 2015 1 HFSS 3D Layout for 3D EM simulation of planar structure (PCB, RFIC, MMIC…) Alain Michel, ANSYS [email protected]
© 2014 ANSYS, Inc. November 12, 2015 1
HFSS 3D Layout for 3D EM simulation of planar structure (PCB, RFIC, MMIC…)
Alain Michel, ANSYS
© 2014 ANSYS, Inc. November 12, 2015 2
Two Design Interfaces
Both Require the Accuracy of 3D and HFSS
Mechanical CAD (MCAD)
Electrical Layout (ECAD)
© 2014 ANSYS, Inc. November 12, 2015 3
ANSYS HFSS Simulation workflow
• HFSS 3D MCAD interface as standard
• HFSS with 3D Layout Editor (Included)
• Automated Interface for Package, PCB, or Integrated Circuit design
• 3D Layout with Integrated HFSS solve
• DC Solver
• Passive/Causal Frequency Sweeps
• Embedded S-Parameters
• Native HFSS solves from Cadence Allegro, APD, SiP, and Virtuoso
• Full-wave SPICE circuit generation
• Planar EM (2.5D Method of Moments) (Included)
– Enabled with the HFSS solve license
• Linear circuit simulator (Included)
• RF Option Add-on (HB, Transient, Envelope…)
HFSS 2014
ECAD FEM
Interface
ECAD MoM
Interface
Full Linear
Circuit
Analysis
3D FEM
Interface
4 © 2013 ANSYS, Inc. November 12, 2015 ANSYS Confidential © 2013 ANSYS, Inc. November 12, 2015 ANSYS Confidential
Stackup Definition
• Standard HFSS design entry uses 3D Object
• HFSS in Designer combine 2D drawing with stackup definition
+ =
5 © 2013 ANSYS, Inc. November 12, 2015 ANSYS Confidential © 2013 ANSYS, Inc. November 12, 2015 ANSYS Confidential
HFSS Meshing Techniques
• Classic • Approach: Starts with a 3D surface triangular mesh on all objects and generate a 3D volume
mesh throughout simulation domain
• Availability: HFSS (traditional 3D interface) and HFSS 3D Layout
• Pro: Works for any arbitrary 3D geometry
• Con: For complex, many layered geometries can require a long time to generate
• PhiNew
• Approach: From a layout, generate layer by layer 2D triangular mesh. Sweep mesh in stackup (+z) direction to generate tetrahedral mesh elements
• Advantage: Skips heavyweight ACIS and 3D surface mesh generation
• Availability: HFSS 3D Layout only
• Pro: Extremely fast relative to classic 3D mesh approach
• Con: Only works for stack-up or ‘swept in Z’ geometries. IC components and packages, PCBs. etc.
6 © 2013 ANSYS, Inc. November 12, 2015 ANSYS Confidential © 2013 ANSYS, Inc. November 12, 2015 ANSYS Confidential
Enhanced Meshing = Faster Run Times
HFSS 3D CAD HFSS 3D Layout
Initial Mesher Classic Phi
Initial Mesh Size (tets) 763, 953 712, 536
Initial Mesh Time 1hr 20min 4min
Number of Adaptive Passes 6 7
Number of Tets - Final 1, 617, 954 1, 620, 969
Adaptive Passes Run Time 4hrs 1min 1hr 5min (3.7X faster)
RAM 47.6 GB 49.6 GB
Release v2014.0 November 12, 2015 L1-0: 7 © 2014 ANSYS, Inc.
Phi versus Classic: RFIC application
HFSS 3D Layout HFSS 3D Layout
Initial Mesher Classic Phi
Initial Mesh Size (tets) 274, 461 106, 167
Initial Mesh Time 1hr 06min 50sec
Number of Adaptive Passes 6 9
Number of Tets - Final 607, 630 552, 970
Adaptive Passes Run Time 1hrs 55min 50min (~2X faster)
RAM 8.85 GB 9.65 GB
P1 p2
RFIC Finger CAP courtesy of Wilocity
Capcitance value@10GHz Pass 4 8mn 0.5560pF Pass 6 19mn 0.2446pF Pass 7 27mn 0.2150pF Pass 8 38mn 0.2069pF Pass 9 53mn 0.2034pF
Release v2014.0 November 12, 2015 L1-0: 8 © 2014 ANSYS, Inc.
Test Case 1: Spiral Inductor on 1 Metal Layer
Page 8 2014-02-19 Copyright © Infineon Technologies AG 2013. All rights reserved.
Original Virtuoso Cell view
ANSYS Cell view (automatic cluster of VIAs pattern)
Release v2014.0 November 12, 2015 L1-0: 9 © 2014 ANSYS, Inc.
3D View of Inductor in ANSYS HFSS 3d Layout
Page 9 2014-02-19 Copyright © Infineon Technologies AG 2013. All rights reserved.
Test Case 1 Simulation Performance Comparison
Tool Simulation Time
(hh:mm:ss) Resources
ANSYS HFSS
(FEM)
L convergence 00:06:00 8 CPUs; 610 MBytes
L + Q
convergence 01:08:00 8 CPUs; 5.04 GBytes
ANSYS Planar EM (MoM) 00:06:00 8 CPUs; 1.15 GBytes
Tool 3 (MoM) 00:23:00 16 CPUs; 213 MBytes
Tool 4 (MoM) 00:11:00 16 CPUs; 973 MBytes
Page 10 2014-02-19 Copyright © Infineon Technologies AG 2013. All rights reserved.
Page 11 2014-02-19 Copyright © Infineon Technologies AG 2013. All rights reserved.
Test Case 2: Spiral Inductor on 3 Metal Layers
Original Virtuoso Cell view
ANSYS Cell view (automatic cluster of VIAs pattern)
Original Layout (directly exported from Virtuoso)
Simplified Layout (reduced layout complexity at VIA layers)
Necessary Layout Modification
Page 12 2014-02-19 Copyright © Infineon Technologies AG 2013. All rights reserved.
The original layout directly exported from Virtuoso has a very complicated 3D structure due the Via pattern huge mesh density that leads to an inefficiency on MoM
A layout simplification was done in order to solve the inductor with MoM within a reasonable time
Port1 Port2
Port1 Port2
Port1 Port2
Port1 Port2
Test Case 2 Simulation Performance Comparison
Tool Simulation Time
(hh:mm:ss) Resources
ANSYS
HFSS
(FEM)
Original layout 00:25:00 8 CPUs ; 1.5 GBytes
Modified layout 00:24:00 8 CPUs ; 1.56 GBytes
ANSYS
Planar EM
(MoM)
Original layout N.A.
(>>1 day : aborted) > 70 GBytes
Modified layout 03:10:00 8 CPUs ; 6.3 GBytes
Tool 3 (MoM) Modified layout 07:48:00 12 CPUs ; 14 GBytes
Tool 4 (MoM) Modified layout 04:27:00 16 CPUs ; 14 GBytes
Page 13 2014-02-19 Copyright © Infineon Technologies AG 2013. All rights reserved.
Release v2014.0 November 12, 2015 L1-0: 14 © 2014 ANSYS, Inc.
• Modify Stackup/Layers
– Select the menu item Layout > Layers
– Add, Remove signal or dielectric layers
• Parameterization – Parametric Design Environment
• Fully parameterized geometry and stackups
• New stackup dialog with laminate mode
• Visibility-by-type
• XML read/write
• Surface Roughess – Hurray or Groise Model
• Per Layer based
• Per polygon based
Layer Stackup Editor
Layers/Stackup
Release v2014.0 November 12, 2015 L1-0: 15 © 2014 ANSYS, Inc.
• Create Gap Coax Port – As simple as Draw > Port > Create or
– Select Edges Port > Create Edge Port
• Vertical or Coaxial
Inteligent Automatic Ports Creation
Release v2014.0 November 12, 2015 L1-0: 16 © 2014 ANSYS, Inc.
• Automatic Ports Setup – Right click > Select Edges > “Click on Ports Edges”
– Wave or Lumped ports depending on routing type
Wave or Lumped Ports
Gap (Lumped) Port
Wave Port
Convert
Lumped to Wave Port
video
Release v2014.0 November 12, 2015 L1-0: 17 © 2014 ANSYS, Inc.
Embedded Components • S-parameters or RLC components
– No requirement to mesh a boundary condition or to add ports for connecting terminals of a device
– Includes ability to represent these component models via S-parameters
Release v2014.0 November 12, 2015 L1-0: 18 © 2014 ANSYS, Inc.
HFSS Extent and Air Box setup
© 2014 ANSYS, Inc. November 12, 2015 19
Post-Processing
• Rectangular, smith chart … plots
• Current, far and near field display
• Meshing
2.00 4.50 7.00 9.50 12.00 14.50 17.00 19.50F [GHz]
-37.50
-25.00
-12.50
0.00
Y1
Ansoft LLC spir2_20S11_12_dB ANSOFT
Curve Info
S12_3D_HFSSSetup HFSS_gap : Sw eep 1
S11_3D_HFSSSetup HFSS_gap : Sw eep 1
5.002.001.000.500.200.00
5.00
-5.00
2.00
-2.00
1.00
-1.00
0.50
-0.50
0.20
-0.20
0.000
10
20
30
40
50
6070
8090100110
120
130
140
150
160
170
180
-170
-160
-150
-140
-130
-120-110
-100 -90 -80-70
-60
-50
-40
-30
-20
-10
spir2_20Smith Chart 1 ANSOFTCurve Info
S(Port1,Port1)Setup HFSS_gap : Sw eep 1
© 2014 ANSYS, Inc. November 12, 2015 20
Integration in existing flow
© 2014 ANSYS, Inc. November 12, 2015 21
Integration in Existing Flow
• GDS Import Layout geometry is imported into HFSS 3D Layout with layer stackup defined.
All information for material properties, layer type, elevation and thickness are
automatically set with regards to .xml file information.
• Cadence Virtuoso Integration Set-up and solve HFSS simulations without leaving the Cadence environment
• Microwave Office Link For HFSS 3-D layered geometries, the exporting of the stack-up, material properties,
boundary conditions and port settings are all included when you click “export to
HFSS” from within the MWO software.
© 2014 ANSYS, Inc. November 12, 2015 22
Thank you