HDL Lab Manual VTU

8/9/2019 HDL Lab Manual VTU

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HDL LAB L.K.S

––––––

Department of Electronics & Instrumentation, BIT

Prepared by: Sudha L.K

Department of Electronics &InstrumentationBangalore Institute of echnology

!ard"are DescriptionLanguage

Lab #anual


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HDL Lab Manual L.K.S

Cycle of Experiments for HDL Lab

l Cycle

I. Write a VHDL/VERILOG code to simlate all lo!ic !ates.". Write a VHDL/VERILOG code to synt#esi$e "%& Decoder.'. Write a VHDL/VERILOG code to simlate (%) *ltiplexer.&. Write a VHDL/VERILOG code to simlate )%& Demltiplexer.+. Write a VHDL/VERILOG code to simlate (%' Encoder ,it#/,it#otpriority.-. Write a VHDL/VERILOG code to synt#esi$e & bit Comparator.

ll Cycle

I. Write a VHDL/VERILOG code to simlate and synt#esi$e t#e fnction of lldder sin! t#e follo,in! modelin! styles and demonstrate t#e operation.a0 Data lo,. b0 1e#a2ioral. c0 3trctral.". Write a VHDL/VERILOG code to simlate 3R and demonstrate t#eoperation.'. Write a VHDL/VERILOG code to simlate 45.&. Write a VIIDL/VERILOG code to synt#esi$e 6 7ip87op.+. Write a VHDL/VERILOG code to synt#esi$e D 7ip87op.

Ill Cycle

). Write a VHDL/VERILOG code to synt#esi$e & bit binary to !ray codecon2erter.". Write a VHDL/VERILOG model for &8bit L9 to simlate t#e follo,in!fnctionsi0 : 1 20 ;D 1ii0 81 2i0 or 1iii0 Complement 2ii0 ;;D 1i20 < 1 2iii0 =OR 1.'. Write a VHDL/VERILOG to synt#esi$e 1CD conter ,it#

sync#ronos/async#ronos reset.&. Write a VHDL/VERILOG code to synt#esi$e & bit binary conter ,it#sync#ronos/ async#ronos reset.+. Write a VHDL/VERILOG code to simlate a conter ,#ic# conts t#ese>ence ??????.

IV Cycle @Interfacin! Experiments0

). Write a VHDL code to display t#e Ele2ator operation.". Write a VHDL code to display t#e Hex Aeypad operation.

'. Write a VHDL code to interface DC and !enerate a 6rian!lar/RampWa2e&. Write a VHDL code to control t#e speed of DC motor anddemonstrate t#e operation.



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+. Write a VHDL code to c#an!e t#e Direction of 3tepper motor.-. Write a VHDL code to demonstrate t#e Relay operation.

Department of Electronics & Instrumentation, BIT !


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Department of Electronics & Instrumentation, BIT "


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Department of Electronics & Instrumentation, BIT #


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Department of Electronics & Instrumentation, BIT $


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1. Write HDL code to realize logic gates and demonstrate the operation.

i) VHDL code

librar% IEEE

use IEEE.STD'L()I*'+#.ALL

use IEEE.STD'L()I*'AITH.ALL

use IEEE.STD'L()I*'-SI)ED.ALL

entit% basic'/ates is

0ort 1 a,b 2 in st3'lo/ic

an3'/, or'/, not'a, nan3'/, nor'/, 4or'/, 4nor'/ 2 out st3'lo/ic5

en3 basic'/ates

arc6itecture lo/ic'/ates of basic'/ates is

be/in Trut6 Table

an3'/ 78 a an3 b

or'/ 78 a or b not'a 78 not a

nor'/ 78 a nor b

nan3'/ 78 a nan3 b

4or'/ 78 a 4or b

4nor'/ 78a 4nor b

en3 lo/ic'/ates

ii) Verilog code

mo3ule b/ates1a, b, an3/, or/, not/, nan3/, nor/, 4or/, 4nor/5 input a,b

output an3/,or/,not/,nan3/,nor/,4or/,4nor/

assi/n an3/ 8 a&b

assi/n or/ 8 a9b

assi/n not/ 8 :a

assi/n nor/ 8 :1a9b5

assi/n nan3/ 8 :1a&b5

assi/n 4or/8 a;b

assi/n 4nor/8:1a;b5en3mo3ule

RESULT: T6e /ates


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$. Descrie the %&nction o% %&ll adder &sing the %ollo'ing modeling st(les

and demonstrate the operation.

a) Data %lo'

) eha*ioral

c) Str&ct&ral

a) Data %lo'

i) VHDL code:

librar% IEEE




entit% fa3 is

0ort 1cin, a, b2 in st3'lo/ic s, c2 out st3'lo/ic5

en3 fa3

arc6itecture Be6a=ioral of fa3 is

be/in

s781a 4or b5 4or cin

c781a an3 b5or 1b an3 cin5 or 1cin an3 a5

en3 Be6a=ioral

ii) Verilog +ode

mo3ule 3ataflo


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) eha*ioral

i) VHDL code:

librar% IEEE




entit% fab is

0ort 1 3 2 in st3'lo/ic'=ector1! 3o5

e 2 out st3'lo/ic'=ector1 3o55

en3 fab

arc6itecture Be6a=ioral of fab is

be/in

process135

be/in

if 138@>>>@5 t6en e78@>>@

elsif 138@>>@5 t6en e78@>@ elsif 138@>>@5 t6en e78@>@

elsif 138@>@5 t6en e78@>@

elsif 138@>>@5 t6en e78@>@

elsif 138@>@5 t6en e78@>@

elsif 138@>@5 t6en e78@>@

else e78@@

en3 if

en3 process

en3 Be6a=ioral

ii) Verilog code:

mo3ule a33'be='=13, e5

input !2> 3

output 2> e

re/2>e

al

"3!2e8!b>

"3"2e8!b>

"3#2e8!b>

"3$2e8!b>

"3+2e8!b>

"3?2e8!b

3efault2

en3case

en3

en3mo3uleDepartment of Electronics & Instrumentation, BIT

Trut6 Table

a b c Sum *arr% e8sc

> > > > > >>> > > >

> > > >

> > >

> > > >

> > >

> > >


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+) Str&ct&ral

i) VHDL code

librar% IEEE




entit% FullA33er is

0ort 1 Ain 2 in st3'lo/ic Bin 2 in st3'lo/ic *in 2 in st3'lo/ic *out 2 out st3'lo/ic

Sum 2 out st3'lo/ic5

en3 FullA33er

arc6itecture FullA33er of FullA33er is

GG Half A33er *omponent bein/ Instantiate3

*omponent Halfa33er

0ort 1 Ain 2 in st3'lo/ic

Bin 2 in st3'lo/ic

Sum 2 out st3'lo/ic*arr% 2 out st3'lo/ic5

en3 *omponent

Si/nal temp,temp!, temp"2 st3'lo/ic GG Si/nal Declaration

Be/in

L2 Halfa33er port map 1Ain, Bin, temp, temp!5

L!2 Halfa33er port map 1temp, *in, Sum, temp"5

*out 78 temp! or temp"

en3 FullA33er

ii) Verilog +ode

mo3ule fulla331a, b, c, sum, carr%5

input a

input b

input c

output sum

output carr%6a 61b, c, s>, c>5

6a 6!1a, s>, sum, c5

or1carr%, c>, c5

en3mo3ule


J1mo3ule for 6alfGa33er5mo3ule 6a1a, b, s, c5

input a, b

output s, c

4or1s, a, b5

an31c, a, b5

en3mo3ule J

RESULT: T6e full a33er usin/ 3ata flo


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,. Write HDL code %or the %ollo'ing cominational design and demonstrate

the operation.

a) $ to - decoder

) - it inar( to gra( code con*erter.

a) $ to - decoder

i) VHDL code:

librar% IEEE




entit% !3ec is

0ort 1 4 2 in st3'lo/ic'=ector1 3o5

e 2 in st3'lo/ic % 2 out st3'lo/ic'=ector1" 3o55

en3 !3ec

arc6itecture Be6a=ioral of !3ec is

be/in

process 14,e5

be/in

if 1e8>5 t6en %78>>>>else

case 4 is

>@8%78@>>>@

@8%78@>>>@

@8%78@>>>@

>>@


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ii) Verilog code:

mo3ule 3eco3e'!'#1enable, 3in, 3out5

input enable

input 2> 3in

output "2> 3out

re/ "2> 3out

al>>>

else

case 13in5

!b>>2 3out8#b>>>

!b>2 3out8#b>>> !b>2 3out8#b>>>

!b2 3out8#b>>>

3efault2

en3case

en3

en3mo3ule

W!VE/R0

RESULT: T6e HDL pro/ram for ! to # 3eco3er is simulate3 an3 Trut6 Table is

=erifie3 an3 t6e


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) - it inar( to gra( code con*erter.

i) VHDL code:

librar% IEEE




entit% B!) is

0ort 1 b 2 in st3'lo/ic'=ector1" 3o5

/ 2 out st3'lo/ic'=ector1" 3o55

en3 B!)

arc6itecture Be6a=ioral of B!) is be/in

/1"578b1"5

/1!578b1"5 4or b1!5

/1578b1!5 4or b15

/1>578b15 4or b1>5

en3 Be6a=ioral

ii) Verilog code:

mo3ule bin'/ra%1binar%, /ra%5

input "2> binar%

output "2> /ra%

assi/n /ra%" 8 binar%"

assi/n /ra%! 8 binar%" ; binar%!

assi/n /ra% 8 binar%! ; binar%

assi/n /ra%> 8 binar% ; binar%>

en3mo3ule

W!VE/R0

RESULT: T6e HDL pro/ram for # bit binar% to /ra% co3e con=erter


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-. Write HDL code %or the %ollo'ing cominational design and demonstrate

the operation.

a) :1 0&ltiple#er. ) 1:- Dem&ltiple#er.

a) :1 0&ltiple#er.

i) VHDL code:

librar% IEEE




entit% multi' is0ort 1 i 2 in STD'L()I*'NE*T( 1? 3o5

sel 2 in STD'L()I*'NE*T( 1! 3o5

% 2 out STD'L()I*

en 2 in STD'L()I*5

en3 multi'

arc6itecture Be6a=ioral of multi' is

be/in process1sel,i,en5

be/in

if1en8>5t6en %78>

else

case 1sel5 is

>>@8%78i1>5

>@8%78i15

>@8%78i1!5

@8%78i1"5

>@8%78i1#5

@8%78i1$5

@8%78i1+5


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ii) Verilog code:

mo3ule mu4'1i, sel, en, %5

input ?2> i

input !2> sel

input en

output %

re/ %

al5 %8>

else

case1sel5

"3>2 %8i> "32 %8i

"3!2 %8i!

"3"2 %8i"

"3#2 %8i#

"3$2 %8i$

"3+2 %8i+

"3?2 %8i?

3efault2

en3case en3

en3mo3ule

W!VE/R0

RESULT: T6e /ates


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) 1:- Dem&ltiple#ers.

i) VHDL code:

librar% IEEE




entit% mu4'# is

0ort 1sel2 in st3'lo/ic'=ector 1 3o5

32 out st3'lo/ic'=ector1" 3o5

%2 in st3'lo/ic5

en3 mu4'#

arc6itecture Be6a=ioral of mu4'# is

be/in

process 1sel,%5

be/in

378 O>>>>

case sel is

>@8 31>578%

@8 31578%@8 31!578%


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ii) Verilog code:

mo3ule 3emu4''#13in, sel, op5

input2> sel

input 3in

output "2> op

re/ "2> op

al

case1sel5

!3>2 op> 83in

!32 op 8 3in

!3!2 op! 8 3in !3"2 op" 8 3in

en3case

en3

en3mo3ule

W!VE/R0

RESULT: T6e /ates


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2. Write VHDL code to realize to , encoder 'ith and 'itho&t priorit( and

demonstrate the operation.

a) W3TH 4R3/R3T5

i) VHDL code:

librar% IEEE




entit% @ 58else

@>>@ >@ @


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ii) Verilog code:

mo3ule pri1in, out5

input ?2> in

output !2> out

re/!2> out

al>2 out 8 "3!

b4444>>>2 out 8 "3"

b444>>>>2 out 8 "3#b44>>>>>2 out 8 "3$

b4>>>>>>2 out 8 "3+

b>>>>>>>2 out 8 "3?

3efault2 out 8 "3>

en3case

en3

en3mo3ule

W!VE/R0

RESULT: T6e NHDL pro/ram for to " enco3er


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) W3TH/UT 4R3/R3T5:

i) VHDL code:

librar% IEEE




entit% enc'" is

0ort 1 i 2 in st3'lo/ic'=ector1? 3o5

% 2 out st3'lo/ic'=ector1! 3o55

en3 enc'"

arc6itecture Be6a=ioral of enc'" is

be/in

process 1i5

be/in

case i is

>>>>>>@ 8 %78@@

>>>>>> 8 %78@>@

>>>>>>@ 8 %78@>@>>>>>>@ 8 %78@>>@

>>>>>>@ 8 %78@>@

>>>>>>@ 8 %78@>>@

>>>>>>@ 8 %78@>>@

>>>>>>@ 8 %78@>>>@

>>@

en3 case

en3 process

en3 Be6a=ioral



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ii) Verilog code:

mo3ule enc'no'pr1enable, 3in, 3out5

input enable

input ?2> 3in

output !2> 3out

re/ !2> 3out

al>>

else

case 13in5

32 3out8"3> 3!2 3out8"3

3#2 3out8"3!

32 3out8"3"

3+2 3out8"3#

3"!2 3out8"3$

3+#2 3out8"3+

3!2 3out8"3?

3efault2 3out8"3>

en3case en3

en3mo3ule

W!VE/R0

RESULT: T6e NHDL pro/ram for to " enco3er


22/63


6. Design and implement HDL code %or an( Se7&ence co&nter and

demonstrate its operation:

i) VHDL code:

librar% IEEE




entit% an%seP is

0ort 1 clQ,rst 2 in st3'lo/ic

P 2 out st3'lo/ic'=ector1" 3o55

en3 an%seP

arc6itecture Be6a=ioral of an%seP is

si/nal a2 st3'lo/ic'=ector 1" 3o5

si/nal clQ3i= 2 st3'lo/ic'=ector 1!> 3o5si/nal clQ 2 st3'lo/ic

be/in

process1clQ5

be/in

if1clQe=ent an3 clQ85 t6en

clQ3i= 78 clQ3i=R

en3 if

clQ78 clQ3i=1$5

en3 process

process1clQ5

be/in

if 1rst 85 t6en

a78@>>>@

elsif 1clQe=ent an3 clQ85t6en

case a is

>>@ 8 a 78@>>@

>@ 8 a 78@>>@>@ 8 a 78@>>@

>@ 8 a 78@>>>@

>>>@

en3 case

en3 if

en3 process

P78a

en3 Be6a=ioral



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ii) Verilog code:

mo3ule an%'sePuence'counter 1clQ,rst,Pout5

input clQ,rst

output "2> Pout

re/"2> Pout

re/ !> 2> temp

re/ clQ

al>

else

case 1Pout5

#b>>>2Pout8#b>>

#b>>2Pout8#b>>>

#b>>>2Pout8#b>>

#b>>2Pout8#b>

#b>2Pout8#b>>>

en3case

en3

en3mo3ule

W!VE/R0

RESULT: T6e NHDL co3e for SePuence counter


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8. Design and implement HDL code %or a +D co&nter &sing s(nchrono&s

and as(nchrono&s reset and demonstrate its operation:

a) S(nchrono&s +D co&nter :

i) VHDL code:

librar% IEEE




entit% s%ncbc3cntr is


P 2 out st3'lo/ic'=ector1" 3o55

en3 s%ncbc3cntr

arc6itecture Be6a=ioral of s%ncbc3cntr is

si/nal P 2 st3'lo/ic'=ector 1" 3o5

si/nal clQ3i= 2 st3'lo/ic'=ector 1!> 3o5

si/nal clQ 2 st3'lo/ic

be/in

process1clQ5

be/in

if1clQe=ent an3 clQ85 t6enclQ3i= 78 clQ3i=R

en3 if

clQ78 clQ3i=1$5

en3 process

process1clQ5

be/in

if1clQe=ent an3 clQ85t6en

if1rst85t6en P 78 @>>>>@

else P 78 PR

if1P8>>5t6en

P8>>>>

en3 if

en3 if

en3 if

en3 process

P 78 P

en3 Be6a=ioral

Department of Electronics & Instrumentation, BIT !"


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ii) Verilog code:

mo3ule s%nreset'bc3'upcounter1clQ,rst,Pout5

input clQ,rst

output "2> Pout

re/ "2> Pout

re/ !> 2> temp

re/ clQ

al>>

else

be/in

Pout8PoutRif1Pout88#b>>5

Pout8#b>>>>

en3

en3mo3ule

W!VE/R0

Department of Electronics & Instrumentation, BIT !#


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) !s(nchrono&s +D co&nter:

i) VHDL code:

librar% IEEE




entit% bc3as%n is


count 2 inout st3'lo/ic'=ector1" 3o55

en3 bc3as%n

arc6itecture Be6a=ioral of bc3as%n is

si/nal clQ3i= 2 st3'lo/ic'=ector 1!> 3o5si/nal clQ 2 st3'lo/ic

be/in

process1clQ5

be/in


clQ3i= 78 clQ3i=R

en3 if

clQ78 clQ3i= 1$5

en3 process process 1clQ,rst5

be/in

if 1rst85 t6en

count78>>>>

elsif 1clQe=ent an3 clQ85 t6en

count 78 count R

if count 8@>>@ t6en

count 78>>>>

en3 ifen3 if

en3 process

en3 Be6a=ioral

Department of Electronics & Instrumentation, BIT !$


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ii) Verilog code:

mo3ule as%nreset'bc3'upcounter1clQ,rst,Pout5

input clQ,rst

output "2> Pout

re/ "2> Pout

re/ !> 2>temp

re/ clQ

al>>

else

be/in

Pout 8PoutRif1Pout88#b>>5

Pout8#b>>>>

en3

en3mo3ule

W!VE/R0

RESULT: T6e HDL co3e for B*D *ounter usin/ bot6 s%nc6ronous an3

as%nc6ronous reset


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. Design and implement HDL code %or a inar( co&nter &sing s(nchrono&s

and as(nchrono&s reset and demonstrate its operation:

a) S(nchrono&s inar( co&nter

i) VHDL code:

librar% IEEE




entit% s%nbincntr is


P 2 out st3'lo/ic'=ector1" 3o55en3 s%nbincntr

arc6itecture Be6a=ioral of s%nbincntr is

si/nal P 2 st3'lo/ic'=ector 1" 3o5

si/nal clQ3i= 2 st3'lo/ic'=ector 1!> 3o5


be/in

process1clQ5

be/inif1clQe=ent an3 clQ85 t6en

clQ3i= 78 clQ3i=R

en3 if

clQ78 clQ3i=1$5

en3 process

process1clQ5

be/in

if1clQe=ent an3 clQ85t6en if1rst85t6en

P 78 @>>>>@

else

P 78 PR

en3 if

en3 if

en3 process

P 78 P

en3 Be6a=ioral

Department of Electronics & Instrumentation, BIT !?


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Verilog code:

mo3ule s%nreset'bin'upcounter1clQ,rst,Pout5

input clQ,rst

output "2> Pout

re/ "2> Pout

re/ !>2> temp

re/ clQ

al>>

elsePout8PoutR

en3

en3mo3ule



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) !s(nchrono&s inar( co&nter

i) VHDL code:

librar% IEEE




entit% as%'bin is


count 2 out st3'lo/ic'=ector1" 3o55

en3 as%'bin

arc6itecture Be6a=ioral of as%'bin is

si/nal temp2st3'lo/ic'=ector1" 3o5si/nal clQ3i= 2 st3'lo/ic'=ector 1!> 3o5


be/in

process1clQ5

be/in


clQ3i= 78 clQ3i=R

en3 if

clQ78 clQ3i=1$5en3 process

process1clQ,rst5

be/in

if 1rst85 t6en

temp78>>>>


temp 78 tempR

en3 if

en3 processcount78temp

en3 Be6a=ioral



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ii) Verilog code:

mo3ule as%nreset'bin'upcounter1clQ,rst,Pout5

input clQ,rst

output "2> Pout

re/ "2> Pout

re/ !> 2> temp

re/ clQ

al>>

else

be/in

Pout 8PoutR

en3

en3mo3ule

RESULT: T6e HDL pro/ram for # bit comparator


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9. Write HDL code %or - it comparator and demonstrate the operation.

i) VHDL code:

librar% IEEE




entit% comparator is

0ort 1 a,b 2 in st3'lo/ic'=ector1" 3o5

e,/,l 2 out st3'lo/ic5

en3 comparator

arc6itecture Be6a=ioral of comparator is

be/in

process1a,b5

be/in

if a8b t6en e78/78>l78>

elsif a7b t6en l78e78>/78>

else /78l78>e78>en3 if

en3 process

en3 Be6a=ioral

Department of Electronics & Instrumentation, BIT "


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ii) Verilog code:

mo3ule comp1a, b, alb, a/b, aeb5

input "2> a

input "2> b

output alb,a/b,aeb

re/ alb,a/b,aeb

al if1ab5 a/b8

else a/b 8 >

if1a88b5 aeb8

else aeb 8>

en3

en3mo3ule

W!VE/R0

RESULT: T6e HDL pro/ram for # bit comparator


34/63


1. Write a HDL %or model %or - ; it !LU to implement the

%ollo'ing %&nctions:

@ L(* 8 @S20I"@

ET @opco3e7@ L(* 8 @S20I#@

ET @opco3e7!@ L(* 8 @S20I$@

ET @out7>@ L(* 8 @S20I?@ ET @out7@ L(* 8 @S20I@

ET @out7!@ L(* 8 @S20I@

ET @out7"@ L(* 8 @S20I!>@

ET @out7#@ L(* 8 @S20I!@

ET @out7$@ L(* 8 @S20I!"@

ET @out7+@ L(* 8 @S20I!#@

ET @out7?@ L(* 8 @S20I!$@


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ii) Verilog code:

mo3ule alu=!1a,b, opco3e, m5

input "2> a,b

input !2> opco3e

output ?2> m

re/ ?2> m

al>2m8aGb

"b>>2m8a9b"b>2m8a&b

"b>>2m8:a

"b>2m8aJb

"b>2m8:1a&b5

"b2m8a;b

en3case

en3

en3mo3ule

W!VE/R0

RESULT: T6e HDL pro/ram for # bit AL- @ L(* 8 @S20I"@

ET @opco3e7@ L(* 8 @S20I#@ ET @opco3e7!@ L(* 8 @S20I$@

ET @out7>@ L(* 8 @S20I?@

ET @out7@ L(* 8 @S20I@

ET @out7!@ L(* 8 @S20I@

ET @out7"@ L(* 8 @S20I!>@

ET @out7#@ L(* 8 @S20I!@

ET @out7$@ L(* 8 @S20I!"@

ET @out7+@ L(* 8 @S20I!#@

ET @out7?@ L(* 8 @S20I!$@


36/63


11. De*elop the HDL code %or the %ollo'ing %lip;%lops and demonstrate the

operation.

a) SR;

i) VHDL code:

librar% IEEE




entit% s'r'flip'flop is

0ort 1s, r, clQ2 in st3'lo/ic

P2 inout st3'lo/ic5en3 s'r'flip'flop

arc6itecture Be6a=ioral of s'r'flip'flop is

be/in

process 1clQ5

be/in

if 1clQe=ent an3 clQ 8 5t6en

if1s8> an3 r8>5 t6en

P 78 Pelsif 1s 8 > an3 r 8 5 t6en

P 78 >

elsif 1s 8 an3 r 8 >5 t6en

P 78

elsif 1s8 an3 r 8 5 t6en

P 78 >

en3 if

en3 if

en3 processen3 Be6a=ioral

Department of Electronics & Instrumentation, BIT "$


37/63


ii) Verilog code:

mo3ule srff1s, r, clQ, P5

input s,r,clQ

output P

re/ P

al & r88b>5 P 8 P

else if 1s88b> & r88b5 P 8 >

else if 1s88b & r88b>5 P 8

else if 1s88b & r88b5 P 8 >

en3

en3mo3ule

W!VE/R0

Department of Electronics & Instrumentation, BIT "+


38/63


) T;

i) VHDL code:

librar% IEEE




entit% t'ff is

0ort 1 t,clQ 2 in st3'lo/ic

P 2 inout st3'lo/ic28>

Pb2 out st3'lo/ic5

en3 t'ff

arc6itecture Be6a=ioral of t'ff is si/nal clQ3i= 2 st3'lo/ic'=ector 1!> 3o5


be/in

process1clQ5

be/in


clQ3i= 78 clQ3i=R

en3 if

clQ78 clQ3i= 1$5en3 process

process 1clQ,t5

be/in

if 1clQe=ent an3 clQ 8 5t6en

if 1t8>5 t6en

P78 >

elsif 1 t 8 5 t6en

P78 not P

en3 if

en3 if

en3 process

Pb78not P

en3 Be6a=ioral

Department of Electronics & Instrumentation, BIT "?


39/63


ii) Verilog code:

mo3ule tff1clQ, t,rst, P,Pb5

input clQ,t,rst

output P,Pb

re/ P,Pb

re/ !>2> temp

re/ clQ

al


40/63


c) D;

i) VHDL code:

librar% IEEE




entit% 3'ff is

0ort 1 3,clQ 2 in st3'lo/ic

P,Pb 2 inout st3'lo/ic5

en3 3'ff

arc6itecture Be6a=ioral of 3'ff is

be/in

process 1clQ5

be/in if 1clQe=ent an3 clQ 8 5 t6en

P78 3

Pb78not 3

en3 if

en3 process

en3 Be6a=ioral

ii) Verilog code:

mo3ule 3ff1clQ, 3, P, Pb5 input clQ,3

output P,Pb

re/ P,Pb

al


41/63


d) ?@;

i) VHDL code:

librar% IEEE




entit% Qff is

0ort 1 clQ,rst,,Q 2 in st3'lo/ic

P 2 inout st3'lo/ic28>

Pb 2 out st3'lo/ic5

en3 Qff

arc6itecture Be6a=ioral of Qff is si/nal clQ3i= 2 st3'lo/ic'=ector 1!> 3o5


be/in

process1clQ5

be/in


clQ3i= 78 clQ3i=R

en3 if

clQ78 clQ3i=1$5en3 process

process1clQ,rst5

be/in

if1rst85t6en P78>

elsif1clQe=ent an3 clQ85t6en

if18> an3 Q8>5t6en P78P

elsif18> an3 Q85t6en P78>

elsif18 an3 Q8>5t6en P78elsif18 an3 Q85t6en P78not P

en3 if

en3 if

en3 process

Pb78 not P

en3 Be6a=ioral

Department of Electronics & Instrumentation, BIT #>


42/63


ii) Verilog code:

mo3ule Qff1Q,reset,clQ, P,Pb5

input2> Q

input reset

input clQ

output P,Pb

re/ P,Pb

re/!>2> temp

re/ clQ

al

en3 al

case1Q5

!b>>2 P8P

!b>2 P8>

!b>2 P8

!b2 P8:Pen3case

Pb8:P

en3

en3mo3ule

W!VE/R0

RESULT: T6e HDL pro/ram for all flip flops


43/63


1. 4R/AR!0 /R S4EED +/BTR/L / ! D+;0/T/R

GG ALS IF*"? D* motor

GG connect U#Gpin !+ to )D

GG connect U#Gpin !$ to R$N

GG connect U#Gpin $ to *0LD pin 1p3cm5

GG connect tQbase clQ $>>Q6 to *0LD pin !>

GG *0LD 0in ,!," as SV >,,!

GG s sGG > > > 8 $>>rpm

GG > > 8 >>rpm

GG> >

GGGG 8 !$>>rpm

librar% IEEE




entit% TKBD*M is

0ort 1 ps< 2 in st3'lo/ic'=ector1! 3o5 p3cm 2 out st3'lo/ic

p>>Q 2 in st3'lo/ic 5

en3 TKBD*M

arc6itecture be6a=ioral of TKBD*M is

si/nal sclQ3i= 2 st3'lo/ic'=ector1 3o5

be/in

;; co&nt &pto , process1p>>Q5

be/inGGR

if1 risin/'e3/e1p>>Q55 t6en

sclQ3i= 78 sclQ3i=R

en3 if

if1sclQ3i= 8 @>>>>>@5 t6en

sclQ3i= 78 @>>>>>>>>>>>>@

en3 if

en3 process

process1ps


44/63


=ariable =3cm 2 bit

be/in

if1sclQ3i= 8 @>>>>>>>>>>>>@5 t6en

=3cm 28

en3 if

;; 1%-C ,$C --cC 28C 6a-C 8dC %cC 9c- if1ps< 8 @>>>@ an3 sclQ3i= 8 @>>>>>>@5 t6en =3cm 28 >elsif1ps< 8 @>>@ an3 sclQ3i= 8 @>>>>>>>>>@5 t6en =3cm 28 >

elsif1ps< 8 @>>@ an3 sclQ3i= 8 @>>>>>>>>@5 t6en =3cm 28 >

elsif1ps< 8 @>@ an3 sclQ3i= 8 @>>>>>>@5 t6en =3cm 28 >

elsif1ps< 8 @>>@ an3 sclQ3i= 8 @>>>>>>>@5 t6en =3cm 28 >

elsif1ps< 8 @>@ an3 sclQ3i= 8 @>>>>>>@5 t6en =3cm 28 >

elsif1ps< 8 @>@ an3 sclQ3i= 8 @>>>>>@5 t6en =3cm 28 >

elsif1ps< 8 @@ an3 sclQ3i= 8 @>>>>>>>@5 t6en =3cm 28 >

en3 if

if1=3cm 8 5 t6en p3cm 78

else p3cm 78 >

en3 if

en3 process

en3 be6a=ioral

U+ 3LE /R D+;0/T/R

ET @p>>Q@ L(* 8 @S20I!>@ ET @ps@ L(* 8 @S20I@

ET @ps >

> > it means t6at t6e connection 3o liQe

3ifference combination5 t6is increase

> > t6e motor spee3. 1W> means connecte3 to )roun3 of *0LD

W means connecte3 to R$N of *0LD5

Department of Electronics & Instrumentation, BIT #"


45/63


$. 4R/AR!0 /R !B ELEV!T/R

librar% IEEE




entit% TKBELE is

0ort 1 pQe%ret 2 in st3'lo/ic'=ector1" 3o5

pQe%scn 2 out st3'lo/ic'=ector1" 3o5

p3spse/ 2 out st3'lo/ic'=ector 1+ 3o5

p3spmu4 2 out st3'lo/ic'=ector 1" 3o5

pclQ>>K 2 in st3'lo/ic 5

en3 TKBELE

arc6itecture be6a=ioral of TKBELE is

si/nal scurflr,sQe%flr 2 inte/er ran/e > to $

si/nal sQe%6it 2 st3'lo/ic

si/nal sQe%scn 2 st3'lo/ic'=ector1" 3o5

si/nal lQe%scn 2 st3'lo/ic'=ector1" 3o5

si/nal lQe%ret 2 st3'lo/ic'=ector1" 3o5

si/nal sclQ3i= 2 st3'lo/ic'=ector1$ 3o5

si/nal sflrclQ,sQe%clQ 2 st3'lo/ic

be/in

;; process e(press

process1pQe%ret5

be/in

case pQe%ret is

@ 8 sQe%6it 78

@ 8 sQe%6it 78

@ 8 sQe%6it 78 @ 8 sQe%6it 78

en3 case

en3 process

process1sQe%6it5

be/in

if1 risin/'e3/e1sQe%6it55 t6en

lQe%scn 78 sQe%scn

lQe%ret 78 pQe%ret

en3 if

en3 processDepartment of Electronics & Instrumentation, BIT ##


46/63


;; process e(*al

process1sQe%6it5

be/in


if1lQe%scn 8 @>@ an3 lQe%ret 8 @>@5

t6en sQe%flr 78 >

elsif1lQe%scn 8 @>@ an3 lQe%ret 8 @>@5

t6en sQe%flr 78


t6en sQe%flr 78 !


t6en sQe%flr 78 "


t6en sQe%flr 78 #

elsif1lQe%scn 8 @>@ an3 lQe%ret 8 @>@5t6en sQe%flr 78 $


t6en sQe%flr 78 +


t6en sQe%flr 78 ?


t6en sQe%flr 78


t6en sQe%flr 78 elsif1lQe%scn 8 @>@ an3 lQe%ret 8 @>@5

t6en sQe%flr 78 >


t6en sQe%flr 78


t6en sQe%flr 78 !


t6en sQe%flr 78 "

elsif1lQe%scn 8 @>@ an3 lQe%ret 8 @>@5t6en sQe%flr 78 #


t6en sQe%flr 78 $

en3 if

en3 if

en3 process

Department of Electronics & Instrumentation, BIT #$


47/63


;; process cl di*ider

process1pclQ>>Q5

be/in

if1 risin/'e3/e1pclQ>>Q55 t6en

sclQ3i= 78 sclQ3i=R

en3 if

sQe%clQ 78 sclQ3i=1+5

sflrclQ 78 sclQ3i=1$5

en3 process

;; process %or e( scan clscan

process1sQe%clQ5

be/in

if1risin/'e3/e1sQe%clQ55 t6en

if sQe%scn 8 @>@ t6en sQe%scn 78 @>@

elsif sQe%scn 8 @>@ t6en sQe%scn 78 @>@elsif sQe%scn 8 @>@ t6en sQe%scn 78 @>@

elsif sQe%scn 8 @>@ t6en sQe%scn 78 @>@

else sQe%scn 78 @>@

en3 if

en3 if

pQe%scn 78 sQe%scn

en3 process

;; process %loor motion

process1sflrclQ5 be/in

if1risin/'e3/e1sflrclQ55 t6en

if1not 1sQe%flr 8 scurflr5 5 t6en

if1sQe%flr scurflr5 t6en scurflr 78 scurflrR

else scurflr 78 scurflrG

en3 if

en3 if

en3 if

en3 process;; process displa( 8seg

process1scurflr5

t%pe tse/? is arra%1> to $5 of st3'lo/ic'=ector 1+ 3o5

constant se/=al 2 tse/? 28@en3 process

en3 be6a=ioral

Department of Electronics & Instrumentation, BIT #+


48/63


U+ 3LE /R ELEV!T/R

ET @pclQ>>K@ L(* 8 @p++@

ET @pQe%ret7>@ L(* 8 @0@

ET @pQe%ret7@ L(* 8 @0!@

ET @pQe%ret7!@ L(* 8 @0"@

ET @pQe%ret7"@ L(* 8 @0#@

ET @pQe%scn7>@ L(* 8 @0$@

ET @pQe%scn7@ L(* 8 @0+@

ET @pQe%scn7!@ L(* 8 @0?@

ET @pQe%scn7"@ L(* 8 @0@

ET @p3spmu47>@ L(* 8 @0#@

ET @p3spmu47@ L(* 8 @0$@

ET @p3spmu47!@ L(* 8 @0?@ ET @p3spmu47"@ L(* 8 @0@

ET @p3spse/7>@ L(* 8 @0"@

ET @p3spse/7@ L(* 8 @0"!@

ET @p3spse/7!@ L(* 8 @0""@

ET @p3spse/7"@ L(* 8 @0"#@

ET @p3spse/7#@ L(* 8 @0"$@

ET @p3spse/7$@ L(* 8 @0"+@

ET @p3spse/7+@ L(* 8 @0"?@

43B +/BBE+T3/B /B +4LD /!RD

(f *0LD

1st - pins are col&mns

Last - pins are ro's

66th pin is connected to cloc.

Department of Electronics & Instrumentation, BIT #?

Hea3erG"Hea3erG!Hea3erG

SEA0EBT+H!BBEL

0UG

+B@E5


49/63


,. 4R/AR!0 /R !B HEG@E54!D

librar% IEEE




entit% TKBHKX is

0ort 1 pQe%ret 2 in st3'lo/ic'=ector1" 3o5

pQe%scn 2 out st3'lo/ic'=ector1" 3o5

p3spse/ 2 out st3'lo/ic'=ector 1+ 3o5

p3spmu4 2 out st3'lo/ic'=ector 1" 3o5


en3 TKBHKX

arc6itecture be6a=ioral of TKBHKX is

si/nal sQe%=al 2 inte/er ran/e > to $

si/nal sQe%6it 2 st3'lo/ic

si/nal sQe%scn 2 st3'lo/ic'=ector1" 3o5

si/nal lQe%scn 2 st3'lo/ic'=ector1" 3o5

si/nal lQe%ret 2 st3'lo/ic'=ector1" 3o5

si/nal sclQ3i= 2 st3'lo/ic'=ector1? 3o5

si/nal sQe%clQ 2 st3'lo/ic

be/in

;; process e(press

process1pQe%ret5

be/in

case pQe%ret is

@ 8 sQe%6it 78

@ 8 sQe%6it 78

@ 8 sQe%6it 78 @ 8 sQe%6it 78

en3 case

en3 process

process1sQe%6it5

be/in


lQe%scn 78 sQe%scn

lQe%ret 78 pQe%ret

en3 if en3 process

Department of Electronics & Instrumentation, BIT #


50/63


;; process e(*al

process1sQe%6it5

be/in


if1lQe%scn 8 @>@ an3 lQe%ret 8 @>@5

t6en sQe%=al 78 >


t6en sQe%=al 78


t6en sQe%=al 78 !


t6en sQe%=al 78 "


t6en sQe%=al 78 #


t6en sQe%=al 78 $elsif1lQe%scn 8 @>@ an3 lQe%ret 8 @>@5

t6en sQe%=al 78 +


t6en sQe%=al 78 ?


t6en sQe%=al 78


t6en sQe%=al 78

elsif1lQe%scn 8 @>@ an3 lQe%ret 8 @>@5t6en sQe%=al 78 >


t6en sQe%=al 78


t6en sQe%=al 78 !


t6en sQe%=al 78 "


t6en sQe%=al 78 #elsif1lQe%scn 8 @>@ an3 lQe%ret 8 @>@5

t6en sQe%=al 78 $

en3 if

en3 if

en3 process

;; process cl di*ider

process1pclQ>>Q5

be/in


sclQ3i= 78 sclQ3i=R

en3 if

sQe%clQ 78 sclQ3i=1+5Department of Electronics & Instrumentation, BIT #


51/63


en3 process;; process %or e( scan clscan

process1sQe%clQ5

be/in

if1risin/'e3/e1sQe%clQ55 t6en

if sQe%scn 8 @>@ t6en sQe%scn 78 @>@




else sQe%scn 78 @>@

en3 if

en3 if

pQe%scn 78 sQe%scn

en3 process

;; process displa( 8seg

process1sQe%=al5t%pe tse/? is arra%1> to $5 of st3'lo/ic'=ector 1+ 3o5

constant se/=al 2 tse/? 28@

en3 process

en3 be6a=ioral

U+ 3LE /R HEG@E54!D

BET pcl1@ L/+ p66 F

BET pe(retIJ L/+ 41 F

BET pe(retI1J L/+ 4$ F

BET pe(retI$J L/+ 4, F

BET pe(retI,J L/+ 4- F

BET pe(scnIJ L/+ 42 F

BET pe(scnI1J L/+ 46 F

BET pe(scnI$J L/+ 48 F

BET pe(scnI,J L/+ 49 F

BET pdspmIJ L/+ 41- F

BET pdspmI1J L/+ 412 F

BET pdspmI$J L/+ 418 F

BET pdspmI,J L/+ 41 F

BET pdspsegIJ L/+ 4,1 FBET pdspsegI1J L/+ 4,$ F

BET pdspsegI$J L/+ 4,, F

BET pdspsegI,J L/+ 4,- F

Department of Electronics & Instrumentation, BIT $>


52/63


BET pdspsegI-J L/+ 4,2 F

BET pdspsegI2J L/+ 4,6 F

BET pdspsegI6J L/+ 4,8 F


(f *0LD

1st - pins are col&mns

Last - pins are ro's

66th pin is connected to cloc.


Hea3erG"Hea3erG!Hea3erG

SEA0EBT+H!BBEL

0UG

+B@E5


53/63


-. 4R/AR!0 /R ! L+D D3S4L!5

librar% IEEE




use IEEE.-MEI*'STD.ALL

entit% tQblc3 is

0ort 1 plc33at 2 out st3'lo/ic'=ector 1? 3o5

plc3rs,plc3r>Q55 t6en

sclQ3i= 78 sclQ3i=R

en3 if

s3spclQ 78 sclQ3i=1$5

plc3en 78 sclQ3i=1$5

en3 process;; displa(

process1s3spclQ5=ariable =3spseP 2 inte/er ran/e > to $

=ariable =3spnum 2 inte/er ran/e > to $

=ariable i 2 inte/er

t%pe tlc3t%p is arra%1> to $5 of st3'lo/ic'=ector 1? 3o5

constant tlc33at 2 tlc3t%p 28

1@>>>>>@,@>>>>>@,@>>>>>>>@,@>>>>>>>@,

@>>>>>>@,@>>>>>>@,@>>>>@,@>>>>>>>@,

@>>>>>>@,@>>>>>>@,@>>>>@,@>>>>>>>@,

@>>>>>>@,@>>>>>>@,@>>>>@,@>>>>>>>@ 5

Department of Electronics & Instrumentation, BIT $!


54/63


be/in

if1fallin/'e3/e1s3spclQ5 5 t6en

=3spseP 28 =3spsePR

en3 if

if1fallin/'e3/e1s3spclQ5 5 t6en

if1=3spseP "5 t6en

=3spnum 28 =3spnumR

en3 if

en3 if

if1=3spseP 7 #5 t6en

plc33at 78 tlc33at1=3spseP5

=3spnum 28 >

else

plc33at 78 tlc33at1=3spseP5

tc6r 78 m%str1=3spnum5

plc33at 78st3'lo/ic'=ector1to'unsi/ne31c6aracterpos1tc6r5,55

en3 if

plc3r< 78 >

if1=3spseP 7 #5 t6en

plc3rs 78 >

else

plc3rs 78

en3 if

en3 processen3 be6a=ioral

U+ 3LE /R L+D

ET @pclQ>>K@ L(* 8 O0??@

ET @plc3rs@ L(* 8 O0@ ET @plc3r


55/63



of *0LD

??t6 pin is connecte3 to clocQ.

Department of Electronics & Instrumentation, BIT $#

Hea3erG!Hea3erG

Data*ontrol


56/63


2. 4R/AR!0 T/ AEBER!TER R!04

librar% IEEE




entit% r=c'3ac is


op 2 out st3'lo/ic'=ector1? 3o55

en3 r=c'3ac

arc6itecture Be6a=ioral of r=c'3ac is

si/nal P2 st3'lo/ic'=ector1? 3o5

be/in

process1clQ,rst5

be/in

if1rst8>5 t6en P781ot6ers8>5


P78 PR GGGGfor step P78PR

en3 if en3 process

op78P

en3 Be6a=ioral

Y0IL(*K'BE)I ET @clQ@ L(* 8 @S20I@

ET @rst@ L(* 8 @S20I!@

ET @op7>@ L(* 8 @S20I"@

ET @op7@ L(* 8 @S20I#@

ET @op7!@ L(* 8 @S20I$@

ET @op7"@ L(* 8 @S20I+@

ET @op7#@ L(* 8 @S20I?@

ET @op7$@ L(* 8 @S20I@

ET @op7+@ L(* 8 @S20I>@

ET @op7?@ L(* 8 @S20I@

Y0IL(*K'ED

Department of Electronics & Instrumentation, BIT $$


57/63


6. 4R/AR!0 /R ! REL!5

librar% IEEE




entit% real% is

0ort 1 p 2 in st3'lo/ic

m 2 out st3'lo/ic5

en3 real%

arc6itecture Be6a=ioral of real% is

be/in

process1p5

be/in

if 1p85t6en

m78

else

m78>

en3 if

en3 process

en3 Be6a=ioral

U+ 3LE /R REL!5

ET @m@ L(* 8 0!

ET @p@ L(* 8 0

Department of Electronics & Instrumentation, BIT $+


58/63


8. 4R/AR!0 /R D3RE+T3/B +/BTR/L / ! STE44ER 0/T/R

librar% IEEE




entit% TKBST0 is

0ort 1 pQe%col 2 in st3'lo/ic'=ector 1" 3o5

pQe%ro< 2 out st3'lo/ic'=ector 1" 3o5

pstpsi/ 2 out st3'lo/ic'=ector1" 3o5


en3 TKBST0

arc6itecture be6a=ioral of TKBST0 is

si/nal sclQ3i= 2 st3'lo/ic'=ector1!> 3o5

si/nal sstpcnt 2 st3'lo/ic'=ector1 3o5

si/nal sstpclQ,sQe%6it 2 st3'lo/ic

si/nal sQe%sts 2st3'lo/ic'=ector 1" 3o5

be/in

;; cldi*ider process1pclQ>>Q5

be/in


sclQ3i= 78 sclQ3i=R

en3 if

sstpclQ 78 sclQ3i=1$5

en3 process

;; e( process

;; o&t e( ro' chec e( col

pQe%ro< 78 @>>>>@

process1pQe%col5

be/in

if1pQe%col1>5 8 > or

pQe%col15 8 > or

pQe%col1!5 8 > or

pQe%col1"5 8 > 5 t6en sQe%6it 78 >

else sQe%6it 78

en3 if

en3 processDepartment of Electronics & Instrumentation, BIT $?


59/63


;; latch e( press

process1sQe%6it5

be/in

if1 fallin/'e3/e1sQe%6it55 t6en

sQe%sts 78 pQe%col

en3 if

en3 process

;; - step co&nter

process1sstpclQ5

be/in

if1risin/'e3/e1sstpclQ55 t6en

if1sQe%sts1>5 8 >5 t6en

sstpcnt 78 sstpcntR

elsif1sQe%sts15 8 >5 t6ensstpcnt 78 sstpcntG

en3 if

en3 if

en3 process

;; o&tp&ts signal pstpsig DC +C K ! %or stepper motor

;; T@ase %rom &c% %ile 1-C1,C1$C 11

;; als stepper controller -C 6C , K 2

process1sstpcnt5 be/in

if 1sstpcnt 8 @>>@5 t6en pstpsi/ 78 @>>>@

elsif1sstpcnt 8 @>@5 t6en pstpsi/ 78 @>@

elsif1sstpcnt 8 @>@5 t6en pstpsi/ 78 @>@

elsif1sstpcnt 8 @@5 t6en pstpsi/ 78 @>>>@

en3 if

en3 process

en3 be6a=ioral



60/63


U+ 3LE /R STE44ER 0/T/R

ET @pclQ>>K@ L(* 8 @S20I>@

ET @pQe%col7>@ L(* 8 @S20I@

ET @pQe%col7@ L(* 8 @S20I!@

ET @pQe%col7!@ L(* 8 @S20I"@

ET @pQe%col7"@ L(* 8 @S20I#@

ET @pQe%ro@ L(* 8 @S20I$@

ET @pQe%ro


61/63


. 4R/AR!0 T/ AEBER!TE ! TR3!BAUL!R W!VE/R0

librar% IEEE




entit% r=c'3ac is


op 2 out st3'lo/ic'=ector1? 3o55

en3 r=c'3ac

arc6itecture Be6a=ioral of r=c'3ac is

si/nal P2 st3'lo/ic'=ector1? 3o5

si/nal u32st3'lo/ic28>

be/in

process1clQ,rst5

be/in

if1rst8>5 t6en P781ot6ers8>5


if 1u38>5t6en P78PR

elsif 1u385t6en P78PG

en3 if

en3 if en3 process

op78P

process 1clQ5

be/in

if 1clQe=ent an3 clQ85t6en

if1P8@>@5t6en u378

elsif1P8@>>>>>>>@5t6en u378>

en3 if

en3 if

en3 process

Department of Electronics & Instrumentation, BIT +>


62/63


en3 Be6a=ioral

Y0IL(*K'BE)I

ET @clQ@ L(* 8 @S20I@

ET @rst@ L(* 8 @S20I!@

ET @op7>@ L(* 8 @S20I"@

ET @op7@ L(* 8 @S20I#@

ET @op7!@ L(* 8 @S20I$@

ET @op7"@ L(* 8 @S20I+@

ET @op7#@ L(* 8 @S20I?@

ET @op7$@ L(* 8 @S20I@

ET @op7+@ L(* 8 @S20I>@

ET @op7?@ L(* 8 @S20I@

Y0IL(*K'ED

Department of Electronics & Instrumentation, BIT +


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Ramp Triang&lar

*0LD 0in os2G W is connecte3 to clQ

W! is connecte3 to reset W" is connecte3 to pin!of Interfacin/GMo3ule

W# is connecte3 to pin!!of Interfacin/GMo3ule

W$ is connecte3 to pinof Interfacin/GMo3ule

W+ is connecte3 to pin!>of Interfacin/GMo3ule

W? is connecte3 to pin?of Interfacin/GMo3ule

W is connecte3 to pinof Interfacin/GMo3ule

W> is connecte3 to pin$of Interfacin/GMo3ule

W is connecte3 to pin+of Interfacin/GMo3ule 0in no.!+ of Interfacin/ Mo3ule is connecte3 to /roun3

+4LD oard 4ins

1 $ , - 2 6 8 9 1 11 1$

M M M M M M M M M M M M

4o'er s&ppl(

J J

J J

J J

J J

J J

J J

J JJ J

J J

J J

J J

J J

!+ !$

!# !"

!! ! D!+

!> 3nter%acing 0od&le ?

+ $

+ $

# "

!

Zi/a/ pattern

1#5!! !1"5

1+5!> 1$5

15 ?1?5

15+ $1>5

HDL Lab Manual VTU

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