HDL Compiler (Presto Verilog) RM: C. Differences Between HDL …read.pudn.com/downloads181/ebook/845528/preug/preug_c.pdf · Table C-1 lists the Verilog 2001 features implemented

vV-2003.12 HDL Compiler (Presto Verilog) Reference Manual

CDifferences Between HDL Compiler (PrestoVerilog) and the Original HDL Compiler C

This appendix describes new features and the differences betweenHDL Compiler (Presto Verilog) and the original HDL Compiler, in thefollowing sections:

• Verilog 2001 Features

• Other New Features and Enhancements

• Features and Variables Not Supported

• Deprecated Features

• Changes From the Original HDL Compiler Tool

• Implementation Differences

• Public Variables for HDL Compiler (Presto Verilog)

/ C-1HOME CONTENTS INDEX

E-mail your comments about Synopsys documentation to [email protected]

mailto:[email protected]


Verilog 2001 Features

Table C-1 lists the Verilog 2001 features implemented by HDLCompiler (Presto Verilog). For additional information on thesefeatures, see IEEE Std 1364-2001. For information about other newfeatures and enhancements, see Table C-3 on page C-35.

Table C-1 Verilog 2001 Features

Feature Description

As of Version 2003.12

Constant function support Allows parameter and local parameter assignments thatcontain calls to constant functions.

Verilog 2001 constant functions are supported on theright-hand side of a parameter assignment, as shown below.

module ram (input_bus);

parameter SIZE = 1024;

parameter word_width = clogb2(SIZE);

input [word_width -1 : 0] input_bus;

function integer clogb2 (input [31:0] depth);

begin

for (clogb2=0; depth>0; clogb2=clogb2+1)

depth = depth >> 1;

end

endfunction

...

endmodule

The following usage is not supported:

parameter mem_size = 256;

input [my_log2(mem_size)-1:0] address_bus; //error

...

function integer my_log2 (input [31:0] size);

...





Local parameter support Presto Verilog fully supports the localparam construct.


No Verilog 2001 featureswere added.


No Verilog 2001 featureswere added.


Generate statement For description and example, see “generate Statements” onpage C-7.

translate_off andtranslate_on

The //synopsys translate_off directive and the //synopsystranslate_on directive are deprecated; their function isreplaced with the SYNTHESIS macro and the appropriateconditional directives (ìfdef, ìfndef, èlse, èndif). For details,see “Deprecated Features” on page C-58.

SYNTHESIS macro To suspend translation of the source code for synthesis, PrestoVerilog supports the macro SYNTHESIS. For details, see“Standard Macros (SYNTHESIS, PRESTO, VERILOG_2001,and VERILOG_1995)” on page 7-6 and “DeprecatedFeatures” on page C-58.

Table C-1 Verilog 2001 Features (Continued)

Feature Description





Implicit net declarations forcontinuous assignments

If an identifier appears on the left-hand side of a continuousassignment statement, and that identifier has not beendeclared previously, then Presto assumes an implicit scalarnet declaration.

For example, the following two module declarations areequivalent:

module m1 (output out, input in);

wire t ;

assign t = in ;

assign out = t ;

endmodule

module m2 (output out, input in) ;

assign t = in ;

assign out = t ;

endmodule

Notice that the explicit wire declaration is no longer needed.

`line directive The `line directives are inserted by preprocessing tools topreserve information for other tools about the line numbersand file names of the original source files, so that diagnosticmessages can still refer to them.


Expanded ANSI-C-styleport declarations

See “Full ANSI Style Declaration Support” on page C-8.


Casting operators Allows sign control; preserves the value of the argument.Casting operators are $signed() and $unsigned(). See See“Controlling Signs With Casting Operators” on page C-19.


Feature Description





Parameter passing by name(IEEE 12.2.2.2)

Allows setting parameters on subdesigns by parameter name;it is not sensitive to number or declaration order of parameters.You only need to specify the subset of parameters you want toset.

For example, assuming

module m1 (x, y);

parameter p = 7;

parameter q = 8;

parameter r = 9;

then

m1 #(.r(3), .p(1)) u1 (x, y)

is equivalent to

m1 #(1,8,3) u1 (x, y);

Implicit event expression list(IEEE 9.7.5)

Makes always blocks sensitive to any variable read.Syntax: (@*)The event expression does not need to list net and variableidentifiers; they are automatically added to the eventexpression. If you do not use this syntax and the tool finds anincomplete sensitivity list, the tool will issue a warning.

ANSI-C-style portdeclaration(IEEE 12.3.3)

You can list types when declaring port values—for example,module t (input [1:0] in, output [2:0] out). For additionalexamples, see “Full ANSI Style Declaration Support” onpage C-8.


Signed/unsignedparameters(IEEE 3.11)

See “Signed Quantities” on page C-14.


Feature Description





Signed/unsigned nets andregisters(IEEE 3.2, 4.3)


Signed/unsigned sized andbased constants(IEEE 3.2)


New array functionalityMultidimensional arrays(IEEE 3.10.3)Arrays of nets(IEEE 3.10)

See “New Array Functionality” on page C-11.

New operators See “New Operators” on page C-27.

Part select addressing ([+:]and [-:] operators)(IEEE 4.2.1)

See “New Operators” on page C-27.

Power operator (**)(IEEE 4.1.5)


Arithmetic shift operators(<<< and >>>)(IEEE 4.1.12)


Sized parameters(IEEE 3.11.1)

A bit range can be used when declaring parameters.

New compiler directivesìfndef, èlsif, ùndef(IEEE 19.4,19.3.2)

See See “New Operators” on page C-27.

New compiler directivesìfdef VERILOG_2001 andìfdef VERILOG_1995

See See “Standard Macros (SYNTHESIS, PRESTO,VERILOG_2001, and VERILOG_1995)” on page 7-6. Thedc_shell variable for enabling/disabling Verilog 2001 mode is:hdlin_vrlg_std.

Set hdlin_vrlg_std = 1995 to disable Verilog 2001features. Default is hdlin_vrlg_std = 2001, which enablesVerilog 2001 features.


Feature Description





generate Statements

The generate statement is an IEEE 1364-2001 Verilog construct thatmakes the language easier to use by simplifying the RTL codeneeded to repeat a group of concurrent statements or componentinstantiations.

In Example C-1, a generate loop is constructed around a flip-flop andexecuted three times making three flip-flops.

Example C-1 generate statementmodule gen (clk, din, dout); parameter N = 3; input clk; input [N-1:0] din; output [N-1:0] dout; reg [N-1:0] dout; genvar i; generate for (i = 0; i < N; i = i+1) begin : my_generate_loop always @ (posedge clk) dout[i] <= din[i]; end endgenerateendmodule

HDL Compiler (Presto Verilog) builds three sequential genericelements—SEQGENs—which, when compiled, are implemented asshown in Figure C-2.

Comma-separatedsensitivity lists(IEEE 4.1.15 and 9.7.4)

Signals in the sensitivity list can be separated with commas.


Feature Description





For additional information, see the IEEE Std 1364-2001, IEEEStandard Verilog Hardware Description Language.

Figure C-1 generate Statement—Compiled Gates

Full ANSI Style Declaration Support

HDL Compiler supports full ANSI style declarations as shown inExample C-2.

Example C-2 Supported ANSI Style Declarations

module m1 (input [3:0]a, output [3:0]b); endmodule

module m2 (input [3:0]a, output reg signed [3:0]b);

function [3:0] f (input [3:0] x);begin

f = x;endendfunction

always @*begin





b = f(a);end

endmodule

module m3 (input [3:0]a, output reg [3:0]b);

task t (input [3:0] x);begin

b = x;endendtask

always @*begin

t(a);end

endmodule

module m4 (input [7:0] a, output reg [7:0] b);defparam t.testb = 8, t.testa=1, t.WIDTH=1;test #(8) t (a, b);

endmodule

module test #(parameter WIDTH=4, testa=5, testb=6) ( input[WIDTH-1:0] in,output[WIDTH-1:0] out);// Instead of declaring parameters inside the body of themodule,// the ANSI style allows you to declare parameters this way.endmodule

module m5 (input signed [7:0]a, output signed [7:0]b);endmodule

module m6 (input signed a, output signed b); endmodule

module m7 (input wire signed [7:0]a, output wire signed[7:0]b);





endmodule

module m8 (input tri signed [7:0]a, output tri b); endmodule

module m9 (input tri [7:0]a, output tri signed b); endmodule

module m10 (input [3:0]a, output reg signed [3:0]b);

function [3:0] f (input signed [3:0] x);begin

f = x;endendfunction

always @*begin

b = f(a);end

endmodule

module m11 (input [3:0]a, output reg [3:0]b);

task t (input signed [3:0] x, output reg signed [3:0] y);begin

y = x;endendtask

always @*begin

t(a,b);end

endmodule





New Array Functionality

HDL Compiler (Presto Verilog) supports multidimensional arrays ofany variable or net data type. This added functionality is shown inExamples C-3 through C-6.





Example C-3 Multidimensional Arrays: Code and Gates

module m (a, z); input [7:0] a;

output z;

reg t [0:3][0:7];

integer i, j;

integer k;

always @(a) begin

for (j = 0; j < 8; j = j + 1) begin

t[0][j] = a[j];

end for (i = 1; i < 4; i = i + 1) begin

k = 1 << (3-i);

for (j = 0; j < k; j = j + 1) begin

t[i][j] = t[i-1][2*j] ^ t[i-1][2*j+1];

end

end

end

assign z = t[3][0];

endmodule

a [0:7]





Example C-4 Arrays of Nets: Code and Gates

Example C-5 Multidimensional Array Variable Subscripting

reg [7:0] X [0:7][0:7][0:7];

assign out = X[a][b][c][d+:4];

Verilog 2001 allows more than one level of subscripting on a variable,without using a temporary variable.

Example C-6 Multidimensional Array

module test(in, en, out, addr_in, addr_out_reg,addr_out_bit, clk);

input [7:0] in; input en, clk; input [2:0] addr_in, addr_out_reg, addr_out_bit; reg [7:0] MEM [0:7]; output out;

assign out = MEM[addr_out_reg][addr_out_bit];

always @(posedge clk) if (en) MEM[addr_in] = in;endmodule

module m (a, z);

input [0:3] a;

output z;

wire x [0:2] ;

assign x[0] = a[0] ^ a[1];

assign x[1] = a[2] ^ a[3];

assign x[2] = x[0] ^ x[1];

assign z = x[2];

endmodule





Signed Quantities

HDL Compiler (Presto Verilog) supports signed arithmeticextensions. Function returns and data types reg and net can bedeclared as signed. This added functionality is shown inExamples C-7 through C-12.

Example C-7 Signed I/O Ports: Code and Circuit

// This results in a// sign-extension.

// (that is, z[0] should be// connected to a[0])

module m1 (a, z);

input signed [0:3] a;

output signed [0:4] z;

assign z = a;

endmodulea [0:3]

a [1] z [2]

a [0] z [0:1]

a [2] z [3]

a [3] z [4]

z [0:4]





Example C-8 Signed Constants: Code and Gates

Example C-9 Signed Registers: Code and Gates

// Because 3’sb111 is signed,

// a signed adder is used; z[0] will// not be logic 0. ADD_TC_OP denotes

// a 2’s complement, that is, a// signed adder.module m2 (a, z);

input signed [0:2] a;

output [0:4] z;

assign z = a + 3’sb111;

endmodule

//Because 4’sd5 is signed, a//signed comparator (LT_TC_OP)//is used. module m3 (a, z);

input [0:3] a;

output z;

reg signed [0:3] x;

reg z;

always begin

x = a;

z = x < 4’sd5;

end

endmodule

ADD_TC_OP

LT_TC_OP





Example C-10 Signed Types: Code and Gates

Example C-11 Signed Nets: Code and Gates

//Because in1, in2, and out are// signed, a signed multiplier// (MULT_TC_OP_8_8_8)//is usedmodule m4 (in1, in2, out);

input signed [7:0] in1, in2;

output signed [7:0] out;

assign out = in1 * in2;

endmodule

// This results in a signed subtracter//(SUB_TC_OP).module m5 (a, b, z);

input [1:0] a, b;

output [2:0] z;

wire signed [1:0] x = a;

wire signed [1:0] y = b;

assign z = x - y;

endmodule

MULT_TC_OP_8_8_8

in1[7:0]

in2[7:0]

out[7:0]

012

z[0]z[1]z[2]

01

01

a[0]a[1]

b[0]b[1]

sub

SUB_TC_OP





Example C-12 Signed Values

Verilog 2001 adds the signed keyword in declarations:reg signed [7:0] x;

It also adds a new feature for signed, sized constants. For example,8'sb11111111 is an 8-bit signed quantity representing -1. If you areassigning it to a variable that is 8 bits or less, 8'sb11111111 is thesame as the unsigned 8'b11111111. A behavior difference ariseswhen the variable being assigned to is larger than the constant. Thisdifference occurs because signed quantities are extended with thehigh-order bit of the constant, whereas unsigned quantities areextended with 0's. When used in expressions, the sign of theconstant helps determine whether the operation is performed assigned or unsigned.

HDL Compiler (Presto Verilog) enables signed types by default; todisable signed types, set hdlin_unsigned_integers to true.

//Because 4’sd5 is signed, a//signed comparator (LT_TC_OP)//is used.

module m6 (a, z);

input [3:0] a;

output z;

reg signed [3:0] x;

wire z;

always @(a) begin

x = a;

end

assign z = x < -4’sd5;

endmodule

0123

0123

a[0]a[1]a[2]a[3]

z<+v

LT_TC_OP





Note:When synthesizing expressions containing variables declared asinteger, the original HDL Compiler did not consider the integertype to be a “hardware” data type and generated unsignedcomponents; HDL Compiler (Presto Verilog) synthesizes thesigned versions of arithmetic operators for expressions whosetype is integer. HDL Compiler (Presto Verilog) behavior conformsmore closely to the IEEE Standard.

Any designs that use the integer type for expressions that cannotbe completely evaluated at the time of elaboration may beaffected by this change. However, computations that are knownconstants at compile time are not affected (for example,calculation of for loop bounds). You should evaluate whether thischange will affect your design.

To obtain the original behavior, sethdlin_unsigned_integers to true. Note that if you use thekeyword signed, any signed constant in your code, or explicittype casting between signed and unsigned types, HDL Compiler(Presto Verilog) issues a warning and forceshdlin_unsigned_integers back to false.

Comparisons With Signed Types

Verilog sign rules are tricky. All inputs to an expression must besigned to obtain a signed operator. If one is signed and oneunsigned, then both are treated as unsigned. Any unsigned quantityin an expression makes the whole expression unsigned and theresult doesn’t depend on the sign of left-hand side. Someexpressions always produce an unsigned result; these include bitand part-select and concatenation. See IEEE P1364/P5 Section4.5.1.





You need to control the sign of the inputs yourself if you want tocompare a signed quantity against an unsigned one. The same istrue for other kinds of expressions. See Example C-14 andExample C-13.

Example C-13 Unsigned Comparison Results When Signs AreMismatched

module m8 (in1, in2, lt);// in1 is signed but in2 is unsigned input signed [7:0] in1; input [7:0] in2; output lt; wire uns_lt, uns_in1_lt_64;/* comparison is unsigned because of the sign mismatch, in1is signed but in2 is unsigned */ assign uns_lt = in1 < in2;/* Unsigned constant causes unsigned comparison; so negativevalues of in1 would compare as larger than 8’d64 */ assign uns_in1_lt_64 = in1 < 8'd64; assign lt = uns_lt + uns_in1_lt_64;endmodule

Example C-14 Signed Values

module m7 (in1, in2, lt, in1_lt_64); input signed [7:0] in1, in2; // two signed inputs output lt, in1_lt_64; assign lt = in1 < in2; // comparison is signed

// using a signed constant results in a signed comparison assign in1_lt_64 = in1 < 8'sd64;endmodule

Controlling Signs With Casting Operators

Use the Verilog 2001 casting operators, $signed() and $unsigned(),to convert an unsigned expression to a signed expression. InExample C-15, the casting operator is used to obtain a signedcomparator. Note that simply marking an expression as signed might





give undesirable results because the unsigned value might beinterpreted as a negative number. To avoid this problem, zero-extendunsigned quantities, as shown in Example C-15.

Example C-15 Casting Operatorsmodule m9 (in1, in2, lt); input signed [7:0] in1; input [7:0] in2; output lt; assign lt = in1 < $signed ({1’b0, in2}); //Cast to get signed comparator.

//Zero-extend to preserve interpretationof unsigned value as positive number.

Sign Conversion Warnings

When reading a design that contains signed expressions andassignments, HDL Compiler warns you when there are signmismatches by outputting a VER-318 warning. This warning can bedisabled by setting hdlin_warn_implicit_sign_conv to false.Default is true.

Note that beginning with the U-2003.06 release, HDL Compiler nolonger issues a signed/unsigned conversion warning (VER-318) if allof the following conditions are true:

• The conversion is necessary only for constants in the expression.

• The width of the constant would not change as a result of theconversion.

• The most significant bit (MSB) of the constant is zero(nonnegative).

Consider Example C-16. Here, even though Presto Verilog implicitlyconverts the type of the constant “1,” which is by default signed, tounsigned, the VER-318 warning is not issued because the abovethree conditions are true.





Example C-16 Mixed Unsigned and Signed Typesinput [3:0] a, b;output [5:0] z;assign z = a + b + 1;

In releases before U-2003.06, HDL Compiler would always issue a(VER-318) unsigned/signed warning if an arithmetic expressioncontained mixed unsigned and signed types, including constants,because implicit type conversion is required to make the expressioncompatible with the type being assigned. Note that integer constantsare treated as signed types by default.

The VER-319 warning indicates that the compiler has implicitlyconverted

• An unsigned expression to a signed expression

• A signed expression to an unsigned expression

or it has assigned

• An unsigned right-hand side to a signed left-hand side

• A signed right-hand side to an unsigned left-hand side

For example, in this code

reg signed [3:0] a;reg [7:0] c;

a = 4'sb1010;c = a+7'b0101011;





an implicit signed/unsigned conversion occurs—the signed operanda is converted to an unsigned value and the VER-318 warning"signed to unsigned conversion occurs" is issued. Note that a will notbe sign-extended. This behavior is in accordance with the Verilog2001 standard.

When explicit type casting is used, conversion warnings are notissued. For example, in the code above, to force a to be unsigned,you assign c as follows:

c = $unsigned(a)+7'b0101011;

no warning is issued.

Consider the following assignment:

reg [7:0] a;

a = 4'sb1010;

A VER-318 warning "signed to unsigned assignment occurs" isissued when this code is read. Note that although the left side isunsigned, the right side will still be sign-extended—in other words, awill have the value 8'b11111010 after the assignment.

If there is more than one implicit conversion in a line, such as theexpression assigned to c in the example below, only one warningmessage will be issued.

reg signed [3:0] a;reg signed [3:0] b;reg signed [7:0] c;

c = a+4'b0101+(b*3'b101);





Note that a and b are converted to unsigned values and because thewhole right side is unsigned, assigning it to c will also result in thewarning.

Note that integers are considered to have signed values and willgenerate VER-318 warnings accordingly. The code below usesintegers and will issue VER-318 warnings.

module m17(y, count1, z); input [3:0] y, count1;output [3:0] z; reg [3:0] x, z, count; always @ (y, count1) begin x = 2; count = count1; while (x < 15) begin count = count + 1; x = x + 1; end z = count; endendmodule

The code in Example C-17 generates eight VER-318 warnings.

Example C-17 Modules m1 Through m9 1 module m1 (a, z); 2 input signed [0:3] a; 3 output signed [0:4] z; 4 assign z = a; 5 endmodule 6 7 8 module m2 (a, z); 9 input signed [0:2] a; 10 output [0:4] z; 11 assign z = a + 3'sb111; 12 endmodule 13 14 15 module m3 (a, z);





16 input [0:3] a; 17 output z; 18 reg signed [0:3] x; 19 reg z; 20 always begin 21 x = a; 22 z = x < 4'sd5; /* note that x is signed and compared to 4'sd5,which is also signed, but the result of the comparison is put into z, an unsignedreg. This appears to be a sign mismatch; however, no VER-318 warning is issuedfor this line because comparison results are always considered unsigned. Thisis true for all relational operators. */ 23 end 24 endmodule 25 26 27 module m4 (in1, in2, out); 28 input signed [7:0] in1, in2; 29 output signed [7:0] out; 30 assign out = in1 * in2; 31 endmodule 32 33 34 module m5 (a, b, z); 35 input [1:0] a, b; 36 output [2:0] z; 37 wire signed [1:0] x = a; 38 wire signed [1:0] y = b; 39 assign z = x - y; 40 endmodule 41 42 43 module m6 (a, z); 44 input [3:0] a; 45 output z; 46 reg signed [3:0] x; 47 wire z; 48 always @(a) begin 49 x = a; 50 end 51 assign z = x < -4'sd5; 52 endmodule 53 54 module m7 (in1, in2, lt, in1_lt_64); 55 input signed [7:0] in1, in2; // two signed inputs 56 output lt, in1_lt_64; 57 assign lt = in1 < in2; // comparison is signed 58 59 // using a signed constant results in a signed comparison 60





61 assign in1_lt_64 = in1 < 8'sd64; 62 endmodule 63 64 65 module m8 (in1, in2, lt); 66 67 // in1 is signed but in2 is unsigned 68 69 input signed [7:0] in1; 70 input [7:0] in2; 71 output lt; 72 wire uns_lt, uns_in1_lt_64; 73 74 /* comparison is unsigned because of the sign mismatch; in1 is signedbut in2 is unsigned */ 75 76 assign uns_lt = in1 < in2; 77 78 /* Unsigned constant causes unsigned comparison; so negative values ofin1 would compare as larger than 8'd64 */ 79 80 assign uns_in1_lt_64 = in1 < 8'd64; 81 assign lt = uns_lt + uns_in1_lt_64; 82 83 endmodule 84 85 86 87 module m9 (in1, in2, lt); 88 input signed [7:0] in1; 89 input [7:0] in2; 90 output lt; 91 assign lt = in1 < $signed ({1'b0, in2}); 92 endmodule 93 94

The eight VER-318 warnings generated by the code inExample C-17 are shown in Example C-18.

Example C-18 Sign Conversion Warnings for m1 Through m9Warning: /usr/00budgeting/vhdl-mr/warn-sign.v:11: signed to unsigned assignmentoccurs. (VER-318)Warning: /usr/00budgeting/vhdl-mr/warn-sign.v:21: unsigned to signed assignmentoccurs. (VER-318)





Warning: /usr/00budgeting/vhdl-mr/warn-sign.v:21: ’a’ is read but does notappear in the sensitivity list of this ’always’ block. (ELAB-292)Warning: /usr/00budgeting/vhdl-mr/warn-sign.v:37: unsigned to signed assignmentoccurs. (VER-318)Warning: /usr/00budgeting/vhdl-mr/warn-sign.v:38: unsigned to signed assignmentoccurs. (VER-318)Warning: /usr/00budgeting/vhdl-mr/warn-sign.v:39: signed to unsigned assignmentoccurs. (VER-318)Warning: /usr/00budgeting/vhdl-mr/warn-sign.v:49: unsigned to signed assignmentoccurs. (VER-318)Warning: /usr/00budgeting/vhdl-mr/warn-sign.v:76: signed to unsigned conversionoccurs. (VER-318)Warning: /usr/00budgeting/vhdl-mr/warn-sign.v:80: signed to unsigned conversionoccurs. (VER-318)Presto compilation completed successfully.Current design is now ’/usr/00budgeting/vhdl-mr/m1.db:m1’m1 m2 m3 m4 m5 m6 m7 m8 m9

Table C-2 describes what caused the warnings listed inExample C-18.

Table C-2 Sign Mismatch Warnings (VER-318)

Module Cause of warning

m1, m4, and m7 These modules do not have any sign conversion warnings because thesigns are consistently applied.

m9 This module does not issue a VER-318 warning because, even though in1and in2 are sign mismatched, the casting operator is used to force the signon in2. When a casting operator is used, no warning is returned when signconversion occurs.

m2 In this module, a is signed and added to 3‘sb111 which is signed and hasa value of -1. However, z is not signed so the value of the expression onthe right, which is signed, will be converted to unsigned when assigned toz. The VER-318 warning “signed to unsigned assignment occurs” isissued.





New Operators

New operator support is described in the following three sections:

• Variable Part-Select Overview

• Power Operator (**)

• Arithmetic Shift Operators (<<< and >>>)

m3 In this module, a is unsigned but put into the signed reg x. Here a will beconverted to signed and a VER-318 warning “unsigned to signedassignment occurs” is issued.Note that in line 22 (z = x < 4'sd5) x is signed and compared to 4'sd5, whichis also signed, but the result of the comparison is put into z, an unsignedreg. This appears to be a sign mismatch; however, no VER-318 warning isissued for this line because comparison results are always consideredunsigned. This is true for all relational operators.

m5 In this module, a and b are unsigned but they are assigned to x and y,which are signed. Two VER-318 warnings “unsigned to signed assignmentoccurs” are issued. In addition, y is subtracted from x and assigned to z,which is unsigned. Here the VER-318 warning “signed to unsignedassignment occurs” is also issued.

m6 In this module, a is unsigned but put into the signed register x. TheVER-318 warning “unsigned to signed assignment occurs” is issued.

m8 In this module, in1 is signed and compared with in2, which is unsigned,and 8‘d64, which is an unsigned value.

For each expression, the VER-318 warning “signed to unsignedconversion occurs” is issued.

Table C-2 Sign Mismatch Warnings (VER-318) (Continued)

Module Cause of warning





Part-Select Addressing Operators ([+:] and [-:])

Verilog 2001 introduces variable part-select operators. Theseoperators allow you to use variables to select a group of bits from avector. In some designs, coding with part-select operators improveselaboration time and memory usage. For more information on codingrecommendations, see “Use Variable Part-Select Operators toImprove Elaboration Time and Memory Usage” on page 2-46.

This section contains the following:

• Variable Part-Select Overview

• Example—Ascending Array and +:

• Example—Ascending Array and -:

• Example—Descending Array and -:

• Example—Descending Array and +:

Variable Part-Select Overview. A Verilog 1995 part-select operatorrequires that both upper and lower indexes be constant: a[2:3] ora[value1:value2].

The variable part-select operator permits selection of a fixed-widthgroup of bits at a variable base address and takes the following form:

• [base_expr +: width_expr] for a positive offset

• [base_expr -: width_expr] for a negative offset

The syntax specifies a variable base address and a known constantnumber of bits to be extracted. The base address is always writtenon the left, regardless of the declared direction of the array. The





language allows variable part-select on the left-hand side (LHS) andthe right-hand side (RHS) of an expression. All of the followingexpressions are allowed:

• data_out = array_expn[index_var +: 3](part select is on the right-hand side)

• data_out = array_expn[index_var -: 3] (part select is on the right-hand side)

• array_expn[index_var +: 3] = data_in (part select is on the left-hand side)

• array_expn[index_var -: 3] = data_in(part select is on the left-hand side)

The table below shows examples of Verilog 2001 syntax and theequivalent Verilog 1995 syntax.

The original HDL Compiler tool allows nonconstant part-selects if thewidth is constant; HDL Compiler (Presto Verilog) permits only thenew syntax.

Verilog 2001 syntax Equivalent Verilog 1995 syntax

a[x +: 3]for a descending array

{ a[x+2], a[x+1], a[x] } a[x+2 : x]

a[x -: 3]for a descending array

{ a[x], a[x-1], a[x-2] } a[x : x-2]

a[x +: 3]for an ascending array

{ a[x], a[x+1], a[x+2] } a[x : x+2]

a[x -: 3]for an ascending array

{ a[x-2], a[x-1], a[x] } a[x-2 : x]





]

Example—Ascending Array and +:. The code below uses the +:operator to select bits from Ascending_Array.

reg [0:7] Ascending_Array;... Data_Out = Ascending_Array[Index_Var +: 3];

The value of Index_Var determines the starting point for the bitsselected. The bits selected are shown below as a function ofIndex_Var.

Note:

• Ascending_Array[Index_Var +: 3] is functionally equivalent to thefollowing non-computable part-select:Ascending_Array[Index_Var : Index_Var + 2]

• Non-computable part-selects are not supported by the Veriloglanguage. Ascending_Array[7 +:3] corresponds to elementsAscending_Array[7 : 9] but elements Ascending_Array[8] andAscending_Array[9] do not exist. A variable part-select mustalways compute to a valid index, otherwise there will be asynthesis elaborate error and a run-time simulation error.

Ascending_Array [ 0 1 2 3 4 5 6 7

Index_Var = 0 • • • • • • • •

Index_Var = 1 • • • • • • • •

Index_Var = 2 • • • • • • • •

Index_Var = 3 • • • • • • • •

Index_Var = 4 • • • • • • • •

Index_Var = 5 • • • • • • • •

Index_Var = 6 not valid, synthesis/simulation mismatch; see note below.

Index_Var = 7 not valid, synthesis/simulation mismatch: see note below.





]

Example—Ascending Array and -:. The code below uses the -:operator to select bits from Ascending_Array.

reg [0:7] Ascending_Array;... Data_Out = Ascending_Array[Index_Var -: 3];


Ascending_Array[Index_Var -: 3] is functionally equivalent to thefollowing non-computable part-select:

Ascending_Array[Index_Var - 2 : Index_Var]

Example—Descending Array and -:. The code below uses the -:operator to select bits from Descending_Array.

reg [7:0] Descending_Array;... Data_Out = Descending_Array[Index_Var -: 3];

Ascending_Array [ 0 1 2 3 4 5 6 7

Index_Var = 0 not valid, synthesis/simulation mismatch


Index_Var = 2 • • • • • • • •

Index_Var = 3 • • • • • • • •

Index_Var = 4 • • • • • • • •

Index_Var = 5 • • • • • • • •

Index_Var = 6 • • • • • • • •

Index_Var = 7 • • • • • • • •





]


Descending_Array[Index_Var -: 3] is functionally equivalent to thefollowing non-computable part-select:

Descending_Array[Index_Var : Index_Var - 2]

Example—Descending Array and +:. The code below uses the +:operator to select bits from Descending_Array.

reg [7:0] Descending_Array;... Data_Out = Descending_Array[Index_Var +: 3];

Descending_Array [ 7 6 5 4 3 2 1 0



Index_Var = 2 • • • • • • • •

Index_Var = 3 • • • • • • • •

Index_Var = 4 • • • • • • • •

Index_Var = 5 • • • • • • • •

Index_Var = 6 • • • • • • • •

Index_Var = 7 • • • • • • • •





]


Descending_Array[Index_Var +: 3] is functionally equivalent to thefollowing non-computable part-select:

Descending_Array[Index_Var + 2 : Index_Var]

Non-computable part-selects are not supported by the Veriloglanguage. Descending_Array[7 +:3] corresponds to elementsDescending_Array[9 : 7] but elements Descending_Array[9] andDescending_Array[8] do not exist. A variable part-select must alwayscompute to a valid index, otherwise there will be a synthesiselaborate error and a run-time simulation error.

Power Operator (**)

This operator performs yx, as shown in Example C-19.

Example C-19 Power Operators

module m (a, z);

Descending_Array [ 7 6 5 4 3 2 1 0

Index_Var = 0 • • • • • • • •

Index_Var = 1 • • • • • • • •

Index_Var = 2 • • • • • • • •

Index_Var = 3 • • • • • • • •

Index_Var = 4 • • • • • • • •

Index_Var = 5 • • • • • • • •







input [3:0] a; output [7:0] x, y, z; assign z = 2 ** a; assign x = a ** 2; assign y = b ** c // where b and c are constantsendmodule

Arithmetic Shift Operators (<<< and >>>)

The arithmetic shift operators allow you to shift an expression andstill maintain the sign of a value, as shown in Example C-20. Whenthe type of the result is signed, the arithmetic shift operator (>>>)shifts in the sign bit; otherwise, it shifts in zeros.

Example C-20 Shift Operator Code and Gates

module s1 (A, S, Q);

input signed [3:0] A;

input [1:0] S;

output [3:0] Q;

reg [3:0] Q;

always @(A or S)

begin

// arithmetic shift right,//shifts in sign-bit from left

Q = A >>> S;

end

endmodule

o

o

o

o

o





Other New Features and Enhancements

HDL Compiler (Presto Verilog) offers Verilog 2001 features—seeTable C-1 on page C-2—and other new features and enhancementslisted in Table C-3.

Table C-3 Other HDL Compiler (Presto Verilog) Features

HDL Compiler (Presto Verilog)New or enhanced features

Description


Blocking and non-blockingassignments

By default, you cannot make blocking and non-blockingassignments to the same variable. In previous versions,this was possible.

Net preservation Unloaded nets can be preserved. For details, see“Internal Net Preservation” on page 2-16.

hdlin_check_no_latch The variable hdlin_check_no_latch is supported.(STAR 157113)


No features were added.


Variables added:hdlin_seqmap_async_search_depthhdlin_seqmap_sync_search_depth

The hdlin_seqmap_search_depth variable is obsoleteand has been replaced with thehdlin_seqmap_async_search_depth variable

and

the hdlin_seqmap_sync_search_depth variable

Version 2003.03

Sequential cell preservation For details, see “Sequential Cell Preservation” onpage 2-14.





map_to_module enhancement map_to_module supports tasks as well as functions. Fordetails, see “map_to_module and return_port_name”on page 7-17.

translate_off andtranslate_on

The //synopsys translate_off directive and the//synopsys translate_on directive are deprecated.

For details, see “Deprecated Features” on page C-58.

Version 2002.05

Automatic detection of input file type HDL Compiler can automatically detect if your design isa gate-level netlist or an RTL design and use the bestreader for your design. For details, see “Starting HDLCompiler” on page 1-4.

DC Ultra datapath optimization DC Ultra enables datapath extraction after timing-drivenresource sharing and explores various datapath/resource-sharing options during compile. For details,see “Datapaths” on page 2-38.

Finite State Machines (FSMs)verification

As of release 2002.05, enumerated types—used inFSMs—are recognized by both Formality and DC Ultra(compare_design -fsm and compile -verify) andthe typical FSM coding style, shown in Example 4-46 onpage 4-40, can be verified by Formality.

Automatic detection of finite statemachines (FSMs)

Automatic detection of finite state machines (FSMs)

In the 2002.05 release, HDL Compiler introducesautomatic detection and inference of finite statemachines. Combined with the new automatic FSMextraction feature in Design Compiler, FSM synthesis issimplified to just reading and compiling your code. Fordetails, see “Finite State Machines” on page 4-35.

Table C-3 Other HDL Compiler (Presto Verilog) Features (Continued)


Description






Displays synthesis progress Reports on synthesis progress. This is helpful forprinting out compile-time computations on parameters,or the number of times a loop executes.Uses the system task - $display.See “Using $display During RTL Elaboration” onpage C-52.

Models simulator behavior Simulates simulator behavior by allowing writing toout-of-bounds array locations using the new variablehdlin_dyn_array_bounds_check. See “Writing toOut-of-Bounds Array Locations” on page C-50.

Improved logic for left side arrayreferences

See “Improved Logic for Array Reference on the LeftSide” on page C-53.

Expanded MUX-OP inference Get MUX-OP’s for both case and if statements and rightside variable array reference x[a].See “Improved MUX_OP inference” on page C-53.

Sharing array references See “Sharing Array References” on page C-54.

Resource-sharing directives Manual control of resource sharing and implementationselection; these directives were not available in the newHDL Compiler (Presto Verilog) version 2000.11.See “Sharing Using hlo_resource_allocation” onpage 6-7.

Can preserve the value ofprocedure-local variables acrosscalls by inferring latches

New variablehdlin_infer_function_local_latchesSee “Changes From the Original HDL Compiler Tool” onpage C-60.


Arrays of instances See “Arrays of Instances” on page C-46.

defparam statement See “defparam Statement” on page C-38.



Description





defparam Statement

The defparam statement allows overriding parameter values at lowerlevels in the hierarchy, enabling parameter values to be changed inany module instance. It works on submodules only, not on thecurrent module or modules elsewhere in the design. SeeExample C-21.

Example C-21 defparam Statement

module top (x, y, q);input x, y;output q;

defparam mid.bot.p2=2, mid.bot.p3=3;

Combinational while loop See “Combinational while Loop” on page C-40.

Resource sharing for conditionalexpressions

See “Sharing Using hlo_resource_allocation” onpage 6-7.

Divide operator See “Divide Operator” on page C-50.

Modulus operator Operator now supports constant and variable operands.

Shift operator inference Synthetic ops can now be inferred for shift operators(<<, >>)

Text macros Text macros are supported with sized constants.

hdlin_enable_vpp The functions of the preprocessor are built in to HDLCompiler, and the functions are automatically enabled.

ùndefineall See See “ùndefineall” on page 7-8.

New Verilog netlist reader The new reader incorporates algorithms that reduce thememory usage and CPU runtime of the read command.See “New Verilog Netlist Reader” on page C-55.



Description





middle mid (x, y, q);endmodule

module middle (x, y, q);input x, y;output q;

bottom #(0,1) bot (x, y, q);endmoduleendmodulemodule bottom (a, b, q);

input a, b;output q;parameter p0 = 100;parameter p1 = 200;parameter p2 = 300;parameter p3 = 400;assign q = a & b;

endmodule

-------------------p0=0, p1=1, p2=2, p3=3

In Example C-21, the original value of parameter p3 is 400. If youuse the defparam statement, the value is changed as it is passedfrom the top to the middle and finally to the bottom design, in whichp3 changes from 400 to 2. The defparam statement enables eachmodule instantiation to customize declared parameters. The result ofthe code in Example C-21 is p0=0, p1=1, p2=2, and p3=3.

There are three ways a module instantiation can override the valueof a parameter in a submodule. For example, assume that

module m1 (x,y); parameter p = 0;

You can override the parameter p by coding

defparam u1.p = 1;m1 u1 (x,y);

or,





m1 #(1) u1 (x,y);

or,

m1 # (.p(1) u1(x,y);

Combinational while Loop

To create a combinational while loop, write the code so that an upperbound on the number of loop iterations can be determined.Examples of supported combinational while loops are provided inExamples C-22 through C-24. An example of an unsupported loop isshown in Example C-25.

The loop iterative bound must be statically determinable; otherwisean error is reported. If the loop bound cannot be determined, theprogram limits the maximum number of iterations to the value set bythe hdlin_loop_iteration_limit variable and reports anELAB-900 error.

The original HDL Compiler tool supports loops with known upper andlower bounds and known constant steps. For example,

input [9:0] a;// ....i = 0;while ( i < 10 && !a[i] ) begin i = i + 1; // loop bodyend

The original HDL Compiler tool only supports while loops with eventstatements in them (implicit state machines). HDL Compiler (PrestoVerilog) relaxes these restrictions but still needs to be able todetermine an upper bound on the number of trips through the loop at





compile time. In HDL Compiler (Presto Verilog), there are no syntaxrestrictions on the loops. While loops that have no events withinthem, such as in the example below, are supported.

input [9:0] a;// ....i = 0;while ( i < 10 && !a[i] ) begin i = i + 1; // loop bodyend

To support this, HDL Compiler (Presto Verilog) interprets the looplike a simulator. It stops when the loop termination condition is knownto be false. Because it can’t tell when a loop is infinite, it stops andreports an error after an arbitrary (but user defined) number ofiterations (the default is 1000).

In the original HDL Compiler tool, disable is recommended for earlyloop exits; for example,

begin: loop_block for (i = 0; i < 10; i = i+1) begin if(a[i]) disable loop_block; // loop body endend

But HDL Compiler (Presto Verilog) allows additional conditions in theloop condition permitting more concise descriptions.

for (i = 0; i < 10 && a[i]; i = i+1) begin // loop bodyend





A loop must unconditionally make progress toward termination ineach trip through the loop, or it cannot be compiled. The examplebelow makes progress (that is, increments i) only when !done is trueand will not terminate.

while ( i < 10 ) begin if ( ! done ) done = a[i]; // loop body i = i + 1; endend

The modified version below, which unconditionally increments i, willterminate. This code creates the desired logic.

while ( i < 10 ) begin if ( ! done ) begin done = a[i]; end// loop body i = i + 1;end

In the next example, loop termination depends on reading valuesstored in x. If the value is unknown (as in the first and third iterations),HDL Compiler (Presto Verilog) assumes it might be true andgenerates logic to test it.

x[0] = v; // Value unknown: implies “if(v)”x[1] = 1; // Known TRUE: no guard on 2nd tripx[2] = w; // Not known: implies “if(w)”x[3] = 0; // Known FALSE: stop the loop

i = 0;while( x[i] ) begin // loop body i = i + 1;end





This code terminates after three iterations when the loop tests x[3],which contains 0.

In Example C-22, a supported combinational while loop, the codeproduces gates and an event control signal is not necessary.

Example C-22 Supported while Loop Codemodule modified_s2 (a, b, z);parameter N = 3;input [N:0] a, b;output [N:1] z;reg [N:1] z;integer i;always @(a or b or z) begin i = N; while (i) begin z[i] = b[i] + a[i-1]; i = i - 1; end endendmodule

In Example C-23, a supported combinational while loop, no matterwhat x is, the loop will run for 16 iterations at most because HDLCompiler (Presto Verilog) can keep track of which bits of x areconstant. Even though it doesn't know the initial value of x, it doesknow that x >> 1 has a zero in the most significant bit (MSB). Thenext time x is shifted right, it knows that x has two zeros in the MSB,and so on. HDL Compiler (Presto Verilog) can determine when xbecomes all zeros.





Example C-23 Supported Combinational while Loop

Figure C-2 shows the compiled design, while_loop_comb1, from thecode in Example C-23.

Figure C-2 while_loop_comb1 Compiled Design

module while_loop_comb1(x, count); input [7:0] x;

output [2:0] count;

reg [7:0] temp;

reg [2:0] count;

always @ (x)

begin

temp = x;

count = 0;

while (temp != 0)

begin

count = count + 1;

temp = temp >> 1;

end

endendmodule

x[7:0] count[2:0]





In Example C-24, a supported combinational while loop, HDLCompiler (Presto Verilog) knows the initial value of x and candetermine x+1 and all subsequent values of x.

Example C-24 Supported Combinational while Loop

Example C-25 is an unsupported combinational while loop.

Example C-25 Unsupported Combinational while Loop

module combinational-while-loop-unsupported ( x, y);input [3:0] x;output [3:0] x;reg [3:0] x;reg [3:0] count;

while ( x < 15 ) begin count = count + 1; x = x + 1; endendmodule

module whil_loop_comb2(y, count1, z); input [3:0] y, count1;output [3:0] z;

reg [3:0] x, z, count; always @ (y, count1) begin

x = 2;

count = count1;

while (x < 15)

begin

count = count + 1;

x = x + 1;

end

z = count;

end

endmodule





HDL Compiler (Presto Verilog) cannot detect the initial value of x andtherefore cannot determine the value of x+1. Because it neverdetects what any bits of x are, it can never determine when x < 15and cannot create gates for this code.

Arrays of Instances

This feature enables instantiations of modules that contain a rangespecification, which, in turn, allows an array of instances to becreated. See See “Naming Arrays of Instances” on page 8-4. InExample C-26, the module test creates two pipeline registers, that is,a single pipeline with two stages.

Example C-26 Module Test: Code and Gates

In Example C-27, the module array_inst uses the test module tomake three pipelines three stages deep.

module test ( D, CK, Q );

input D, CK;

output Q;

reg Q0, Q;

always @ (posedge CK)

begin

Q0 <= D;

Q <= Q0;

end

endmodule

DQ

CLK





Example C-27 Arrays of Instances: Code and Gates

Another example of array instantiation is shown below in which fourcopies of the dff module are instantiated.

module dff (d, ck, q); input d, ck; output q;...

module array_inst (clk, din, dout);

parameter N=3;

input clk;

input [N-1:0] din;

output [N-1:0] dout;

reg [N-1:0] dout;

wire [N-1:0] idout;

test test1[N-1:0] (.D(din), .CK(clk), .Q(idout));

always @ (posedge clk) begin

dout <= idout;

end

endmodule

module test ( D, CK, Q );

input D, CK;

output Q;

reg Q0, Q;

always @ (posedge CK)

begin

Q0 <= D;

Q <= Q0;

end

endmodule





input ck;input [0:3] d;output [0:3] q;

dff ff[0:3] (d, ck, q);

HDL Compiler (Presto Verilog) unwraps the array instantiation asshown below. Note that ck is connected to each instance, whereas dand q have one bit connected to each instance.


dff ff_0 (d[0], ck, q[0]);dff ff_1 (d[1], ck, q[1]);dff ff_2 (d[2], ck, q[2]);dff ff_3 (d[3], ck, q[3]);

In this next example of array instantiation, x exactly matches thewidth of a on the submodule, so its full width is connected to eachinstantiated module.

module submod (x, ck, y); input [0:3] d; input ck; output q;...input ck;input [0:3] x;output [0:3] y;

submod ff[0:3] (x, ck, y);

The new HDL Compiler unwraps the array instantiation as shownbelow.






submod M_0 (x, ck, y[0]);submod M_1 (x, ck, y[1]);submod M_2 (x, ck, y[2]);submod M_3 (x, ck, y[3]);

In this next example of array instantiation, note that the declaredordering of bits [3:0] of y does not affect the instantiation of submod(compare to the previous example). Bits are connected by positionnot by number.

module submod (x, ck, y); input [0:3] d; input ck; output q;...input ck;input [0:3] x;output [0:3] y;

submod ff[0:3] (x, ck, y);

HDL Compiler (Presto Verilog) unwraps the array instantiation asshown below.


submod M_0 (x, ck, y[0]);submod M_1 (x, ck, y[1]);submod M_2 (x, ck, y[2]);submod M_3 (x, ck, y[3]);





Divide Operator

HDL Compiler (Presto Verilog) supports division where the operandsare not constant by instantiating a DesignWare divider. Note thatwhen you compile a design that contains an inferred divider, youmust have a DesignWare-Foundation license.

Example C-28 Divide Operator: Code and Gates

Writing to Out-of-Bounds Array Locations

Verilog simulators allow writing to out-of-bounds array locations; insimulation, this has no effect on the values stored in the array.However, HDL Compiler assumes that nonconstant array accessesare in bounds. This means that out-of-bounds accesses, as shownin Example C-29, might have unintended consequences and HDLCompiler will issue a warning that the access might be out of bounds.

Example C-29 Out of Bounds Access

module E (addr, data, clk, out, out_addr); reg [2:0] mem; input data, clk; output out; input [2:0] addr, out_addr;

module divide (a, b, z);

input [9:0] a, b;

output [8:0] z;

assign z= a / b;

endmodule divide_DW_div_uns_10_10_0





// Value of addr could be 3..7: possibly out of bounds access

always @(posedge clk) mem[addr] = data;

// Read could be out of bounds too;// In simulation, 1’bx but for synthesis, 1’b0 or 1’b1

assign out = mem[out_addr];endmodule

If you get that warning and you can’t guarantee that the address willbe in-bounds, add an if statement, as shown in Example C-30,around the write to protect it by explicitly testing that the address isin bounds before the assignment.

Example C-30 Added Code to Insure In-Bounds Access

module E (addr, data, clk, out, out_addr); reg [2:0] mem; input data, clk; output out; input [2:0] addr, out_addr; always @(posedge clk)

// Test that addr accesses an in-bounds location.

if ( addr < 4) mem[addr] = data; assign out = mem[out_addr];endmodule

The HDL Compiler (Presto Verilog) optionhdlin_dyn_array_bounds_check = true automatically addsthe code, as shown in Example C-30. This allows you to implementsimulator behavior and guarantees that no out-of-bounds access willaffect values stored in the array. This option increases the area of thedesign.





Using $display During RTL Elaboration

The $display system task is usually used to report on simulationprogress; however, HDL Compiler (Presto Verilog) executes $displaycalls as it sees them. It usually cannot tell the value of variables,except compile-time constants like loop iteration counters. It willexecute all the display statements on all the paths through theprogram as it generates the logic.

Note that because HDL Compiler (Presto Verilog) executes all$display calls, error messages from the Verilog source can beexecuted and can look like unexpected messages.

Using $display is useful for printing out any compile-timecomputations on parameters, or the number of times a loopexecutes. A $display example is shown below.

module F (in, out, clk) parameter SIZE = 1; input [SIZE-1: 0] in; output [SIZE-1: 0] out; reg [SIZE-1: 0] out; input clk;// ...ìfdef PRESTO always $display(“Instantiating F, SIZE=%d”, SIZE);èndifendmodule

F #(2) F2 (in1, out1, clk);F #(32) F32 (in1, out1, clk);

Here is what is output to the screen while elaborating.

dc_shell> elaborate TOPRunning PRESTO HDLC...





Information: Building the design 'F' instantiated from design'TOP' with

the parameters "2". (HDL-193)Running PRESTO HDLCInstantiating F with SIZE = 2

Presto compilation completed successfully.Information: Building the design 'F' instantiated from design'TOP' with

the parameters "32". (HDL-193)Running PRESTO HDLCInstantiating F with SIZE = 32

Improved Logic for Array Reference on the Left Side

Compare the code below.

The original HDL Compiler

• Builds different GTECH circuits for these two cases

• Requires using the style on the right to get the best results

HDL Compiler (Presto Verilog)

• Builds the same GTECH circuit for each case

• Allows using the more concise style on the left

Improved MUX_OP inference

MUX_OPs offer significantly better timing than SELECT_OPs and,in some cases, better layout.

mem[addr] = data;

for (i = 0; i < size; i = i + 1) if ( i == addr ) mem[i] = data;

vs.





Using the original HDL Compiler, there is only one way to get aMUX_OP, and that is to use a case statement with the //synopsysinfer_mux directive.

With HDL Compiler (Presto Verilog), there are three ways to get aMUX_OP:

• Use a case statement with the //synopsys infer_muxdirective.

• Use an if statement with the //synopsys infer_mux directive.

• Use a variable array reference: x[a].

Note that, for Presto, the case statement must be parallel, otherwisea MUX_OP is not inferred and an error is reported. Even when the//synopsys parallel_case directive is used, if the casestatement is not truly parallel, an error is reported. The original HDLCompiler does not require parallel case statements. To avoidMUX_OPs for variable array references, sethdlin_build_selectop_for_var_index to true.

Sharing Array References

Array references with variable subscripts can be an overlookedcause of increased area. HDL Compiler (Presto Verilog) detectswhen you refer to the same array location more than once, andshares the logic. An example is shown below.

out1 = p2[var_index][0];

// ...

out2 = p2[var_index][1];

T = p2[var_index];

out1 = T[0];

// ...

out2 = T[1];





Here, HDL Compiler (Presto Verilog) computes p2[var_index] onlyonce and stores it in T, sharing the result in the T assignments.

Label and Resource Directives—Manual ResourceSharing

Label and resource directives are used for manually controllingresource sharing and implementation selection. They were notsupported in HDL Compiler (Presto Verilog) version 2000.11 but aresupported in HDL Compiler (Presto Verilog) 2001.08. See“Directives That Control Sharing” on page 6-9 and “Sharing Usinghlo_resource_allocation” on page 6-7.

Example

always :b1 /* synopsys resource r0: ops = "op1 op2" map_to_module = "sub" */

if ( p ) z = a - b; // synopsys label op1 else z = c - d; // synopsys label op2

New Verilog Netlist Reader

The Verilog netlist reader incorporates algorithms that reduce thememory usage and CPU runtime of the read command. To use thenew reader, invoke the read command with the -netlist option asshown:

read -netlist -f verilog <file.v>

In Tcl mode, use





read_file -f verilog -netlist <file.v>

Features and Variables Not Supported

The following features are not supported:

• forever loops

• Finite State Machine Compiler (directives will be ignored)

• Toggle flip-flops

• Implicit state machines (planned for future release)The implicit style means using more than one “@posedge clock”in a process.

• label_applies_to directive

• may_merge_with directive (may_merge_with is equivalent toadd_ops == "false")

• dont_merge_with directive (dont_merge_with is equivalentto add_ops == "true")

• async_set_reset_local,async_set_reset_local_all, sync_set_reset_local,and sync_set_reset_local_all (These directives areignored.)

• Describing ops for a resourceOnly labels/hierarchical labels are allowed to describe the ops fora resource. If you want to put another resource in the definition,you need to inline that resource to fit the new syntax.





• As of the 2002.05-2 release, support for the backslash (\)continuation of single-line comments is discontinued. SeeSolvNet article 001630.

The variables listed in Table C-4 are ignored by HDL Compiler(Presto Verilog).

Table C-4 Variables Ignored in HDL Compiler (Presto Verilog)

Name

hdlin_advisor_directory

hdlin_dont_check_param_width

hdlin_enable_analysis_info

hdlin_enable_analysis_info_for_analyze

hdlin_enable_vppThe functions of the preprocessor are built in to HDL Compiler (Presto Verilog), and thefunctions are automatically enabled.

hdlin_hide_resource_line_numbers

hdlin_keep_inv_feedback

hdlin_latch_always_async_set_reset

hdlin_merge_nested_conditional_statements

hdlin_preserve_vpp_files

hdlin_preserve_vpp

hdlin_reg_report_length

hdlin_translate_off_skip_text

hdlin_vpp_temporary_directory

hdlin_write_gtech_design_directory





Deprecated Features

As of 2003.03, the macro SYNTHESIS replaces the macro DCalthough DC is still supported for backward compatibility. See“Standard Macros (SYNTHESIS, PRESTO, VERILOG_2001, andVERILOG_1995)” on page 7-6.

As of 2003.03, to suspend translation of the source code forsynthesis, use the macro SYNTHESIS and the appropriateconditional directives (ìfdef, ìfndef, èlse, èndif) rather thantranslate_off and translate_on, as shown in the followingexample:

Example C-31 Coding for Simulation—Recommended Method

module dff_async (RESET, SET, DATA, Q, CLK); input CLK; input RESET, SET, DATA; output Q; reg Q; // synopsys one_hot "RESET, SET"

always @(posedge CLK or posedge RESET or posedge SET) if (RESET) Q <= 1'b0; else if (SET) Q <= 1'b1; else Q <= DATA; 'ifndef SYNTHESIS always @ (RESET or SET) if (RESET + SET > 1) $write ("ONE-HOT violation for RESET and SET."); 'endif endmodule

Example C-32 Coding for Simulation—Deprecated Method

module dff_async (RESET, SET, DATA, Q, CLK); input CLK; input RESET, SET, DATA;





output Q; reg Q; // synopsys one_hot "RESET, SET" always @(posedge CLK or posedge RESET or posedge SET) if (RESET) Q <= 1’b0; else if (SET) Q <= 1’b1; else Q <= DATA; // synopsys translate_off always @ (RESET or SET) if (RESET + SET > 1) $write ("ONE-HOT violation for RESET and SET."); // synopsys translate_onendmodule

Beginning with the U-2003.06 release, the //synopsystranslate_off directive and the //synopsys translate_ondirective are changed. The code contained within these directives isignored and treated similar to the /* and the corresponding */comment delimiters. In previous releases, HDL Compiler and PrestoVerilog would parse, but not synthesize, the code within thesedirectives; if you wanted the code totally ignored, you needed to setthe variable hdlin_translate_off_skip_text to true. Thevariable hdlin_translate_off_skip_text is ignored becauseit’s function is incorporated into the translate_on/off directives.





Changes From the Original HDL Compiler Tool

Behavior that is changed by HDL Compiler (Presto Verilog) is listedin Table C-5.

Table C-5 Changes

Topic Description

Integers When synthesizing expressions containing variables declared as integer, theoriginal HDL Compiler tool did not consider the integer type to be a “hardware”data type and generated unsigned GTECH components; HDL Compiler(Presto Verilog) synthesizes the signed versions of GTECH arithmeticoperators for expressions whose type is integer. HDL Compiler (PrestoVerilog) behavior conforms more closely to the IEEE Standard.

Any designs that use the integer type for expressions that cannot becompletely evaluated at the time of elaboration may be affected by this change.However, computations that are known constants at compile time are notaffected (for example, calculation of for loop bounds). You should evaluatewhether this change will affect your design.

To obtain the original behavior, set hdlin_unsigned_integers to true. Notethat if you use any signs in your code, HDL Compiler (Presto Verilog) issues awarning and forces hdlin_unsigned_integers back to false.

Three-statedrivers

When all drivers of a multiply driven net are not declared as tri and a tristatecoding style is not used, that is, a conditional assignment of the variable to 1'bzin each block or continuous assignment that drives the variable, HDL Compilerissues an ELAB-366 error by default and no gates are created. You can sethdlin_prohibit_nontri_multiple_drivers to false to report a ELAB-365 warningfor this condition. With this variable false, you will get gates under all conditionsexcept when one of the drivers is a constant, which would create an illegaldesign. In this case, HDL Compiler issues an error.





Resourcedeclaration

HDL Compiler (Presto Verilog) allows only one resource declared in onesynopsys directive. However, multiple resources can be declared for onealways block.

If you want to include more than more one resource for an always block, youcan split them into several synopsys comments:

For example, the original HDL Compiler tool accepted

/* synopsys resource r0: ops = "a0",

resource r1: ops = "a1"; */

HDL Compiler (Presto Verilog) requires you to rewrite it as

/* synopsys resource r0: ops = "a0"; */

/* synopsys resource r1: ops = "a1"; */

ops for aresource

Only labels and hierarchical labels are allowed to describe the ops for aresource. If you want to put another resource in the definition, you need to writeinline code for that resource to fit the new syntax. For example, the code inExample C-36 was accepted by the original HDL Compiler tool but to beaccepted by HDL Compiler (Presto Verilog), the resource declarationschanged must be changed as follows: Remove the declaration for R1 and writeinline code for R1 in R2 as shown in Example C-37. Notice that L5/f1/L2 L5/f1/L3 L6/f1/L2 L6/f1/L3 has replaced L5/R1 L6/R1 in the R2 declaration.

Latches Latch inference improvement

HDL Compiler (Presto Verilog) can optionally preserve the value ofsubprogram-local variables across calls by inferring latches. See See“Persistence of Values Across Calls to Tasks” on page 2-9.

Table C-5 Changes (Continued)

Topic Description





Architecturesin modules

The original Verilog HDL Compiler tool allows you to specify architectures formodules, which is not in accordance with IEEE Std 1364. In Presto Verilog, thisnonstandard behavior is not available. Module names of the form e__a (“e” and“a” separated by two underscores) are not interpreted as <architecture a>of <entity e>, but rather as <entity e__a>, as illustrated in this example:

module e__a(...);

...

endmodule

After analyzing the code in the example, you cannot elaborate it as elaboratee -arch a. It was possible to do so with the original HDL Compiler tool. Thenew functionality in Presto Verilog is consistent with standard Verilog. To runthe original HDL Compiler tool, set hdlin_enable_presto to false.

Variables innamed alwaysblock

In HDL Compiler (Presto Verilog), variables declared locally within a namedalways block may be put into a latch or flip-flop if necessary. The original HDLCompiler tool does not generate flip-flops for such reg declarations. To disablethis in HDL Compiler (Presto Verilog), sethdlin_infer_block_local_latches to false. The default and recommendedvalue for the variable is true.

MUX_OPinference

To infer a MUX_OP, Presto requires that the case statement be parallel,otherwise a MUX_OP is not inferred and an error is reported. Even when the//synopsys parallel_case directive is used, if the case statement is not

truly parallel, an error is reported. The original HDL Compiler does not requireparallel case statements.

Inferencereports

HDL Compiler (Presto Verilog) will indicate a N in the Bus column of theinference report if the flip-flop has different enable conditions. The original HDLCompiler indicates a Y (yes) in the Bus column if the flip-flop has differentenable conditions. An example is shown below.

reg [1:0] mem;

always @(posedge clk)

mem[addr] = data;


Topic Description





Under certain conditions, HDL Compiler (Presto Verilog) generateserrors when incorrect syntax is used; the original HDL Compiler toolgenerates no warnings or errors under the same conditions. SeeExample C-33 through C-35.

New SyntaxErrors

Under certain conditions, HDL Compiler (Presto Verilog) generates errorswhen incorrect syntax is used; the original HDL Compiler tool generates nowarnings or errors under the same conditions. See Examples C-33 throughC-35.

translate_offandtranslate_on

The //synopsys translate_off directive and the //synopsystranslate_on directive are changed. Beginning with the U-2003.06 release,the code contained within these directives is ignored and treated similar to the/* and the corresponding */ comment delimiters. In previous releases, HDLCompiler and Presto Verilog would parse, but not synthesize, the code withinthese directives; if you wanted the code totally ignored, you needed to set thevariable hdlin_translate_off_skip_text to true. In 2003.06, the variablehdlin_translate_off_skip_text is ignored because it’s function isincorporated into the translate_on/off directives. In addion, thetranslate_off and translate_on directives are deprecated directives. See“Deprecated Features” on page C-58.


Topic Description





Example C-33 Syntax Error Notificationmodule dif_case (sel, a, b, c, d, dout);

input a, b, c, d;input [1:0] sel;output dout;reg dout;always @ (sel or a or b or c or d)

begincase (sel)

2'b00: dout = a;2'b01: dout = b;2'b10: dout = c;2'b11: dout = d;

endcase; //Error: It is illegal to use a semicolon after endcase.end

endmodule

Example C-34 Syntax Error Notificationmodule dif_reg_in (clk, reset, a, b, y);

input clk, reset, a, b;output y;reg y;reg clk;//Error: it is illegal to code the clock as both input and register.

always @ (posedge clk or posedge reset)if ( reset ) begin

y <= 0;endelse begin

y <= a & b;end

endmodule

Example C-35 Syntax Error Notificationmodule dif_ditto (clk, reset, a, b, y);

input clk, reset, a, b;output y;reg y;always @ (posedge clk or posedge reset)

if ( reset ) beginy <= 0;; /*Error: HDL Compiler will not read the file and returns

parse error at or near token ‘;’ (VER-294). */endelse begin

y <= a & b;end





endmodule

Only labels and hierarchical labels are allowed to describe the opsfor a resource. If you want to put another resource in the definition,you need to write inline code for that resource to fit the new syntax.For example, the code in Example C-36 was accepted by the originalHDL Compiler tool but to be accepted by HDL Compiler (PrestoVerilog), the resource declarations changed must be changed asfollows: Remove the declaration for R1 and write inline code for R1in R2 as shown in Example C-37. Notice that L5/f1/L2 L5/f1/L3 L6/f1/L2 L6/f1/L3 has replaced L5/R1 L6/R1 in the R2 declaration.

Example C-36 Original HDL Compiler Code—Resource SharingWith Hierarchical Naming

module top (a, b, add, sub, inc, switch, z); input[3:0] a, b; input add, sub, inc, switch; output[3:0] z;

reg[3:0] z; always begin: b1 /* synopsys resource R2: ops = "L4 L5/f1/L1 L6/f1/L1 L5/f1/L2 L5/f1/L3 L6/f1/L2 L6/f1/L3"; */

if (add) z = a + b; // synopsys label L4 else if (switch) z = sub_inc_dec (a, b, sub, inc); // synopsys label L5 else z = sub_inc_dec (b, a, sub, inc); // synopsys label L6 end

function [3:0] sub_inc_dec; input [3:0] a, b; input sub, inc;

begin: f1 if (sub) sub_inc_dec = (a-b); //synopsys label L1 else if (inc)





sub_inc_dec = a + 1'b1; //synopsys label L2 else sub_inc_dec = a - 1'b1; // synopsys label L3 endendfunctionendmodule

Example C-37 HDL Compiler (Presto Verilog) Code—ResourceSharing With Hierarchical Naming

module TOP (A, B, ADD, SUB, INC, SWITCH, Z); input[3:0] A, B; input ADD, SUB, INC, SWITCH; output[3:0] Z;

reg[3:0] Z; always begin : b1

/* synopsys resource R2 :ops = ”L4 L5/f1/L1 L6/f1/L1 L5/R1 L6/R1”;

*/if(ADD)

Z = A+B; // synopsys label L4else if (SWITCH)

Z = sub_inc_dec (A, B, SUB, INC); // synopsys label L5else

Z = sub_inc_dec (B, A, SUB, INC); // synopsys label L6end

function [3:0] sub_inc_dec;input [3:0] A, B;input SUB, INC;/* synopsys resource R1 :

ops = ”f1/L2 f1/L3”;*/begin : f1

if (SUB)sub_inc_dec = (A-B);// synopsys label L1

else if (INC)sub_inc_dec = (A+1’b1); // synopsys label L2

elsesub_inc_dec = (A-1’b1); // synopsys label L3

end





endfunctionendmodule

Implementation Differences

Often a single HDL design source can result in several differentdesign implementations. In such cases, HDL Compiler (PrestoVerilog) and the original HDL Compiler produce different butfunctionally equal designs. In some cases, differences occurbecause HDL Compiler (Presto Verilog) adheres more closely to theIEEE Std. Many portions of the original HDL Compiler were writtenbefore this standard existed. When generated logic is differentbetween designs, HDL Compiler (Presto Verilog) typically providesswitches so users can control behavior with an option. For example,HDL Compiler (Presto Verilog) infers a MUX_OP for a variable arrayreference by default—See “Improved MUX_OP inference” onpage 53. However, if you do not want to infer a MUX_OP for avariable array reference and instead want the SELECT_OP, you canset hdlin_build_selectop_for_var_index to false, which isthe original HDL Compiler behavior.





Public Variables for HDL Compiler (Presto Verilog)

HDL Compiler (Presto Verilog) public variables are described inTable C-6.

Table C-6 New Public Variables

Name Default Description

hdlin_array_instance_naming_style "%s[%d]" Controls array instance naming

hdlin_auto_full_case true Performs automatic full-case detection

hdlin_auto_parallel_case_early true Performs automatic parallel-casedetection during IL passes

hdlin_auto_save_templates false Controls whether designs containingparameters are read in as templates.When set to true, the automatic netllistreader is disabled. See “Starting HDLCompiler” on page 1-4.

hdlin_black_box_pin_hdlc_style true For black box, uses HDLC pin naming(pin naming is affected by the inputsignal's type)

hdlin_branch_optimization true Attempts to optimize branchconditions

hdlin_build_selectop_for_var_index

false Specifies if SELECT_OPS should bebuilt for variable indexing on rhs

hdlin_call_stack_depth 1000 Sets maximum depth of call stack forfunctions and tasks

hdlin_check_no_latch false Controls whether a warning messageis issued if a latch is inferred from adesign.

hdlin_check_user_full_case true Warns if full_case is applied tonon-full case statements





hdlin_check_user_parallel_case

true Warns if parallel_case is applied tonon-parallel case statements

hdlin_compare_const_with_gates

true Prevents the use of syntheticoperators == and != for equalitycomparisons with constants

hdlin_compare_eq_with_gates false Prevents the use of syntheticoperators for any == and != operators

hdlin_decoder_max_input_width 31 Infers a decoder only when thenumber of inputs is less than this value

hdlin_decoder_min_input_width 5 Infers a decoder only when thenumber of inputs exceeds this value

hdlin_decoder_min_use_percentage 90 Sets the percentage of outputs thatmust be used in order to infer adecoder

hdlin_dyn_array_bounds_check false Checks an array index against arraybounds when the index is wider thanwhat is needed to index the array

hdlin_enable_presto true Runs the original HDL Compiler whenset to false

hdlin_escape_special_names false Prepends a backslash onto anyVerilog name with special characters

hdlin_infer_block_local_latches true Allows latches to be inferred forvariables local to Verilog namedblocks

hdlin_infer_comparators true Infers two- and six-output comparators(value numbering dependent)

hdlin_infer_decoders false Infers decoders(value numbering dependent)

hdlin_infer_enumerated_types false Infers enumerated types

Table C-6 New Public Variables (Continued)






hdlin_infer_fsm true Option enables and disables finitestate machine automatic detectionand inference. When set to false, FSMdetection is disabled.

hdlin_infer_function_local_latches

false Allows latches to be inferred forfunction- and task-scope variables

hdlin_keep_feedback false Preserves feedback to synch-data pinof SEQGEN.

hdlin_keep_signal_name default Keeps only those internal nets with thedont_munch pragma attached.

hdlin_keep_feedback_netname false When set to true, the automatic netllistreader is disabled. See “Starting HDLCompiler” on page 1-4.

hdlin_link_design false Links design

hdlin_loop_invariant_code_motion true Hoists loop-invariant code out of loops

hdlin_map_to_module true Processes map_to_module directivefor Verilog function

hdlin_map_to_operator true Processes map_to_operatordirective for functions and tasks.

hdlin_module_arch_name_splitting true Splits module names in Verilog intoentity/architecture portions by twosubsequent underscores.

hdlin_mux_oversize_ratio 100 Defined as the ratio of the number ofMUX inputs to the unique number ofdata inputs; when this ratio isexceeded, a MUX will not be inferredand the circuit will be generated withSELECT_OPs.

hdlin_mux_size_min 2 Sets the minimum number of datainputs for MUX inference







hdlin_netlist_transform true Does netlist trimming for syntheticoperators

hdlin_no_adder_feedthroughs true Prevents feedthrough optimizations onadders and subtractors.

hdlin_no_sequential_mapping false Prevents sequential mapping

hdlin_one_hot_one_cold_on true Optimizes according to one_hot andone_cold attributes

hdlin_optimize_array_references true Optimizes constant offsets in arrayreferences.

hdlin_optimize_case_default true Optimizes the default-branch controllogic for case statements.

hdlin_optimize_enum_types false Simplifies comparisons based onenumerated type information

hdlin_optimize_shift_expressions true Reduces the number of GTECH gatesrequired to implement variable shiftoperations.

hdlin_optimize_slice_op true For variable part-select ([+:], [-:]),generates simple logic (which doesnot give x's for out-of-bounds indices).

hdlin_preserve_sequential false Preserve cells that are inferred butoptimized away by HDL Compiler.

hdlin_print_modfiles false Informs user of reads and writes tomodule files

hdlin_prohibit_nontri_multiple_drivers

true Issues an error when a non-'tri' net isdriven by more than one processes orcontinuous assignment

hdlin_redundancy_elimination true Performs value numbering-basedredundancy elimination (SSAdependent)







hdlin_register_report_depth 3 Determines levels of logic to traversewhen generating sequential inferencereports

hdlin_report_enumerated_types true Reports inferred enumerated types

hdlin_report_fsm false Enables and disables the finite statemachine inference report. For details,see “FSM Inference Report” onpage 4-50

hdlin_report_mux_op true Prints summary of MUX_OPs

hdlin_report_syn_cell false Prints summary of synthetic cells

hdlin_report_tri_state true Prints report for inferred three-stateelements

hdlin_selector_simplify_effort 1 Selects effort used in simplifyingselectors with constant inputs

hdlin_seqmap_search_depth 3 Obsoleted in U-2003.06; replaced withhdlin_seqmap_async_search_depthvariable andhdlin_seqmap_sync_search_depth

The obsoleted variable,hdlin_seqmap_search_depth,controlled how many levels of logicPresto Verilog would traverse to find aset or reset of a sequential element.

hdlin_seqmap_async_search_depth Controls how many levels of logicPresto Verilog will traverse whenlooking for asynchronous sets orresets.

hdlin_seqmap_sync_search_depth Controls how many levels of logicPresto Verilog will traverse looking forsynchronous sets or resets.







hdlin_share_all_nodes false If true, shares arithmetic nodes even ifit may reduce the effectiveness ofresource sharing.

hdlin_share_all_operators false Share all operators that can beshared; share arithmetic nodes even ifit may reduce the effectiveness ofresource sharing. (that is, ignorehdlin_dont_share_nodetypes)

hdlin_subprogram_default_values false Reads tick-LEFT as default value forvariables instead of 0's

hdlin_translate_off_on true Heeds the translate_off andtranslate_on directives. Note thattranslate_off and translate_on aredeprecated directives. See“Deprecated Features” on page C-58.

hdlin_unsigned_integers false Allows you to obtain the original HDLCompiler behavior for signs when setto true. Note that if you use any signsin your code, the new HDL Compilerissues a warning and forceshdlin_unsigned_integers back to false

hdlin_upcase_names false Converts all Verilog names touppercase

hdlin_use_carry_in false Uses the carry-in input on adders

hdlin_use_syn_shifter false Generates DesignWare shift operators

hdlin_verbose_cell_naming false Puts verbose (descriptive) names oncells

hdlin_warn_implicit_wires true Warns about implicitly declared wires

hdlin_warn_sens_list true Warns on incomplete sensitivity list







hdlin_while_loop_iterations 1000 Sets the iteration limit forindeterminate for and while loops

vrlg_std 2001 Specifies the Verilog standard toenforce (1995 or 2001).






HDL Compiler (Presto Verilog) RM: C. Differences Between HDL …read.pudn.com/downloads181/ebook/845528/preug/preug_c.pdf · Table C-1 lists the Verilog 2001 features implemented

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