HCS12 Technical Training Module 14-NVM, Slide 1 MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product.
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• 256K bytes of Flash made of four 64K byte blocks• Single supply program and erase.• Automated program and erase algorithm.• Interrupt on command completion.• All four flash blocks can be programmed and erased in parallel.• Read-While-Write into different block.• Fast sector erase and word program operation.• Flexible protection scheme against accidental program or erase.• Security feature to prevent intrusive access.
• All four Flash Blocks Occupy 16 Bytes In The I/O Register Area.• Registers Are Divided Into Banked and Unbanked• Banked Registers Are Selected With BLKSEL1: BLKSEL0 In FCNFG• Unbanked Registers Control State Machine Clock, Security, Interrupts• Banked Registers Control Erasure, Programming, Protection• Banked Registers Allow Erasure and Programming All Four Blocks in Parallel
FDIVLD — Flash Clock Divider LoadedThis bit is set when the FCLKDIV register is written to. An attemptto program or erase the flash without having written to this registerpreviously will result in an access error and the command will not be executed.
1 = Register has been written to since the last reset.0 = Register has not been written to.
PRDIV8 — Enable Prescaler by 81 = Enables a prescaler by 8 before feeding into the FCLKDIV divider.0 = OSCCLK is directly fed into the FCLKDIV divider
FDIV[5:0] — Flash Clock DividerThe combination of FDIV8 and FDIV[5:0] is used to divide the oscillator clock down to a frequency of 150KHz - 200KHz. This resulting clock, FCLK, is used to drive the program and erase state machines for the flash. For frequencies of OSCCLK > 12.8MHz the Prescaler bit PRDIV8 must be set on.
This register is loaded from flash address $FF0F during thereset sequence, indicated by “F” in the reset row of the register description.KEYEN — Enable backdoor key to security1 = Backdoor to flash read via BDM or external bus interface is enabled0 = Backdoor to flash read via BDM or external bus interface is disabled.
When KEYEN is set, the user can then bypass the security by:1. Setting the KEYACC bit in the configuration (FCNFG) register.
2. Writing the correct four 16 bit words to the flash using the backdoor comparison keys addresses.
3. Clear the KEYACC bit.
4. If all four 16bit words match the flash content, the MCU is unsecured by forcing the bits SEC[1:0] to the unsecured state.
5. If any of the four 16bit words does not match the flash content the MCU remains secured and a security violation signal is sent to the CPU.
NV[6:2] = Non-Volatile FlagsThese Non-Volatile Flags are available to the user
This unbanked register enables the interrupts, gates the securitybackdoor writes and selects the register bank to be operated on.
CBEIE — Command Buffers Empty Interrupt EnableThis bit enables the interrupts in case of empty address, data and command buffers.1 = An interrupt will be requested whenever the CBEIF flag is set0 = Command Buffers Empty Interrupts disabled
CCIE — Command Complete Interrupt EnableThis bit enables the interrupts in case of all commands being completed.1 = An interrupt will be requested whenever the CCIF flag is set0 = Command Complete Interrupts disabled
KEYACC — Enable Security Key Writing1 = Writes to flash module are interpreted as keys to open the backdoor.0 = Flash writes are interpreted as the start of a program or erase sequence.
BKSEL[1:0]— Register bank selectThese two bits are used to select which of the four register banks areaddressed. The register bank associated with Flash 0 is the defaultout of reset.00 = Bank 001 = Bank 110 = Bank 211 = Bank 3
This register determines whether a whole block or subsections of a block are protected against accidental programor erase. Each flash block can have two protected areas, one starting from relative address $8000 (called lower) towards higher addresses and the other growing downwards from $FFFF (called higher).
FPOPEN — Opens the flash block or subsections of it for program or erase.1 = The flash block or subsections are enabled to program or erase.0 = The whole flash block is protected.
FPHDIS — Flash Protection Higher address range disableThis bit determines whether there is a protected area at the higher end of the flash block address map.1 = Protection disabled0 = Protection enabled
FPHS[1:0] — Flash Protection Higher address size.These bits determine the size of the protected area.
FPLDIS — Flash Protection Lower address range disableThis bit determines whether there is a protected area at the lower end of the flash block address map.1 = Protection disabled0 = Protection enabled
FPLS[1:0] — Flash Protection Lower Address sizeThese 2 bits determine the size of the protected area.
Note: “F” indicates that registers are loaded from Flash control area as follows:. $FF0D --> Block 0, $FF0C --> Block 1, $FF0B --> Block 2, $FF0A --> Block 3
*CBEIF — Command Buffers Empty Interrupt FlagIndicates that the address, data and command buffers are empty sothat a new command sequence can be started. The flag is cleared bywriting a “1”. By clearing the flag the command sequence is launched.Writing a “0” aborts a command sequence that has not yet beenlaunched and sets the ACCERR flag.1 = Buffers are ready to accept a new command.0 = Buffers are full.
*CCIF — Command Complete Interrupt FlagIndicates that there are no more commands pending. 1 = All commands are completed0 = Command in progress
*PVIOL — Protection violationIndicates an attempt was made to program or erase an address in aprotected memory area. A subsequent program or erase commandcannot be executed while this flag is set. The flag is also cleared by writing anew, valid command after CBEIF is cleared or when CCIF is clear.1 = A protection violation has occurred.0 = no failure
*BLANK — Blank Verify FlagIndicates that the flash block is fully erased in response to an Erase-Verify command. 1 = Flash block fully erased.0 = Flash block not fully erased.
1. Writing to the flash address space before initializing FCLKDIV.
2. Writing to the flash address space in the range $8000–$BFFF when PPAGE does not select a 16K block in the flash selected by BKSEL[1:0].
3. Writing to the flash address space $4000–$7FFF or $C000–$FFFF with BKSEL[1:0] not selecting Flash 0.
4. Writing a misaligned word or a byte to the flash address space.
5. Writing to the flash address space while CBEIF is not set.
6. Writing a second aligned word to the flash address space before executing a program or erase command on the previously written word.
7. Writing to any Flash register other than FCMD after writing an aligned word to the flash address space.
8. Writing a second command to the FCMD register before executing the previously written command.
9. Writing a MASS erase command to FCMD while any protection is enabled. See FPROT register description.
10. Writing a SECTOR erase command to FCMD while protection is enabled for that sector. See FPROT register description.
11. Writing to any Flash register other than FSTAT (to clear CBEIF) after writing to the command register.
12. The part enters STOP mode and a program or erase command is in progress. The command is aborted. The flag is cleared by writing a “1”.1 = Access error has occurred.0 = Command sequence or command execution successfully completed.
ERASE — Erase flashErases a flash sector (512 bytes) or the whole flash depending on the MASS bit. Trying to erase a sector located in a protected area will result in a protection violation indicated by the PVIOL bit in the FSTAT register being set.1 = Perform a sector erase if MASS=0 or a mass erase if MASS=1.
PROG — Word programmingTrying to program a word located in a protected area will result in a protection error indicated by PVIOL set.
ERVER - Enable Erase VerifyVerifies the flash block is fully erased. A successful verification will set the BLANK bit in the FSTAT register. 1 = Perform an erase verify after mass erase.
MASS - Enables Mass ErasePerform a mass erase of the selected 64K byte block. This bit worksin conjunction with the ERASE bit. If any protection is active on theselected block, mass erase has no effect and the PVIOL bit in theFSTAT register is set. Write at anytime.1 = Perform a mass erase of the whole block.0 = Perform sector erase.
EDIVLD — Flash Clock Divider LoadedThis bit is set when the ECLKDIV register is written to. An attempt to program or erase the EEPROM without having written to this register previously will result in an access error and the command will not be executed.
PRDIV8 — Enable Prescaler by 8A pre-prescaler! Set this bit if oscillator frequency is >12.8MHz.
EDIV[5:0] — Flash Clock DividerThe combination of PRDIV8 and EDIV[5:0] is used to divide the oscillator clock down to a frequency of 150KHz - 200KHz. This resulting clock, EECLK, is used to drive the program and erase state machines for the EEPROM.Follow the flow chart in the specification to calculate the correct value for each application.
FOR CORRECT PROGRAM AND ERASE OPERATION EECLK MUST BE WITHIN SPEC REGARDLESS OF THE SYSTEM FREQUENCY.
EDIVLD — Flash Clock Divider LoadedThis bit is set when the ECLKDIV register is written to. An attempt to program or erase the EEPROM without having written to this register previously will result in an access error and the command will not be executed.
PRDIV8 — Enable Prescaler by 8A pre-prescaler! Set this bit if oscillator frequency is >12.8MHz.
EDIV[5:0] — Flash Clock DividerThe combination of PRDIV8 and EDIV[5:0] is used to divide the oscillator clock down to a frequency of 150KHz - 200KHz. This resulting clock, EECLK, is used to drive the program and erase state machines for the EEPROM.Follow the flow chart in the specification to calculate the correct value for each application.
FOR CORRECT PROGRAM AND ERASE OPERATION EECLK MUST BE WITHIN SPEC REGARDLESS OF THE SYSTEM FREQUENCY.
** NOTE: locations must only be programmed once following each erase.
The operation executed by the EEPROM state machine is determined by the value written to the Command Buffer Register (ECMD)
CommandValue
Operation Comments
$20Word
ProgramProgram a word. **(2 bytes, word aligned)
$40SectorErase
Erase an EEPROM sector.(4 bytes, double word aligned)
$41MassErase
Erase the whole EEPROM. (Only possible when EPDIS and EOPEN bits are set)
$05EraseVerify
Verify the EEPROM block is fully erased. A successful verification will set the BLANK bit in the ESTAT register.
$60SectorModify
Erase the EEPROM sector containing the word and then program one word with the new data.By launching a sector modify command and then pipelining a Program command it’s possible to completely update a Sector.
other illegal Any other value will generate an Access Error.
CBEIE - Command Buffers Empty Interrupt EnableThis bit enables the interrupts in case of an empty address, data andcommand buffers.1 = An interrupt will be requested whenever the CBEIF flag is set0 = Command Buffers Empty Interrupts disabled
CCIE - Command Complete Interrupt EnableThis bit enables the interrupts in case of all commands beingcompleted.1 = An interrupt will be requested whenever the CCIF flag is set0 = Command Complete Interrupts disabled
EPOPEN — Opens the EEPROM block or a subsection of it for program or erase.1 = The EEPROM block or subsections are enabled to program or erase.0 = The whole EEPROM block is protected. In this case the other bits within the protect register are don’t care.
EPDIS — EEPROM Protection disableThis bit determines whether there is a protected area at the higher endof the EEPROM block address map.1 = Protection disabled0 = Protection enabled EEPROM Protection address size
ERASE — Erase EEPROMErases a EEPROM sector (4 bytes) or the whole EEPROM depending on the MASS bit. Trying to erase a sector located in a protected area will result in a protection violation indicated by the PVIOL bit in the FSTAT register being set.1 = Perform a sector erase if MASS=0 or a mass erase if MASS=1.
PROG — Word programmingTrying to program a word located in a protected area will result in a protection error indicated by PVIOL set.
ERVER - Enable Erase VerifyVerifies the EEPROM block is fully erased. A successful verification will set the BLANK bit in the FSTAT register.1 = Perform an erase verify after mass erase.
MASS - Enables Mass ErasePerform a mass erase of the selected 64K byte block. This bit worksin conjunction with the ERASE bit. If any protection is active on theselected block, mass erase has no effect and the PVIOL bit in theFSTAT register is set. Write at anytime.1 = Perform a mass erase of the whole block.0 = Perform sector erase.
*CBEIF — Command Buffers Empty Interrupt FlagIndicates that the address, data and command buffers are empty sothat a new command sequence can be started. The flag is cleared bywriting a “1”. By clearing the flag the command sequence is launched.Writing a “0” aborts a command sequence that has not yet beenlaunched and sets the ACCERR flag.1 = Buffers are ready to accept a new command.0 = Buffers are full.
*CCIF — Command Complete Interrupt FlagIndicates that there are no more commands pending. 1 = All commands are completed0 = Command in progress
*PVIOL — Protection violationIndicates an attempt was made to program or erase an address in aprotected memory area. A subsequent program or erase commandcannot be executed while this flag is set. The flag is also cleared by writing anew, valid command after CBEIF is cleared or when CCIF is clear.1 = A protection violation has occurred.0 = no failure
*BLANK — Blank Verify FlagIndicates that the EEPROM block is fully erased in response to an Erase-Verify command. 1 = EEPROM block fully erased.0 = EEPROM block not fully erased.
1. Writing to the EEPROM address space before initializing ECLKDIV.
2. Writing a misaligned word or a byte to the EEPROM address space.
3. Writing to the EEPROM address space while CBEIF is not set.
4. Writing a second aligned word to the EEPROM address space before executing a program or erase command on the previously written word.
5. Writing to any EEPROM register other than ECMD after writing an aligned word to the EEPROM address space.
6. Writing a second command to the ECMD register before executing the previously written command.
7. Writing a MASS erase command to ECMD while any protection is enabled. See EPROT register description.
8. Writing a sector erase command to ECMD while protection is enabled for that sector. See EPROT register description.
9. Writing to any EEPROM register other than ESTAT (to clear CBEIF) after writing to the command register.
BLANK — Blank Verify FlagIndicates that the EEPROM block is fully erased in response to an Erase- Verify command. The flag is cleared by writing a “1”. 1 = EEPROM block fully erased.0 = EEPROM block not fully erased.