8/14/2019 HC20.26.620.Micro-Architecture of Godson-3 Multi-Core Processor http://slidepdf.com/reader/full/hc2026620micro-architecture-of-godson-3-multi-core-processor 1/35 1 Micro-architecture of Godson-3 Multi-Core Processor Weiwu Hu, Jian Wang, Xiang Gao, and Yunji Chen Institute of Computing Technology Chinese Academy of Sciences [email protected]
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HC20.26.620.Micro-Architecture of Godson-3 Multi-Core Processor
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8/14/2019 HC20.26.620.Micro-Architecture of Godson-3 Multi-Core Processor
A brief introduction to Godson processors The architecture of Godson-3 multi-core processor Physical implementation Preliminary performance evaluation PetaFLOPS and TeraFLOPS
Godson is the academic name of Loongson TM
8/14/2019 HC20.26.620.Micro-Architecture of Godson-3 Multi-Core Processor
A brief introduction to Godson processors The architecture of Godson-3 multi-core processor Physical implementation Preliminary performance evaluation PetaFLOPS and TeraFLOPS
8/14/2019 HC20.26.620.Micro-Architecture of Godson-3 Multi-Core Processor
Crossbar + Mesh Single crossbar connects cores, L2s, and four directions
Directory-based cache coherence protocol Distributed L2 caches are global addressed Each cache block has a directory entry Both data cache and instruction cache are recorded in directory
8x8 Xbar
P0 P1 P2 P3
L2 L2 L2 L2
E S
W
N
E S W
N
8/14/2019 HC20.26.620.Micro-Architecture of Godson-3 Multi-Core Processor
GS464 general purpose core MIPS64, 200+ more instructions for X86
binary translation and media acceleration Four-issue superscalar OOO pipeline Two fix, two FP, one memory units Two FP units each supports full pipelined
double/paired-single MAC operation 48-bit VA and PA, 128-bit memory access 64KB icache and 64KB dcache, 4-way 64-entry fully associated TLB, 16-entry
Define new instructions X86 ISA function and MIPS ISA format Binary translation mechanism supporting >200 instructions are defined with 5% additional silicon cost
Speedup X86-to-MIPS binary translation by 10 times
MS windows Linux apps. on X86
Linux apps. on MIPS System level X86 VM Process level X86 VM
Linux on MIPS
Enhanced MIPS decode
Enhanced Godson internal operations
Figure 2. The architecture of Godson-2 virtual machine
8/14/2019 HC20.26.620.Micro-Architecture of Godson-3 Multi-Core Processor
A brief introduction to Godson processors The architecture of Godson-3 multi-core processor Physical implementation Preliminary performance evaluation PetaFLOPS and TeraFLOPS
8/14/2019 HC20.26.620.Micro-Architecture of Godson-3 Multi-Core Processor
Cell-based high performance physical design The Full Hierarchical Design Methodology Manual placement & route for critical paths Manual placement of all FFs and clock buffers,manual clock gating Architecture optimization with physical feedback
8/14/2019 HC20.26.620.Micro-Architecture of Godson-3 Multi-Core Processor
A brief introduction to Godson processors The architecture of Godson-3 multi-core processor Physical implementation Preliminary performance evaluation PetaFLOPS and TeraFLOPS
8/14/2019 HC20.26.620.Micro-Architecture of Godson-3 Multi-Core Processor
A brief introduction to Godson processors The architecture of Godson-3 multi-core processor Physical implementation Preliminary performance evaluation PetaFLOPS and TeraFLOPS
8/14/2019 HC20.26.620.Micro-Architecture of Godson-3 Multi-Core Processor
The architecture of Godson-2 superscalar architecture isavailable at: Weiwu Hu, Fuxin Zhang, Zusong Li, “Microarchitecture of the Godson-2
Processor”, Journal of Computer Science and Technology , 20(2):243-249,Mar. 2005
Weiwu Hu, Jiye Zhao, Shiqiang Zhong, Xu Yang, Elio Guidetti, Chris Wu,“Implementing a 1GHz Four-issue Out-of-Order Execution Microprocessorin a Standard Cell ASIC Methodology”, Journal of Computer Science and Technology , 22(1):1-14, Jan. 2007
The experiences learning from Godson processor design isavailable at:
Weiwu Hu, Jian Wang, “Making Effective Decisions in ComputerArchitects’ Real-World: Lessons and Experiences with Godson-2 ProcessorDesigns”, Journal of Computer Science and Technology , 23(4), July 2008
The architecture of Godson-3 multi-core is available at: HotChip’08
8/14/2019 HC20.26.620.Micro-Architecture of Godson-3 Multi-Core Processor