Hardware & Operating System Overview Ch.1 and Ch.2

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Hardware & Operating System

Overview

Ch.1 and Ch.2

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About Your Book

• Published in 1979• Mainframe Assembler Language• What is Assembler Language?• No JCL• Using a mainframe emulator in

class

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Why Learn Assembler?

• Directly manipulate hardware– Device Driver programs– Processor-specific instructions, such as for sound cards or

printers• Unusual performance issues

– Real-time applications, such as flight simulators or patient monitoring devices

– Game programming• Disassembling (reverse engineering?)• Learn the hardware – really well!

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Class Organization/Outline

1. Intro to IBM Mainframe Hardware2. Intro to the Operating System3. Program Development & Documentation4. Defining Data/Instruction Formats5. Defining Character Data6. Packed Decimal Arithmetic7. Binary Arithmetic8. Subroutine Linkages

Continued on the next slide

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Class Organization - continuedClass Outline (Week-to-Week)

9. Program Debugging Strategies

10. Processing I/O and File Organization

11. Dummy Sections

12. Subroutines & Parameter Passing

13. Creating & Manipulating Tables & Arrays

14. Sorting Strategies

15. Bit Manipulation

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IBM Mainframe Computers

IBM S/390 – G6

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Mainframe - defined

• A large powerful computer, often serving many connected terminals and most often used by large complex organizations.

• A state-of-the-art computer for mission critical tasks. In the "ancient" mid-1960s, all computers were mainframes, since the term referred to the main CPU cabinet. Today, it refers to a class of ultra-reliable medium and large-scale servers designed for enterprise-class and carrier-class operations.

• The first mainframe vendors were Burroughs, Control Data, GE, Honeywell, IBM, NCR, RCA and Univac, otherwise known as "IBM and the Seven Dwarfs."

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Memory

Processor

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Memory

• Electronic/High-Speed• Holds programs and data• Programs included:

– Operating system– Application programs

• Volatile• Relatively expensive• Size: MB, GB, and more

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Early Memory

Visual shows 12-bits of memory – core storage – each ring or donut in the visual represents a single bit of memory. The wires running through the “core” of each donut can change the direction of the power thereby flipping the bit back and forth to represent either “bit on” or “bit off.”

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Processor

• Manipulate data• Execute program instructions

– 4-steps per instruction• Fetch• Decode• Execute• Store

– 3 different instruction lengths• 2 bytes, 4-bytes, 6-bytes

• Interrupts – 6 types• Supervisor call, I/O, External, Machine

Check, Program Check, Restart

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4-steps or Phases of Execution per Instruction

1. Fetch the instruction – Obtain next instruction from memory into the processor

2. Decode – 2, 4, or 6-byte instruction length plus update IC in PSW to point at next instruction

3. Execute – carry out the instruction

4. Store – place result of instruction in its designated field

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Instruction Lengths

op code R1 R2

op code R1 M2

op code M1 M2

Many instructions have each instruction length – for example, there are at least 3 ADD instructions. They all work the same way. The second operand (R2 or M2) is added to the first operand (R1 or M1) and the result is stored in the first operand location. The R operand is a General Purpose Register and the M operand represents a location in memory.

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Programs in Execution

Hold

Ready

Running

Done

Waiting

Initially, programs enter the system by being queued on the HOLD queue. After all needed resources are assigned to the program, it can re-queue on the READY queue. From there, it can move to the RUNNING queue while it is assigned a processor and the program will probably move often between the READY, RUNNING, and WAIT queues as it goes through its execution. Finally, when the program completes, it will move to the DONE queue where the operating system will un-assign the assigned resources

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Interrupts

EXTERNAL NEW PSW

SVC NEW PSW

PROGRAM NEW PSW

MACHINE CHECK NEW PSW

I/O NEW PSW

RESTART NEW PSW

EXTERNAL OLD PSW

SVC OLD PSW

PROGRAM OLD PSW

MACHINE CHECK OLD PSW

I/O OLD PSW

RESTART OLD PSW

CURRENT PSW

12

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At any point in time, there could be a large number of programs sitting in the READY queue waiting to get access to a processor when it becomes available. These programs cannot re-queue anywhere unless directed by the operating system as the result of an interrupt occurring.

Let’s say that your program is currently running, so it is on the RUNNING queue, then your program wants to read a record from an input file. When it request the input (from the operating system), an interrupt occurs (Supervisor Call). As a result of any interrupt type, the CURRENT PSW is saved in the appropriate OLD PSW location and the appropriate NEW PSW content becomes the CURRENT PSW. So the next instruction to be executed comes from the program pointed to by the appropriate NEW PSW, which just happens to be the o/s program to service that type of interrupt (Supervisor Call).

After the reason for this interrupt is determined and the appropriate action has been taken, processor control is given to another o/s routine, called the Dispatcher, to determine which program to move from the READY to the RUNNING queue. When it is the turn of the program that wanted to read that input record eventually gets processor control back, its PSW has been preserved, so it can be restored and now the program can return to the exact point where it left off when the interrupt originally occurred.

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Program Status Word

Instruction Address

I/O Mask

External Mask

Machine Check Mask

Wait State

Cond. Code

Addressing Mode

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In the PSW (previous slide), the mask fields are used in effect to disable some of the interrupts from occurring. This doesn’t really disable the interrupt since interrupts are unpredictable, but to indicate to the operating system to ignore (for now) the interrupt if it does occur. You would not want a machine check failure to occur while you were in the midst of handling a machine check that has just occurred. There are other ways to disable interrupts. For example, if you don’t want a Supervisor Call interrupt to occur, don’t attempt to execute an instruction that forces a Supervisor Call, such as request I/O.

The condition code field is where the condition code is kept for instructions that set the condition code, such as a COMPARE instruction to indicate the result of the compare the condition code can be tested by subsequent instructions, as a Branch-On-Condition instruction.

The instruction address field is where the next sequential instruction (to be executed) is remembered so it can be located when the current instruction completes, the next instruction can be fetched. Addressing mode establishes whether memory is restricted to the first 16MB (24-bit addressing) or up to 2GB (31-bit addressing) can be addressed.

Finally, the Wait State bit indicates that there is nothing on the READY queue to dispatch.

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Program Interrupts & Queues

Hold

Ready Running

Done

Waiting

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I/O Devices

• Input into memory• Output from memory• Some devices are input only, some devices are output only, but

some devices are both input and output

• Be sure to read: Characteristics of direct storage access devices – bottom of page 9 through the end of page 14 : (Input/Output Equipment)

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Major Features of Main Frame Operating Systems

• Support thousands of interactive users• Self-healing ?• Virtual memory• Data Security• Managing many devices and files• Managing work

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Single-User/Single-Tasking System

In early memory only one program at a time could be executed. In the bottom (beginning at 0K – in the Resident Area of Memory) lived the operating system and most of upper memory, operating system programs were moved in and out (Transient Program Area) based on demand. In between, lived the application program to be executed, up to its maximum size allowed, which was the difference between to top of the Resident Area and the bottom of the Transient Area. Free Spaces was what was left that the program did not use.

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Fixed PartitionsIn the next system, called Multi-Programming with a Fixed Number of Tasks (MFT). But some things remained the same – namely the top and bottom of memory was still essentially the operating system and whatever amount of memory was left over could be occupied by up to 52 programs, which included programs such as what we call “print drivers” today.Multiple programs could each run in a separate partition. Between these partitions are fixed walls so partitions were all the same size, but customizable at Boot Time.

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Variable (Dynamic) Partitions

• Fixed Ptns seemed to cause as many problems as it solved, such as:– Keep free memory in contiguous blocks so its use could be

maximized

• How about a different approach?– Section the program into smaller pieces so it might fit into

fragments of memory

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O/S

Job1 (10K)

10K

20K

Job2 (15K)

35K

Job3 (20K)

55K

Job4 (50K)

105K

• Job1 = 10K• Job2 = 15K• Job3 = 20K• Job4 = 50K

Multi-Programming with a Variable Number of Tasks:Initially each program entering memory will load provided there is sufficient memory. The walls can now move around.In this example, the operating system lives solely in the bottom of memory (but it also still lives at the top – just not shown anymore.Where one program ends, the next one begins. Let’s see what happens as we go through a few programs ending and a few new programs beginning.Continue to the next slide

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O/S

10K

20K

Job2 (15K)

35K

Job3 (20K)

55K

105K

When jobs complete, memory becomes available

But… memory is now fragmented

At this point in time, program (job) JOB1 and JOB4 have completed from the previous slide. Job1 was 10K and Job4 was 50K, but these programs were not in contiguous, so there is now 60K of free memory and all of it is reusable, but only in 50K (or less) and 10K (or less) chunks. The 50K free area could be further cut into smaller pieces.

Let’s see what happens when another program comes along.Continue to the next slide

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O/S

10K

20K

Job2 (15K)

35K

Job3 (20K)

55K

105K

Job5 (5K)15K

Job6 (30K)

So here comes Job5 that wants 5K of memory. And here comes Job6 that wants 30K of memory. There is still some available memory, but it is still non-contiguous. In this example, it wouldn’t matter which algorithm was used to get these programs into memory. First Fit would place Job5 into the first available area from the bottom. That’s where Job 5 is located here. The same algorithm would place Job6 where it is now.

Best Fit algorithm would place the two jobs in the same areas of memory. Best fit looks at all the available areas and chooses the area that is the same size as the job or the next size smaller.

Continue to the next slide

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O/S

10K

20K

Job2 (15K)

35K

55K

105K

Job5 (5K)15K

Job6 (30K)

Now Job3 has finished leaving the free space between Jobs 2 & 6 (20K). The jobs that are still executing cannot be relocated to make the free space a large contiguous free area, so we now have 3 free areas for a total of 45K, yet the largest area still free is 20K – two 20K areas are available.

Continue to the next slide

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O/S

10K

20K

Job2 (15K)

35K

55K

105K

Job5 (5K)15K

Job6 (30K)

45K

Job7 (10K)

Jobs 7 & 8 arrive, but is there sufficient memory available? Job7 needs 10K of memory and Job 8 needs 30K. There is 35K memory available, but the space is not contiguous, so there is not sufficient space for Job 8 at this time. Job8 must wait until 35K of contiguous space becomes available. This style of memory management is better than what preceded it, but it still is not as efficient as it could be managed.

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NON-RESIDENT O/S&

SHARED MEMORY

EACHUSER

SECTION

RESIDENT O/S

EACHUSER

SECTION

EACHUSER

SECTION

In more recent versions of operating systems, memory management has taken on a newer look altogether. Partitions and regions have become address spaces. … fuscia, aqua, and yellow. Green is still the operating system.Implications are that each program has all of memory between the parts of the operating system – sounds like our original system. When a program is dispatched its address space is shifted so that it lines up with the operating system – for example, the aqua address space would be aligned with the green o/s and fuscia would no longer be aligned. If there is no addressability with all address spaces but one, this is the ultimate security of memory.This is handled by way of virtual memory which is large enough to hold an unlimited number of programs ready to run.

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Be sure to read Ch.2 in your textbook

After reading Ch.1

PLUS, there is also a “lecture” available in e-College

on this material which may be more useful to those preferring to read text rather than look at diagrams and pictures

End of Slide Set for Ch.1 and Ch.2