Hardware Architectures of Control Algorithms for Cyber ...

UNIVERSITY OF SOUTHAMPTON

FACULTY OF ENGINEERING AND PHYSICAL SCIENCES

School of Electronics and Computer Science

Hardware Architectures of Control Algorithms for Cyber-physical

Systems Model Identification

by

Charan Kumar Vala

Thesis for the degree of Doctor of Philosophy

June 2021

mailto:[email protected]

UNIVERSITY OF SOUTHAMPTON

ABSTRACT

FACULTY OF ENGINEERING AND PHYSICAL SCIENCES

School of Electronics and Computer Science

Doctor of Philosophy

HARDWARE ARCHITECTURES OF CONTROL ALGORITHMS FOR

CYBER-PHYSICAL SYSTEMS MODEL IDENTIFICATION

by Charan Kumar Vala

Applications of multiple model adaptive estimation (MMAE) based controllers are emerg-

ing in Cyber-physical systems (CPS). Such control algorithms are computationally in-

tensive as they involve recursive estimation of signals and this thesis investigates the

hardware architectures of MMAE algorithm for resource-constrained embedded com-

puting platforms.

This thesis presents three original contributions. The first contribution presents a novel

hardware architecture for the MMAE based linear time-invariant system model iden-

tification. A key feature of the architecture is area efficient which is achieved through

the reuse of multipliers and fixed computations in the MMAE filter bank. The pro-

posed architecture is implemented on FPGA and validated for auto-mobile application.

It is shown that the proposed architecture has achieved 39% LUT%, 13% FF%, 27%

DSP%, and 43% power reduction when compared with directly mapped hardware archi-

tecture. The second contribution presents a novel hardware architecture for the linear

time-variant (LTV) system model identification, based on the MMAE algorithm. To

investigate the area and timing trade-offs, an eight and four multiplier based Kalman

filter bank in LTV model identification architecture considered. The architecture has

been validated on FPGA for the DC-DC boost converter application with load resis-

tance as an uncertain parameter. From the experimental results, it has been shown that

the proposed four multipliers based architecture is area-efficient and 17% LUTs, 14%

FFs, 50% DSPs resource and 32% power consumption reduction when compared with an

eight multiplier version design with an increase of 50% clock cycles for execution. Fur-

thermore, resource utilization analysis is presented for the higher number (1 to 1024) of

filter banks. The final contribution addresses the applicability of the MMAE closed-loop

control algorithm for power electronic application, it is shown that the algorithm has

significantly improved the closed-loop output voltage response time and settling time

when compared with the PID controller and it is demonstrated by the simulation results

by changing the load resistance of boost converter abruptly.


Declaration of Authorship

I, Charan Kumar Vala , declare that the thesis entitled Hardware Architectures of Control

Algorithms for Cyber-physical Systems Model Identification and the work presented in

the thesis are both my own, and have been generated by me as the result of my own

original research. I confirm that:

• this work was done wholly or mainly while in candidature for a research degree at

this University;

• where any part of this thesis has previously been submitted for a degree or any

other qualification at this University or any other institution, this has been clearly

stated;

• where I have consulted the published work of others, this is always clearly at-

tributed;

• where I have quoted from the work of others, the source is always given. With the

exception of such quotations, this thesis is entirely my own work;

• I have acknowledged all main sources of help;

• where the thesis is based on work done by myself jointly with others, I have made

clear exactly what was done by others and what I have contributed myself;

• none of this work has been published before submission

Signed:.......................................................................................................................

Date:..........................................................................................................................

v


Contents

Declaration of Authorship v

Acknowledgements xix

Abbreviations xxi

Nomenclature xxiii

1 Introduction 1

1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Application selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.3 Research Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.4 Research Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.5 Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.6 Thesis Organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2 Adaptive Control in Cyber Physical Systems and Computing Plat-forms 9

2.1 Control Systems Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1.1 Preliminaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1.2 Norms on Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2 Introduction to Adaptive control . . . . . . . . . . . . . . . . . . . . . . . 11

2.3 Classical Adaptive Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.4 Multiple Model Adaptive Control . . . . . . . . . . . . . . . . . . . . . . 15

2.4.1 Historical Development of MMAC . . . . . . . . . . . . . . . . . . 15

2.4.2 Multiple Model Switched Adaptive Control . . . . . . . . . . . . . 16

2.4.3 Features of MMAC Algorithms . . . . . . . . . . . . . . . . . . . . 18

2.5 EMMSAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.5.1 Disturbance Estimation . . . . . . . . . . . . . . . . . . . . . . . . 20

2.5.1.1 Disturbance Estimation using Kalman filter . . . . . . . . 22

2.5.2 Switching Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.5.3 Uncertainty and physical system model set selection . . . . . . . . 25

2.6 Applications of MMAE/MMAC . . . . . . . . . . . . . . . . . . . . . . . . 26

2.7 Boost Converter Accurate Mathematical Model . . . . . . . . . . . . . . 28

2.7.1 Boost converter operating modes . . . . . . . . . . . . . . . . . . . 29

2.7.1.1 Continuous conduction mode (CCM) . . . . . . . . . . . 30

2.7.1.2 Discontinuous conduction mode (DCM) . . . . . . . . . . 30

2.8 Computing Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

vii

viii CONTENTS

2.8.1 General purpose Central Processing Unit . . . . . . . . . . . . . . 31

2.8.2 Microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.8.3 Digital signal processors . . . . . . . . . . . . . . . . . . . . . . . . 32

2.8.4 Graphics processing units . . . . . . . . . . . . . . . . . . . . . . . 34

2.8.5 Field-programmable gate arrays . . . . . . . . . . . . . . . . . . . 34

2.9 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3 Hardware Architecture for Linear Time Invariant System Model Iden-tification 39

3.1 Proposed Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.1.1 Cyber-Component . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.1.2 Multiplications reduction in Algorithm− 1 . . . . . . . . . . . . . 42

3.1.3 Deterministic Kalman Filter (DKF) . . . . . . . . . . . . . . . . . 47

3.2 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.2.1 Physical system data generation . . . . . . . . . . . . . . . . . . . 50

3.2.2 Matlab implementation . . . . . . . . . . . . . . . . . . . . . . . . 50

3.2.3 FPGA implementation . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.2.4 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.2.4.1 Original physical system vs proposed architecture . . . . 53

3.2.5 Hardware Resource Utilization . . . . . . . . . . . . . . . . . . . . 54

3.2.5.1 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.2.5.2 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.3 Resource utilization analysis . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.4 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4 Linear Time Variant System Model Identification Architecture 61

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

4.2 LTV model identification algorithm . . . . . . . . . . . . . . . . . . . . . . 62

4.3 Proposed architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

4.3.1 Control block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

4.3.2 Residuals computation unit . . . . . . . . . . . . . . . . . . . . . . 70

4.3.3 Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

4.4 Boost Converter Application and Model . . . . . . . . . . . . . . . . . . . 72

4.5 Results and discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4.5.1 Experimental set-up . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4.5.1.1 Case study-1 . . . . . . . . . . . . . . . . . . . . . . . . . 76

4.5.1.2 Case study-2 . . . . . . . . . . . . . . . . . . . . . . . . . 78

4.5.1.3 Case study-3 . . . . . . . . . . . . . . . . . . . . . . . . . 78

4.5.2 Residuals window size impact on model identification time . . . . 78

4.5.3 Performance analysis in-terms estimation . . . . . . . . . . . . . . 79

4.5.4 Model identification performance . . . . . . . . . . . . . . . . . . . 81

4.5.5 Performance analysis in-terms of area, speed and power . . . . . . 82

4.5.6 Resource utilization analysis . . . . . . . . . . . . . . . . . . . . . 83

4.5.7 Power consumption analysis . . . . . . . . . . . . . . . . . . . . . . 85

4.6 Resource utilization for higher number of models . . . . . . . . . . . . . . 86

4.7 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

CONTENTS ix

5 Multiple Model Adaptive Estimation Based Control with an applica-tion of DC−DC Boost Converter 91

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

5.2 EMMSAC for DC-DC boost converter . . . . . . . . . . . . . . . . . . . . 93

5.2.1 Physical system model set generation . . . . . . . . . . . . . . . . 94

5.2.2 Control Problem for DC-DC boost converter . . . . . . . . . . . . 94

5.2.3 Controller Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

5.2.4 Closed loop operation using EMMSAC . . . . . . . . . . . . . . . 97

5.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

5.3.1 Performance during abrupt load change . . . . . . . . . . . . . . . 98

5.3.1.1 Benchmark-A . . . . . . . . . . . . . . . . . . . . . . . . 98

5.3.1.2 Residuals window selection . . . . . . . . . . . . . . . . . 101

5.3.1.3 Benchmark-B . . . . . . . . . . . . . . . . . . . . . . . . . 102

5.3.2 Wrong controller effect on model identification . . . . . . . . . . . 105

5.4 Two model based real time model identification . . . . . . . . . . . . . . 106

5.4.1 ADC implementation on VCU118 FPGA using AD7476A . . . . . 106

5.4.2 DAC implementation on VCU118 FPGA using AD7303 . . . . . . 108

5.4.3 Moving Average Filter . . . . . . . . . . . . . . . . . . . . . . . . . 110

5.4.4 PWM signal generator . . . . . . . . . . . . . . . . . . . . . . . . . 110

5.4.5 Obtained results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

5.5 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

6 Conclusion and Future Directions 117

6.1 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

6.1.1 Closed loop hardware implementation of EMMSAC . . . . . . . . 119

6.1.2 An investigation to MMAE reconfigurable architecture with par-ticular focus on exploring trade-offs between the architecture useof resources area and time . . . . . . . . . . . . . . . . . . . . . . 119

6.1.3 EMMSAC based controller for Buck converter . . . . . . . . . . . . 121

A FPGA implementation SDC file 123

B Boost converter circuit parameter comparison 125

References 129

References 129

List of Figures

1.1 General structure of cyber-physical system (Source [1]) . . . . . . . . . . . 1

1.2 Envisaged Cyber-physical system with estimation based multiple modeladaptive control, where (u2, y2)T are the measured signals, (u0, y0)T arethe external disturbances and (u1, y1)T are the original signals at the inputand output of a physical system (Pp∗) respectively . . . . . . . . . . . . . 2

2.1 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2 General control system with feedback . . . . . . . . . . . . . . . . . . . . 13

2.3 Switched control system with feedback (Source [2]) . . . . . . . . . . . . . 16

2.4 Observer-based control system (Source [2]) . . . . . . . . . . . . . . . . . 17

2.5 EMMSAC block diagram (Source [2]) . . . . . . . . . . . . . . . . . . . . 20

2.6 Uncertainty (U) and an example sampling that produces ∆s (Source [2]) . 25

2.7 Accurate model of boost converter . . . . . . . . . . . . . . . . . . . . . . 28

2.8 Boost converter circuit in switch is closed mode . . . . . . . . . . . . . . 29

2.9 Boost converter circuit in switch is open mode . . . . . . . . . . . . . . . 29

2.10 Boost converter inductor current with respect to the PWM . . . . . . . . 30

2.11 FPGA fabric structure (Source [3]) . . . . . . . . . . . . . . . . . . . . . . 35

2.12 FPGA configurable logic block structure (Source [3]) . . . . . . . . . . . . 35

2.13 Execution of function y = (a&b)||!c on CLB (Source [3]) . . . . . . . . . . 35

3.1 Proposed architecture for MMAE based LTI model identification. Eachmodel represents the deterministic Kalman filter with a particular statespace matrices. Here (u2, y2)T are the measured signals, (u0, y0)T are theexternal disturbances and (u1, y1)T are the original signals at the input andoutput signals of a physical system (Pp∗) respectively. The cyber compo-nent design also corresponds to the MMAE part in Figure 1.2 shown inchapter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3.2 Auto-mobile vehicle with uncertainties De . . . . . . . . . . . . . . . . . 42

3.3 Error rate comparison for various scaling factors . . . . . . . . . . . . . . 45

3.4 Multiplications reduction using the proposed hardware architecture: com-parison for 1 to 64 models (Note: Number of multipliers used in theproposed architecture are even less than the number of multiplicationsrequired) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.5 (a) Proposed multiple model estimation based model identification archi-tecture: deterministic Kalman filter architecture, (b) residuals, argmin,comparator and model selection . . . . . . . . . . . . . . . . . . . . . . . 46

xi

xii LIST OF FIGURES

3.6 Deterministic Kalman filter detailed architecture for computing Xpestimate

and Σpestimate recursively, in parallel n similar architectures for N models

are used compute the parameters. The numbers correspond to the linenumbers in Algorithm− 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.7 Reusable multiplier architecture . . . . . . . . . . . . . . . . . . . . . . . 49

3.8 Experimental setup for the LTI model identification architecture validation 51

3.9 (a) Shows the identified model by the proposed architecture when modelsswitched for every 3µs and (b) switched for every 6µs . . . . . . . . . . . 52

3.10 FPGA power consumption results for 16 models between the directlymapped and proposed architecture . . . . . . . . . . . . . . . . . . . . . . 55

3.11 FPGA power consumption results for 32 models between the directlymapped and proposed architecture . . . . . . . . . . . . . . . . . . . . . . 55

3.12 FPGA power consumption results for 64 models between the directlymapped architecture and proposed architecture . . . . . . . . . . . . . . . 56

3.13 LUTs and FFs resource utilization of the proposed LTI MMAE architec-ture for number of models 1 to 1024 . . . . . . . . . . . . . . . . . . . . . 57

3.14 DSPs utilization of the proposed LTI MMAE architecture for number ofmodels 1 to 1024 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3.15 Power consumption of the proposed LTI MMAE architecture for numberof models 1 to 1024 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3.16 Comparison between the original data and regression analysis data forLUT utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.17 Comparison between the original data and regression analysis data forFF utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.18 Comparison between the original data and regression analysis data forFF utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

4.1 Proposed model identification block diagram . . . . . . . . . . . . . . . . 63

4.2 Block diagram of the proposed 3 stage architecture for MMAE basedLTV system model identification. Stage-1 is DKF computation, stage-2is residuals computation and stage-3 is minimum residuals identification.This architecture also corresponds to the MMAE part in Figure 1.2 shownin chapter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

4.3 Number of multipliers comparison between the conventional and proposedeight, four multipliers version architectures for n = 2 and models rangingform 1 to 256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

4.4 Proposed deterministic Kalman filter detailed architecture for computingxpestimate and Σp

estimate, in parallel n similar architectures are used for Nmodels to compute the parameters. (module 2 is shown in Figure 4.6) . . 68

4.5 Reusable multiplier architecture . . . . . . . . . . . . . . . . . . . . . . . 69

4.6 Proposed residuals computation architecture . . . . . . . . . . . . . . . . 71

4.7 The boost converter circuit diagram. When the PWM signal is 1, theMOSFET acts as a closed switch (S = 1) giving rise to the left-handcircuit. When the PWM signal is 0, the MOSFET acts as a closed switch(S = 0) giving rise to the right-hand circuit . . . . . . . . . . . . . . . . . 73

LIST OF FIGURES xiii

4.8 The detailed block diagram of the boost converter model identification, 1depicts the accurate model of the boost converter and 2 shows the MMAEblock diagram in Fig. 4.1, where N is the number of models. The PWMdetermines whether the top or bottom circuit is switched into the systemat any time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

4.9 Experimental setup for FPGA in loop, where coe stands for Xilinx coef-ficient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

4.10 Model identification comparison between the original model and identifiedby the proposed architecture with load resistance as an uncertain param-eter, load started with R1 = 5Ω and changed to R3 = 15Ω at 52msec,R2 = 10Ω at 104msec, R4 = 42Ω at 156msec and at 208msec R5 = 102Ω 77

4.11 Residuals plot for the 5 model MMAE architecture with residuals windowsize 500 where Resn= residuals for corresponding model number . . . . . 77

4.12 Mapping of the 50 models to boost converter load resistance range 1Ω−105Ω (case study-2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.13 Boost converter load resistance and identified load resistance by proposedarchitecture (case study-2) . . . . . . . . . . . . . . . . . . . . . . . . . . 80

4.14 Mapping of the 45 models to boost converter load resistance from 1Ω −250Ω (case study-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

4.15 Boost converter load resistance and identified load resistance by proposedarchitecture (case study-3) . . . . . . . . . . . . . . . . . . . . . . . . . . 82

4.16 Model-1 (5Ω) and Model-3 (15Ω) residuals comparison for various windowsizes, where Res200, Res500 and Res800 represents the residuals with win-dow size of 200, 500, 800 respectively. T1 = 52.9msec, T2 = 53.55msecand T3 = 54.25msec, load is switched from M1 to M2 at 52msec timeinstance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

4.17 Estimated voltage using the proposed architecture when load changingfrom 5Ω to 15Ω, where Vmeasured represents the measured output voltagefrom boost converter, M1 − V1 and M2 − V2 represents estimated voltageby using model-1 with 5Ω load and model-2 with 15Ω load respectively . . 83

4.18 Estimated voltage using the proposed architecture when load changingfrom 42Ω to 102Ω, where Vmeasured represents the measured output volt-age from boost converter, M4 − V4 and M5 − V5 represents estimatedvoltage by using model-4 with 42Ω load and model-5 with 102Ω loadrespectively . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

4.19 Resource utilization of look-up tables for various number of models from1 to 256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

4.20 Resource utilization of flip-flops for various number of models from 1 to256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

4.21 Resource utilization of DSPs for various number of models from 1 to 256 86

4.22 Power consumption analysis for various number of models from 1 to 256 86

4.23 Detailed power reduction comparison between eight and four multiplierversion filter bank for 190 models MMAE at operating frequency of 100MHz.An eight and four multipliers version architecture takes 10 and 15 clockcycles respectively . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

xiv LIST OF FIGURES

5.1 Block diagram of the proposed multiple model adaptive estimation basedcontrol of boost converter, where DKF1, DKF2,−−−DKFN representsthe deterministic Kalman filter which estimates output voltage of theboost converter for various load resistance values, N is the number ofload resistors, D is the switching delay . . . . . . . . . . . . . . . . . . . 93

5.2 Required PWM duty cycle for various load resistance values in range 7Ωto 90Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

5.3 Comparison between the proposed methodology and PID controller in-terms of boost converter out voltage and PWM duty cycle, when loadchanged from 25Ω to 8Ω and 8Ω to 55Ω. Benchmark-A1: Rload=8Ω(Model -1), Rload=25Ω (Model-2), Rload=55 Ω (Model-3). Total simula-tion time 0-200msec, initially boost converter stared with load 25Ω, attime instance 50msec load changed to 8Ω and at 100msec load changedto 55Ω. Plots for Benchmark A10 were given in appendix B . . . . . . . 100

5.4 Residuals plots for the 3 model EMMSAC based boost converter. WhereRn represents the residuals for model n. Rload=8Ω (Model -1), Rload=25Ω(Model-2), Rload=55 Ω (Model-3). Total simulation time 0-200msec, ini-tially boost converter stared with load 25Ω, at time instance 50msec loadchanged to 8Ω and at 100msec load changed to 55Ω (same graph fromtime 100msec to 200msec is shown in Figure 5.5) . . . . . . . . . . . . . . 102

5.5 Residuals plots for the 3 model EMMSAC based boost converter to ob-serve the residuals window impact on final residuals values between 100msecto 200msec time (same graph from time 0 to 200msec is also shown inFigure 5.4), where Rn represents the residuals for model n. Rload=8Ω(Model -1), Rload=25Ω (Model-2) and Rload=55Ω (Model-3). Total simu-lation time 0-200msec, initially boost converter stared with load 25Ω, attime instance 50msec load changed to 8Ω and at 100msec load changedto 55Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

5.6 Benchmark-B: 5 model based EMMSAC closed loop comparison betweenthe proposed methodology and PID controller in-terms boost converterout voltage and PWM signal, Vin = 5V and Vout = 10V. initially EMM-SAC PID PWM are started with default PWM duty cycle 0.30. Loadresistance (Rload) changes from 10Ω to 30Ω at 50msec, 30Ω to 8Ω at100msec, 8Ω to 85Ω at 150msec and 85Ω to 15Ω at 230msec . . . . . . . 104

5.7 Plot to show the effect of EMMSAC when wrong controller activated,when load changes from 25Ω to 8Ω and 8Ω to 55Ω. Benchmark-A1:Rload=8Ω (Model -1), Rload=25Ω (Model-2), Rload=55 Ω (Model-3). To-tal simulation time 0-200msec, initially boost converter stared with load25Ω, at time instance 50msec load changed to 8Ω and at 100msec loadchanged to 55Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

5.8 Block diagram of the experimental setup . . . . . . . . . . . . . . . . . . . 107

5.9 Real-time experimental setup . . . . . . . . . . . . . . . . . . . . . . . . . 107

5.10 ADC input/output pin details . . . . . . . . . . . . . . . . . . . . . . . . . 108

5.11 ADC timing (Source: AD7476A data sheet [4]) . . . . . . . . . . . . . . . 108

5.12 DAC input/output pin details . . . . . . . . . . . . . . . . . . . . . . . . . 109

5.13 Timing digram of DAC AD7303 (Source AD7303 data sheet [5] ). . . . . . 109

5.14 Proposed moving average filter architecture . . . . . . . . . . . . . . . . . 110

5.15 Proposed PWM signal generation architecture . . . . . . . . . . . . . . . . 110

LIST OF FIGURES xv

5.16 Plot to show the real-time measured and estimated voltages for the modelidentification when model changed from system-1 to system-2, whereVmeasured represents the measured boost converter output voltage, V1 rep-resents estimated voltage by model-1 and V2 represents estimated voltageby model-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

5.17 Plot to show the real-time measured and estimated voltages for the modelidentification when the model changed from system-2 to system-1. whereVmeasured represents the measured boost converter output voltage, V1 rep-resents estimated voltage by model-1 and V2 represents estimated voltageby model-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

5.18 Residuals and model identification plots with load resistance 33Ω, whenthe system changed from 1 to 2. At time instance 32.77msec systemchanged from 1 to 2, after 0.31msec time EMMSAC identified the changein model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

5.19 Residuals and model identification plots with load resistance 33Ω, whenthe system changed from 2 to 1. At time instance 32.77msec systemchanged from 1 to 2, after 0.32msec time EMMSAC identified the changein model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

5.20 Plots to show the time difference between the original model (OM) andidentified model (IM) when physical system changed from 1 to 2 underload resistance Rload 33Ω, 40Ω, 50Ω, 60Ω, 68Ω, 89Ω and 100Ω. Modelidentification time 0.32, 0.32, 0.31, 0.32, 0.31, 0.32 and 0.31msec respec-tively for aforementioned load resistances . . . . . . . . . . . . . . . . . . 114

5.21 Plots to show the time difference between the original model (OM) andidentified model (IM) when physical system changed from 1 to 2 underload resistance Rload =33Ω, 40Ω, 50Ω, 60Ω, 68Ω, 89Ω and 100Ω. Modelidentification time 0.31, 0.32, 0.32, 0.31, 0.31, 0.30 and 0.31msec respec-tively for aforementioned load resistances . . . . . . . . . . . . . . . . . . 115

6.1 Illustration of reconfigurable multiple model adaptive estimation . . . . . 120

B.1 Comparison between the proposed methodology and PID controller in-terms boost converter out voltage and PWM duty cycle, when loadchanges from 30Ω to 8Ω and 8Ω to 60Ω. Benchmark-A1: Rload=8Ω(Model -1), Rload=30Ω (Model-2), Rload=60 Ω (Model-3). Total simu-lation time 0-200msec, initially boost converter stared with load 30Ω, attime instance 50msec load changed to 8Ω and at 100msec load changedto 60Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

B.2 Residuals plots for 3 model EMMSAC based boost converter. Where Rnrepresents the residuals for model n. Rload=8Ω (Model-1), Rload=30Ω(Model-2), Rload=60 Ω (Model-3). Total simulation time 0-200msec, ini-tially boost converter stared with load 30Ω, at time instance 50msec loadchanged to 8Ω and at 100msec load changed to 60Ω . . . . . . . . . . . . 127

List of Tables

3.1 Comparison between the MMAE algorithm (Shown in algorithm-1) andproposed hardware modules in terms of the number of multiplications.Where sub-module 1-7 are associated with DKF, N= Number of models,n= number of states to be estimated, No. of mul=Number of multiplica-tions, H.W.A= Hardware architecture . . . . . . . . . . . . . . . . . . . . 46

3.2 Reusable multiplier operation. Kp=Kalman gain, AI=abs(Innovation)and SM=Sub module OTM=Output to the sub-module . . . . . . . . . . 49

3.3 Module wise breakdown of the FPGA resource utilization of the proposedLTI model identification architecture . . . . . . . . . . . . . . . . . . . . . 51

3.4 Resource utilization comparison in-terms of LUT between the proposedarchitectures with respect to the model size. Directly mapped = Directlymapping of the MMAE algorithm without a reduction in multiplications, 51

3.5 Resource utilization comparison in-terms of FF between the proposedarchitectures with respect to the model size. Directly mapped = Directlymapping of the MMAE algorithm without a reduction in multiplications,Proposed = proposed architecture, % percentage with respect to the totalavailable resources on VCU118-FPGA . . . . . . . . . . . . . . . . . . . . 53

3.6 Resource utilization comparison in-terms of DSP and power, between theproposed architectures with respect to the model size. Directly mapped =Directly mapping of the MMAE algorithm without a reduction in multi-plications, Proposed = proposed architecture, % percentage with respectto the total available resources on VCU118-FPGA . . . . . . . . . . . . . 53

3.7 Resource utilization comparison in-terms of power between the proposedarchitectures with respect to the model size. Directly mapped = Directlymapping of MMAE algorithm without a reduction in multiplications, Pro-posed = proposed architecture, % percentage with respect to the totalavailable resources on VCU118-FPGA . . . . . . . . . . . . . . . . . . . . 53

4.1 Total number of multiplication operations in model identification archi-tecture, N= Number of models, n= number of states to be estimated, No.of mul= Number of multiplications . . . . . . . . . . . . . . . . . . . . . . 67

4.2 Multiplier version-1 input data, where cx is the control bit and mulx isthe multiplier number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

4.3 Multiplier version-2 input data, where cx is the control bit and mulx isthe multiplier number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

4.4 Argmin module resource utilization . . . . . . . . . . . . . . . . . . . . . . 71

4.5 Steady state output voltage for the test loads with the 10kHz and 70%duty cycle PWM signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

4.6 Proposed architecture detailed model identification time for case study-1 . 80

xvii

xviii LIST OF TABLES

4.7 Proposed architecture LTV model identification average time . . . . . . . 84

4.8 Resource utilization comparison between 8 and 4 multipliers based ar-chitecture for single DKF, where mul= multiplier and Nclk is number ofclock cycles required for each DKF iteration . . . . . . . . . . . . . . . . . 84

4.9 Resource utilization comparison in-terms of LUTs between eight multipli-ers (8-mul) and four multipliers (4-mul) based architectures with respectto the model size (N). Where N= number of DKF models in MMAE,†=estimated LUT resources and percentage % with respect to the totalnumber of available resources on Virtex ultra scale+ FPGA . . . . . . . . 87

4.10 Resource utilization comparison in-terms of FFs between eight multipli-ers (8-mul) and four multipliers (4-mul) based architectures with respectto the model size (N). Where N= number of DKF models in MMAE,†=estimated FF resources and percentage % with respect to the totalnumber of available resources on Virtex ultra scale+ FPGA . . . . . . . . 87

4.11 Resource utilization comparison in-terms of DSPs between the 8 multipli-ers (8-mul) and four multipliers (4-mul) based architectures with respectto the model size (N). Where N= number of DKF models in MMAE,†=estimated DPSs and percentage % is with respect to the total numberof available resources on Virtex ultra scale+ FPGA . . . . . . . . . . . . . 88

4.12 Power consumption comparison between the 8 multipliers (8-mul) and 4multipliers (4-mul) based architectures with respect to the model size.Where N= number of DKF models in MMAE, †=estimated power andpercentage % is with respect to the total number of available resourceson Virtex ultra scale+ FPGA . . . . . . . . . . . . . . . . . . . . . . . . . 88

4.13 BRAM utilization for the 8 multipliers (8-mul) based and 4 multipliers (4-mul) architectures with respect to the model size. Where N= number ofDKF models in MMAE, % is with respect to the total number of availableresources on Virtex ultra scale+ FPGA . . . . . . . . . . . . . . . . . . . 88

5.1 The controller set PWM values for boost converter with various loadresistances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

5.2 Benchmark-A: Boost converter Rload changed to 2nd load at 50msec andto 3rd load at 100msec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

5.3 Benchmark B: Boost converter Rload is changed to 2nd at 50msec, 3rd at100msec, 4th at 150msec and 5th at 200msec. ‡ In this case 5th load isswitched at 230msec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

5.4 Boost converter Rload is changed to 2nd at 50msec, 3rd at 100msec, 4th

at 150msec and 5th at 200msec. ‡ In this case 5th load is switched at230msec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

5.5 ADC module output data (Input range 0v-3.3v and output range 0-4096) 109

5.6 Real-time closed loop model identification time for various load resistancevalues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

6.1 Resource utilization for single 2nd order model on FPGA. LTI= lineartime-invariant, LTV= linear time-variant . . . . . . . . . . . . . . . . . . 119

6.2 Possible approximate number of second order LTV models on variousFPGA boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

B.1 Boost converter circuit parameter and load range comparison with thestate-of-the-art designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Acknowledgements

My heartfelt gratitude to all my friends and peers in the VLSI, control and power

electronics community whose contributions in big and little ways to this fascinating field

have laid the foundations of this thesis.

I am grateful to my supervisors Prof. Mark French for giving me research freedom,

proposing interesting ideas, providing invaluable suggestions and being a patient mentor

throughout my PhD and Prof. Bashir M. Al-Hashimi for his direction and advice at

many times, for providing me with an opportunity to undertake this research and I

am inspired by his research vision and devotion to work, this PhD project would not

have been possible without his supports and encouragement. I also extend my thanks

to the School of Electronics and Computer Science, the University of Southampton

for providing state-of-the-art research facilities. Thanks to Prof. Geoff Merrett, Kath

Kerr and Jo Axtell for their kind administrative and logistics support. I would also

like to thank Dr. Amit Acharyya for always providing me with career guidance and

support. Many thanks also go to the Engineering and Physical Sciences Research Council

(EPSRC) for financially supporting me throughout the PhD.

I am grateful to the Southampton Sai family who made me feel at home even miles

away from my home. I would like to thank you my friend Dr. Satyanarayana Katla

for engaging in philosophical conversations during tea break times. Further, my sincere

thanks to all my friends who have always been there to help and for making my stay in

Southampton a pleasant memory. In this regard, I would like to mention a few notable

names who are part of our regular discussions at tea breaks sessions: Dr. Karunakar

reddy, Amin Sabet, Samuel Isuwa, Jie Zhan, Edward Longman, Lei Xun, Dr. Amit

Singh, Dr. Oktay Cetinkaya, Dr. Dominic Balsamo, Dr. Charlie leech, and Dr. Alberto

R. Arreola. Thanks to all members of the CPS group for creating an attractive and

vibrant research environment for thought-provoking discussions and knowledge sharing.

Finally, I would like to express my warmest gratitude to my mother Nirmala Vala, to

my father Srinivasulu vala, to my brother Sharath-Aswini, and to my sister Swapna-

Venkatesh for everything that they have done, and continue to do, for me. I would not

be who or where I am today without their encouragement and support.

xix

Abbreviations

ADC Analog to digital converterAFM Atomic force microscopeCS Chip selectCCM Continuous conduction modeCPS Cyber-physical systemsDKF Deterministic Kalman filterDSP Digital signal processing unitDAC Digital to analog converterDCM Discontinuous conduction modeEMMSAC Estimation-based multiple-model switched adaptive controlESR Equivalent series resistorFDI Fault detection and isolationFPGA Field programmable gate arrayFF Flip flopsGPU Graphics processing unitHDL Hardware description languageHEV Hybrid electric vehicleILA Integrated logic analyserILC Iterative learning controlLTI Linear time invariantLTV Linear time variantLHC Large hadron colliderLUT Look up tableMA Moving average filterMI Model identificationMIMO Multiple-input multiple-outputMMAC Multiple-model adaptive controlMMAE Multiple-model adaptive estimationODE23 MATLAB ordinary differential equation solverOWT Offshore wind turbinesPID Proportional integral differentiatePWM Pulse width modulatorSOC Self organizing controlSPI Serial peripheral interfaceSISO Single-input single-output

xxi

Nomenclature

δ Gap metric

∆ Transition delay function

D Delay operator

Mp Graph of Pp

E Disturbance estimator (operator)

fclk Operating frquency

h Step size

In Innovation

iL Inductor current

ki Switching time

ks(k) Last switching time up to time k

n Number of states

N Number of models

Nas Average number of samples

Nclk Number of clock cycles

Nts Total number of samples

Ok Ongoing switching times up to time k

Pk Position of vehicle

Pp∗ Physical system

q Switching signal

qf Free undelayed switching signal

Rload Load resistance

S Switching operator

Sclk System clock

ωn Uncertain natural frequency

u0 Physical system input disturbance

u1 Physical system input after disturbance u0

u2 Controller output

Vc Capacitor voltage

x(t) n-dimensional vector denotes the state of the system

y0 Physical system disturbance

y1 Physical system output before disturbance y0

xxiii

xxiv NOMENCLATURE

y2 Physical system measured output

Vk Velocity of vehicle

Chapter 1

Introduction

1.1 Motivation

Cyber-physical systems (CPS) integrate computing and communication capabilities with

monitoring and control of entities in the physical world [1]. These systems are usually

composed of a set of networked agents, including sensors, actuators, control processing

units, and communication devices, as shown in Figure 1.1. Research into and applica-

tions of CPS are receiving interest worldwide because of the many benefits they offer,

such as responding to highly uncertain working environments so that efficient operation

and use of resources may be achieved. Applications of CPS include high confidence

medical devices and systems [6], smart homes [7], safety, advanced automotive systems

[8], process control, energy conservation, environmental control, avionics [9], instru-

mentation, critical infrastructure control (such as electric power, water resources, and

communications systems) [10, 11], distributed robotics (telepresence, telemedicine), de-

fence systems, manufacturing, and smart structures [12, 13, 14, 15]. A typical challenge

Figure 1.1: General structure of cyber-physical system (Source [1])

1

2 Chapter 1 Introduction

Sensor

MMAE(Bank of Kalman

filters)

1

2…

N

Controller selection

1

2…

N

Network

Cyber Space

Actuator

Physical System

PhysicalPlant (Pp*)

𝑢0 𝑦0

++− −𝑢2 𝑢1 𝑦1 𝑦2

P1 P2 PN-1 PN

Network

Figure 1.2: Envisaged Cyber-physical system with estimation based multiplemodel adaptive control, where (u2, y2)T are the measured signals, (u0, y0)T arethe external disturbances and (u1, y1)T are the original signals at the input andoutput of a physical system (Pp∗) respectively

of control theory in all the applications mentioned is to design a control policy which

ensures that the CPS feedback loop remains stable under both model mismatch and ex-

ternal disturbances. Conventional non-adaptive controllers, including PID (proportional

integral differential) controller, robust control (H1 etc.), and optimal control with its im-

plementation as model predictive control (non-adaptive MPC), can tolerate both small

modelling inaccuracies (resulting from simplified, idealised physical system models and

uncertainty) and the existence of external disturbances applied to the system. As the

physical system uncertainty increases, the performance of the control system degrades

[16].

To overcome these challenges in CPS, a potential candidate is an advanced control

approach based on multiple model adaptive estimation (MMAE), called an estimation-

based multiple-model switched adaptive control (EMMSAC) [17, 18, 19, 2, 20, 21, 22].

EMMSAC involves selecting several models that could potentially represent the true

physical system, and determining the control signal based on their respective perfor-

mances, as determined by some measure of fit to the observed closed-loop signal. Gen-

erally, EMMSAC algorithms have the same basic structure shown in Figure 1.2. The

chosen N physical system models are collectively referred to as the physical system

model set, P1, P2...PN. For each model, Pp 1 6 p 6 N , a controller Cp is designed,

which is a member of the controller set, C1, C2, ...CN. The resulting physical system-

controller pairs, [Pp, Cp], are required to exhibit closed-loop stability. The main problem

Chapter 1 Introduction 3

associated with continuously-tuned algorithms is that, if the uncertain physical system

is parametrised over a non-convex set, it could lead to dangerous destabilising effects.

This problem does not arise when implementing EMMSAC schemes because the phys-

ical system models are pre-selected, which provides the ability to jump between any

of the corresponding controllers without exiting the parametrisation region. However,

due to the computational complexity issues, EMMSAC is still out of reach for real-time

applications, and its applicability to a wide range of CPS applications has yet to be ad-

dressed. In addition to software improvements, recent developments in computational

and communication technologies have increased the capabilities of embedded real-time

platforms, which potentially increases the scope of application of EMMSAC. Exploiting

hardware architecture for EMMSAC potentially allows the achievement of the best pos-

sible performance for the given computational resources. However, improvement of the

closed-loop performance cannot be considered as the only design objective.

From the hardware point of view, the most computational complexity of EMMSAC is

associated with the multiple model adaptive estimation (MMAE) which uses a bank of

Kalman filters for estimation. For a physical system with two states, if the controller

bank uses a typical adaptive PID controller set, 94% and 6% of multiplications are

associated with the MMAE filer bank and controller set respectively1. In practice, there

is a trade-off between performance and computational resource usage. Resources that are

required to perform computations include performance, power and area (PPA), which

are also the functions of the EMMSAC algorithm and hardware platform. Therefore, this

thesis focuses on efficient hardware architecture design and implementation for MMAE-

based linear time-invariant (LTI) and linear time-variant (LTV) model identification.

The following metrics are used to evaluate the designs:

1. Area: This is the number of configurable logic blocks (CLB), flip flops (FF) and

DSP units on the FPGA used by the design.

2. Clock speed: This is the maximum speed achievable by the hardware design. As

one fixed point value enters the design during each clock cycle, the design is able

to handle incoming data at clock speed bits/s. In this thesis, autonomous vehicle

application requires 70ns sample rate with the operating frequency of 100MHz and

power electronic application requires 5us sample rate with the operating frequency

of 100MHz.

3. Total time: Ideally this is the period of time between the arrival of the first input

and the output of the last result. However, this thesis considers model identifica-

tion time and closed-loop control time.

1A physical system with n-states required (1 + 3n+ 4n2 + 3n3) number of multiplications in Kalmanfilter and 3 multiplications in PID controller.


4. Throughput: This is computed as (total number of outputs)/(output time). The

output time is the period between generating the first result and outputting the

last result. For applications that generate input sets sequentially for reduction,

high throughput is more desirable than short latency. Thus, when multiple sets

are reduced, throughput is a better measurement of performance than total time.

1.2 Application selection

Recently, systems and control researchers have pioneered the development of powerful

system science and engineering methods and tools, such as time and frequency domain

methods, state-space analysis, system identification, filtering, prediction, optimisation,

robust control, stochastic control, optimal control [23], and multiple model adaptive

control [21, 24], to increase the performance of physical systems in the presence of un-

certainties. However, these algorithms must be adapted for real-time application to

achieve better performance. The applicability of these algorithms to emerging applica-

tions, like power electronics, health care, robotics etc., to improve their performance,

also needs to be investigated.

A few attempts have been made to use MMAE for applications such as estimation of

position and velocity states [25], atomic force microscope control [26], control of func-

tional electrical stimulation [20, 27, 28], MMAE extension to iterative learning control

[29] and its application for human movement assistance [30], power electronics [31, 32],

fault detection and isolation for power electronics devices [33] and batteries [34], state

of charge estimation for batteries [35, 36, 37], high speed train control [38], gas turbine

control [39], and control in nuclear power plants [40].

Nevertheless, control and systems science are choosing applications from a range of

established theoretical techniques to provide solutions involving both simulation and

technology demonstration. To accomplish this, a flexible and rapid prototyping and

benchmarking hardware environment are needed for investigating features such as scaling

the number of models and performance trade-offs of MMAE.

Bearing this in mind, autonomous vehicle application and power electronics DC-DC

boost converter applications have been chosen in this thesis for validating MMAE-based

LTI and LTV model identification architecture. The autonomous vehicle application was

not chosen to be potentially realistic as the experiment operates on far faster timescales

for switching than the real world, but to illustrate the methodology and implementation

before using them for a realistic example of a power electronics application in a later

chapter.


The LTV power electronics application DC-DC boost converter provides flexible, rapid

prototyping and benchmarking. Moreover, it has a wide range applications, such as pho-

tovoltaic (PV) power systems [41], offshore wind turbines (OWT) [42], electric/hybrid

electric/plug-in-hybrid electric/fuel cell vehicles (EV/HEV/PHEV/FCV) [43], medium-

voltage DC (MVDC) and high-voltage DC (HVDC) power systems [44, 45], telecom-

munication power supply [46], shipboard power systems [47], dc motor drives, personal

computers, home appliances, and portable electronics [48, 49]. These devices present

several challenges regarding their control issues, and require serious, high-quality, reli-

able, adaptive, and efficient, power supplies [50, 51]. Therefore, a boost converter is a

challenging application for investigating real-time MMAE performance for systems with

large uncertainty.

Due to the computational complexity of the MMAE algorithm, most of the above ap-

plications are validated in simulation and the computational complexity is a bottleneck

to use the MMAE in real-time resource-constrained applications. Applications such as

AFM and FES [27, 52] are implemented on the DSP platform with a 0.5Hz sampling rate

which is far behind the CPS applications requirement. To address these limitations, this

thesis focuses on designing dedicated custom hardware architectures to achieve high-

speed execution and lower hardware resources.

1.3 Research Objectives

1. To investigate the hardware architecture for MMAE based LTI system model iden-

tification, and to provide trade-off analysis for resource utilization for the higher

number of filter banks in the MMAE.

2. To investigate the hardware architecture by using a limited number of multipliers

in each filter bank for LTV system model identification, and to provide trade-

off analysis for resource utilization. To investigate an architecture to utilize the

BRAM memory for larger depth residual computation.

3. To investigate the applicability of the EMMSAC to a CPS power electronic appli-

cation to improve its closed-loop performance and real-time model identification

for two model based DC-DC boost converter.

1.4 Research Contribution

The following contributions are made by this work:

• To address the first objective of this research, for the first time a novel hardware

architecture for the multiple model adaptive estimation scheme of linear time-

invariant model identification is proposed. The architecture is implemented using


an FPGA for 16, 32 and 64 filter banks as part of position and velocity estimations

for an autonomous auto-mobile application. It is found that up to 78% reduction

in multiplications was possible, which translates to a reduction of 39% LUTs,

13% FFs, 27% DSPs, and 43% power reduction when compared with a directly

mapped architecture (without reusable multipliers and multiplications reduction)

at 100MHz operating frequency. Furthermore, the proposed architecture is able to

identify an accurate model of auto-mobile application within an average of 510ns,

in the presence of external disturbances and abrupt changes. The proposed archi-

tecture can be also utilized in CPS application like adaptive estimation, intelligent

adaptive plant control, position and velocity estimation.

• To address the second objective of this research, a novel linear time-variant cyber-

physical system model identification architecture is proposed based on the multiple

model adaptive estimation algorithm using eight and four multipliers in the esti-

mator filter bank. Furthermore, an architecture to utilize BRAM memory for

larger depth residual computation. This is the first-ever hardware architecture

for LTV model identification. The FPGA implementation of the architecture em-

ployed 16, 32, 64, 128, 190 and 256 models and demonstrated on power electronic

applications. The FPGA implementation area, power and speed are reported for

various banks of parallel Kalman filters of sizes between 16 and 256. It is found

that, with four multipliers in the estimator filter bank, a reduction of 17% LUTs,

14% FFs, 50% DSPs resource and 32% power consumption was possible by penal-

ising the number of clock cycles when compared with an eight multiplier version

at 100MHz operating frequency. The proposed architecture is able to identify

the physical system within us of time. This architecture suitable to use in real-

time resource-constrained edge computing embedded and cyber-physical systems

at high execution speed. This work will broaden the applicability of LTV model

identification to large uncertainty systems, in custom hardware platforms that

have been considered out of reach to date.

• To address the third objective of this research, for the first time an application of

the EMMSAC algorithm to the DC-DC converter is developed. Simulation results

found that the EMMSAC-based controller is superior to the regular PID controller

both in boost converter output voltage settling time and under/overshoot voltages.

It is shown that the EMMSAC significantly improves the closed-loop output volt-

age response time and settling time when compared with the PID controller and

it is demonstrated by the simulation results by changing the load resistance of the

boost converter abruptly. It is also identified that the EMMSAC method control

time improved by 10 times for smaller change in load and 20 times improvement

for a larger change in load. The real-time model identification for the two model-

based physical systems with positive and negative signs is also designed. The real-

time demonstration using the boost converter showed accurate identification of the


sign change. Due to the improved closed-loop timing performance, the proposed

method enables use of the EMMSAC for wider applications such as applications

photovoltaic power systems, offshore wind turbines and electric vehicles.

1.5 Publications

1. Vala, C.K., French, M., Acharyya, A., and Al-Hashimi, B.M. Low-Complexity

Architecture for Cyber-Physical Systems Model Identification. IEEE Transactions

on Circuits and Systems II: Express Briefs, 66(8):1416-20, 2018.

2. Vala, C.K., French, M., and Al-Hashimi, B.M. Linear Time Variant System Model

Identification Architecture with an Application in Power Electronics. IEEE Trans-

actions on Circuit and Systems-I: 2020 (under review).

3. Vala, C.K., French, M., and Al-Hashimi, B.M. Multiple Model Adaptive Estima-

tion Based Control for Cyber-Physical Systems with an application of DC-DC

Boost Converter. IEEE Control System Letters: 2020 (under review).

1.6 Thesis Organisation

Chapter 2 begins with a brief review of systems theory followed by a historical summary

of developments in adaptive control theory. Multiple model adaptive control is then de-

scribed and the advantages this approach provides over more conventional continuously-

tuned adaptive controllers are addressed. The chapter then focuses on a description

of EMMSAC, and applications of MMAE are discussed. This chapter also discusses

computing platforms such as CPU, GPU, DSP and FPGA, with their advantages and

disadvantages for implementing the MMAE algorithm.

Chapter 3 presents possible hardware architectures for the LTI model identification and

provides details of the proposed architecture. This is followed by a discussion on the

experimental results of FPGA in loop for a simple auto-mobile example, and compares

performance of the proposed methodology with conventional designs, in terms of resource

utilization and power consumption. Resource utilization analysis is also presented for

the higher number of models in MMAE.

Chapter 4 presents the LTV model identification hardware architecture in detail, with

an eight and four multiplier based DKF designs in the MMAE filter bank. It then

discusses the residuals architecture for the higher depth. Details are provided of the

proposed architecture validation of FPGA for the DC-DC boost converter application.

Various case studies are addressed, and their results using the proposed architecture

using the FPGA in loop experiment given. This chapter provides detailed resource

utilization and power consumption for various numbers of filter banks in LTV MMAE.


Chapter 5 presents an EMMSAC-based control methodology for a DC-DC boost con-

verter. This is followed by validation details of various benchmarks to show the closed-

loop timing performance. A detailed comparison is given of the results for simulations of

the proposed methodology with PID controller. A two model-based model identification

with a real-time boost converter using FPGA is demonstrated. The results show that

the proposed design is able to identify system changes within ms.

Chapter 6 provides a summary of the key contributions of the thesis. Potential future

directions for the work are given.

Appendix A Provides details of the constraint files used in FPGA validation of the LTI

and LTV model identification architectures.

Appendix B Presents detailed comparison of boost converter circuit parameters with

state-of-the-art designs and EMMSAC closed loop simulation results graphs.

Chapter 2

Adaptive Control in Cyber

Physical Systems and Computing

Platforms

This chapter begins by introducing the basic definition of adaptive control, notation

and systems theory. Both classical linear time-invariant control and classical adaptive

control, are outlined, and their respective limitations. The historical development and

features of multiple model adaptive control algorithms are discussed, which overcome

the limitations of classical adaptive control. A summary of multiple model architec-

tures follows, before introducing the recently-proposed estimation-based multiple model

switched adaptive control, an approach that embeds modern robust stability tools into

adaptive control. The potential advantages of this over the state-of-the-art algorithms

are addressed. Applications of the MMAE algorithms in cyber-physical systems are

discussed in detail. Feasibility of implementing the MMAE algorithm on various com-

puting hardware platforms, such as CPU, GPU, DSP, and FPGA, is discussed in detail,

together with basic evaluation terminology and the advantages of the FPGA platform.

2.1 Control Systems Theory

2.1.1 Preliminaries

• Continuous-time and discrete-time signals: If a signal is defined for all time t

contained in some interval on the real line (numbers from −∞ to ∞), it is called

a continuous-time signal, often also called an analogue signal. If the signal is

restricted to a set of discrete points (natural numbers n = 1, 2, 3, ..... ) then

that signal is called discrete-time signal, often also called a digital signal.

9

10 Chapter 2 Adaptive Control in Cyber Physical Systems and Computing Platforms

• System: A system is any process that produces an output signal in response to

an input signal, as shown in Figure 2.1. Generally, systems are modelled using

differential equations that represent systems functionality. The interconnection of

system with a controller is called a control system.

Figure 2.1: System

Time domain signals and systems are difficult to analyse; therefore signals and systems

can also be represented in the frequency domain, i.e. as functions of frequency as opposed

to functions of time. The frequency domain representation of a continuous-time signal

is obtained by taking the Laplace transform of the signal. In general,

L [x(t)] =

∫ ∞0

x(t)e−stdt = x(s) (2.1)

where s is a complex number. The equivalent discrete-time signal in the frequency

domain is given by the Z-transform

Z [x(n)] =

∞∑0

x(n)z−ndt = x(z) (2.2)

It is to be noted that by applying the inverse transform, these frequency domain signals

can be converted back into the time domain.

2.1.2 Norms on Signals

To describe the performance of a system, the size of certain signals of interest is used.

Norms can be applied in both the time-domain and the frequency-domain. To qualify

as a norm, they must possess the following properties:

1. positivity, x = 0 ⇐⇒ ‖x‖ = 0

2. homogeneity, ‖ax‖ = ‖a‖‖x‖; a ∈ R

Chapter 2 Adaptive Control in Cyber Physical Systems and Computing Platforms 11

3. triangle inequality, ‖x+ y‖ 6 ‖x‖+ ‖y‖

In general, the continuous-time Lp norm of a signal x(t) is given by

‖x‖p =

(∫ ∞0|x(t)|pdt

)1/p

, 1 6 p 6∞ (2.3)

Several norms are commonly used in the analysis of control systems. The one-norm

(p = 1) is simply the integral of a signal (or sum in the discrete-time case). The two-

norm (p = 2) measures the energy content of a signal. The infinity-norm (p =∞), which

does not fit the general norm equation, is given by

‖x‖∞ = ess sup|x(t)|, 0 6 t 6∞ (2.4)

where ess sup is called essential supremum. It produces the maximum value or least

upper bound of the magnitude of the signal to which it is applied, which is a useful

metric for testing the boundedness of signals. The equivalent discrete-time lp− and

l∞− norms are given by

‖x‖p =

( ∞∑0

|x(i)|p)1/p

, 1 6 p 6∞ (2.5)

and

‖x‖∞ = supi∈T|x(i)| (2.6)

respectively, where T can be the set of natural numbers N or the set of integers Z.

2.2 Introduction to Adaptive control

In everyday language, to “adapt” means to change a behaviour to adjust to new circum-

stances. Intuitively, an adaptive regulator is a regulator that can modify its behaviour

in response to changes in the dynamics of the process and the disturbances. Since classic

feedback control was introduced for the same purpose, the question of the difference be-

tween feedback control and adaptive control immediately arises. There have been many

attempts to define adaptive control. At a symposium in 1961, a long discussion ended

with the following suggestion: “An adaptive system is any physical system that has been

designed with an adaptive viewpoint.” A new attempt was made by an IEEE committee

in 1973, which proposed a new vocabulary based on notions of a self-organizing con-

trol (SOC) system, parameter-adaptive SOC, performance-adaptive SOC, and learning

control system [53, 54].


Adaptive control covers a set of techniques which provide a systematic approach for

automatic adjustment of controllers in real time, in order to achieve or to maintain a

desired level of control system performance when the parameters of the plant dynamic

model are unknown and/or change in time [53, 55]. The requirements of any good control

system are speed, accuracy, and stability. Achieving these in complex systems, in the

presence of large uncertainty concerning the process to be controlled, is the challenge for

the control theorist today. The realisation that conventional controllers do not possess all

the attributes necessary to achieve such control has, in recent years, given rise to several

definitions for intelligent control. The perspective adopted here is that intelligent control

is merely the ability of the control system to operate successfully in a wide variety of

situations by detecting the specific situation that exists at any instant and servicing

it appropriately. External disturbances, changes in subsystem dynamics, parameter

variations, etc., are examples of different unknown environments in which the system

has to operate. These are discussed below in detail.

Robust control theory considers the physical system Pp∗ that was shown in Figure 1.2,

and is represented by equations P1, also called a model. These models are obtained by

analytical or empirical techniques, and are therefore an approximation of the physical

system. A mismatch between the model (P1) and physical system (Pp∗) is inevitable.

This mismatch is strongly influenced by the nature of the dynamics of the physical

system and the requirements of the control objective.

For example, a room heating system within a building does not require a very accurate

model of the physical properties of the room, so a coarse model is sufficient to develop the

controller that keeps temperature variations within limits. However, to control human

limbs in milliseconds by functional electrical stimulation (FES), an accurate model of

electrically stimulated muscle is essential [27]. To assess the mismatch of the physical

system and the model, or the uncertainty in the physical system, a so-called uncertainty

model is typically invoked. The mismatch is measured by the gap (metric) between

the physical system and its mathematical model, as represented by δ(P, P1) [56, 57].

Robustness analysis is typically used to assess the level of uncertainty in the physical

system that can be tolerated before either the system performance degrades beyond

some required level or, in the worst case, the system becomes unstable.

The second major factor influencing the stability and performance of dynamical systems

are external disturbances acting on the physical system. A stable system has to remain

so, even in the presence of disturbances. For example, an airplane guided by an au-

topilot shows good disturbance rejection since it maintains its course and altitude even

in the presence of disturbances, e.g. wind or air pockets. In contrast, an example of

unwanted disturbance amplification was the Tacoma Narrows suspension bridge, where

disturbances from strong winds caused resonant oscillations of increasing magnitude in

the bridge structure and ultimately led to its destruction.


Therefore, a typical problem in control theory is to design a control policy to ensure

that the CPS feedback-loop remains stable under both model mismatch and external

disturbances. Typically applications will possess a high level of system uncertainty.

Several attempts have been made to address these issues, some of which are discussed

here.

2.3 Classical Adaptive Control

PhysicalSystem (Pp*)

𝑢𝑢0 𝑦𝑦0

++− −

Controller (C)

𝑢𝑢2 𝑢𝑢1 𝑦𝑦1 𝑦𝑦2

Figure 2.2: General control system with feedback

The general structure of a control system is shown in Figure 2.2. The closed loop

interconnection of the physical system, Pp∗ , and its controller, C, is represented by the

following equations:

y1 = Pu1, u0 = u1 + u2, y0 = y1 + y2, u2 = Cy2 (2.7)

where w0 = (u0, y0)ᵀ represents the input and output disturbances present in the system,

w1 = (u1, y1)ᵀ represents the physical system input and output, and w2 = (u2, y2)ᵀ

represents the controller input and output, respectively. In general, the disturbances

w0, and therefore the system signals w1, are unknown. The control input, u2, and

the measurable physical system output, y2, are observable signals. To allow stability

and robustness analysis of the closed-loop system, [Pp∗ , C], to be performed, the loop is

required to be well posed. That is, for all external (norm-bounded) signals w0 there exist

unique (possibly unbounded) signals (w1, w2) that are consistent with Equation (2.7).

In classical linear time-invariant (LTI) control theory, LTI feedback loops were used to

control the physical system. This method allowed the system to tolerate both small

modelling inaccuracies (resulting from simplified, idealised physical models and physical

system uncertainty), and the existence of external disturbances applied to the system.

If the performance of the control system degrades due to the increase in uncertainty in

the physical system, such controllers are called conservative. For example consider a


physical system (P ) given by the transfer function

P : u1 7−→ y1 : y1 =1

s− au1 (2.8)

C : y2 7−→ u2 : u2 = −ly2, l > 0 (2.9)

Let a > 0 be a fixed but uncertain parameter, for example an unknown mass, and

consider a proportional controller to be in a closed loop interconnection with P as in

Figure 2.2. The resulting closed-loop transfer function from y0 to u1 is given by

S =u1

y0=

C

1− CP=

l(s− a)

s+ (l − a)(2.10)

where u1, y0 are the Laplace transforms of the corresponding time domain signals. All

poles must reside in the left complex half plane in order to ensure bounded input -

bounded output (BIBO) stability of S. This requires us to choose the controller gain

l larger than a. Consequently for a large uncertainty in a, i.e. if all that is known is

that |a| ≥ amax where amax is large, we will have to choose a large l, i.e. l > amax,

to ensure stability of S. The maximum gain from the external disturbances to the

physical system signals scales with |a| ≥ amax and therefore its inverse, the robust

stability margin, shrinks to zero as amax becomes large. Other example linear quadratic

regulator is only stable if the phase angle of the uncertainty is less than 60 degrees in

magnitude. One way of showing that a controller is non-conservative is therefore to

show that it is universal. A controller is said to be universal if it maintains a constant

level of performance invariant to the uncertainty in the system.

If the physical system uncertainty exceeds that required for robust-stability or perfor-

mance, a more complex feedback architecture can be implemented in the form of an

adaptive controller. Adaptive controllers can be used to avoid conservative designs, i.e.

they are universal [58]. The first adaptive controllers attempted to overcome the limi-

tations of feedback control by using performance information of the closed-loop system

to determine how the controller parameters should be adapted. Although this was a

promising approach, early continuously-tuned algorithms lacked theoretical guarantees

for stability and performance from a robust control perspective. Rohrs et al. [59] il-

lustrated this lack of robustness and it was shown that, unlike their LTI counterparts,

adaptive controllers were unable to tolerate, what were thought to be, harmless plant

uncertainty and external disturbances without becoming unstable. Other deficiencies

associated with continuously-tuned algorithms are given in [16] with Rohrs counter-

example. To address these issues, multiple model adaptive control was introduced.


2.4 Multiple Model Adaptive Control

To overcome the limitations associated with continuously tuned algorithms, multiple

model adaptive control (MMAC) comprises a number of models that could better repre-

sent the true physical system, and determine the control signal based on their respective

performances, as determined by some measure.

2.4.1 Historical Development of MMAC

Initial multiple model adaptive controllers, for example those of Lainiotis et al. [60],

Athans et al.[61] and Chang et al. [62], were developed to produce accurate estimates of

system states in systems with parametric uncertainty. In such examples, the local state

estimate and residuals of a physical system are computed using banks of Kalman filters.

The local state estimate is then used to assess how closely it represents the true system

state, and is termed posterior probability evaluation. A global state estimate is then

created by blending the local state estimates. Blending is achieved using a weighted

sum of two or more local control signals, the weights for each signal being determined

by the performance of their associated physical systems. In the closed loop switched

version of this algorithm, the control signal is associated with the physical system model

with largest posterior probability, and all other control signals are weighted to zero.

Classical multiple model adaptive control (CMMAC) is an extension to MMAC that

uses the state estimate for each physical system model and a corresponding controller

(for example a linear quadratic optimal controller) to produce a control signal for that

physical system model. Similar to MMAE, Kalman filter residuals are used to determine

weights for each of the local control signals (as opposed to the state estimates), which

are blended to produce the global control signal (see Griffin et al. [63] for practical

examples). Fekri et al. [17] presented robust multiple model adaptive control (RMMAC),

in which mixed-µ synthesis is used to develop output feedback controllers. To simplify

the robustness analysis of the algorithm in this work, identification and control processes

are separated by using feedback as opposed to state feedback. MMAE and CMMAC were

used in He et al. [64], Yu et al. [65], Athans et al. [66], Menke and Maybeck [67]). For

practical applications however, theoretical robust performance results for these schemes

are lacking.

This limits the development of a principled procedure by which the physical system

model set (and corresponding controller set) can be designed. Anderson et al. [68]

and Fekri et al. [17] made an attempt to assess stability and performance, based on

the robustness margins of the individual physical system-controller pairings, (Pp, Cp).

Although this resulted in a principled procedure by which the physical system model sets

can be selected, it gave no indication how a particular selection would affect the global

performance of the algorithm. In contrast, significant theoretical robustness results


have been developed for so-called multiple model switched adaptive control (MMSAC)

algorithms, which are discussed in following section.

2.4.2 Multiple Model Switched Adaptive Control

PhysicalPlant (Pp*)

𝑢𝑢0 𝑦𝑦0

++− −

Controller (C) Switch (S)

𝑢𝑢2 𝑢𝑢1 𝑦𝑦1 𝑦𝑦2

𝑦𝑦2

q

Figure 2.3: Switched control system with feedback (Source [2])

The block diagram of MMSAC setup is shown in Figure 2.3, where Pp∗ represents the

true physical system with input-output signals w1 = (u1, y1)ᵀ. The external disturbances

acting on the system are represented by w0 = (u0, y0)ᵀ. w2 = (u2, y2)ᵀ represents the

observable signals while u2 is the control input applied to the system, and y2 is the

measurable output from the physical system after disturbance. The model performance

evaluating function is contained within the switching block, S, and it is most commonly

achieved through observation of signals w2. The output, qf (k), indicating the closest

to the physical system model, Pq(k) ∈ P1, P2, .....PN, is used in C to switch the

corresponding controller, Cq(k) ∈ C1, C2, ......CN, into the closed loop at sample instant

k. Note that the underlying controller can incorporate state feedback as well as output

feedback designs.

Performance of each model can be assessed by feeding each of the physical system models

P1, P2, .....PN with the control input, u2, and comparing the resulting outputs with the

output from the physical system. The output error obtained can be used to indicate

the performance of each model, the smaller the error the closer the physical system-

model to the true physical system. However, this method is limited since the model’s

initial conditions are required to match those of the physical system, otherwise a growing

output error can occur, even if the physical system and model are identical. This problem

only presents itself if both the physical system and model are unstable, which imposes

a significant restriction on the type of physical system that can be considered when

implementing this performance measure.


To overcome this limitation (state) observers can be implemented. Observers uses both

the control input, u2, and the measured output, y2, from the physical system to produce

an estimate of its state. Assuming no disturbances, the state estimate converges to

the true state (independently of the stability characteristics of the physical system and

model) and hence the output error converges. The block diagram of an observer-based

control system is shown in Figure 2.4, where Pp∗ represents the true physical system and

O1, O2, .......ON are bank of observers, one designated for each of the n physical system

models. The output errors are represented by e1, e2, .....eN , which are used to identify the

physical system model (minimum error model) that best matches the observation, w2.

The history of the error signal in integral form can be accounted for when implementing

the switch.

PhysicalPlant (Pp*)

𝑢0 𝑦0

++− −

Observer-1

𝑢2 𝑢1 𝑦1 𝑦2

Error-N

Observer-2

Observer-N

Error-2

Error-1

𝑦2

𝑦2

𝑦N

𝑒2

𝑒N

𝑒1

Figure 2.4: Observer-based control system (Source [2])

Several attempts have been made to establish theoretical robustness results for observer-

based MMSAC schemes. Morse [18] implemented an observer-based MMSAC scheme

for a fixed LTI single-input single-output physical system, and showed output conver-

gence (given prior knowledge of the parametric physical system uncertainty). Morse

[19] extended this to include additive and multiplicative perturbations in the analysis.

Morse [69] gave an explicit bound on the gain from the disturbance to the tracking er-

ror. Although these are promising theoretical results, the generality of the algorithm is

limited by restrictions on the physical systems and controllers considered (e.g. physical

systems are single-input/single output and the true system is assumed to have a pole at

zero). Furthermore, the analysis is performed in l2 and lacks a complete unstructured

(general) uncertainty model.

An alternative approach is the use of optimal disturbance estimation, as suggested by

Fisher-Jeffes [70]. Specifically, the performance of each physical system model, Pp, 1 6


p 6 N , is determined by the size of the smallest disturbance estimate, w0, that explains

the signals, w2, observed from the true physical system. The estimate, w0, represents the

(smallest) distance between the physical system model, Pp, and the observation, w2. To

each physical system model, Pp, is assigned a scalar (or residual), rp, that indicates the

size of its smallest disturbance estimate. The residuals are then compared to determine

which model best explains (with minimal disturbances) the observed signals. Then,

as previously described, the switching signal, q, is specified, and the controller, Cq,

corresponding to the chosen physical system, Pq, is switched into the loop.

Disturbance estimation is a (well-studied) convex optimisation problem that can be

solved by a number of different algorithms. Similar to observer-based schemes, attempts

have been made to establish theoretical robustness results for estimation-based schemes.

Vinnicombe [71] established l2 gain bounds from the disturbances to the system state

for estimation-based multiple model switched adaptive controllers. Recall that internal

stability can be guaranteed if, when injected with finite-energy signals, the system re-

sponds with finite-energy signals, i.e. the gain from w0 to w2 (or equivalently the state)

is bounded. These results were extended in [72] to obtain lp, 1 6 p 6 ∞ gain bounds

for a broader class of physical systems with additive disturbances included on both the

input and output. This represents a key extension to previous work as it allows the ana-

lytical (gap metric) framework presented by Georgiou and Smith [73] to be used, albeit

with restrictions on the underlying controllers (they are required to be dead-beat).

The generalisation of these results to multiple-input, multiple-output LTI systems ap-

peared in Buchstaller and French [58], with the important result that the gain bounds

are invariant with the size of the physical system model set (Buchstaller and French,

[21]). Instead, the established gain bound is dependent on a finite cover of the uncer-

tainty, U , representing the true physical system. These results form the basis for a

general robust multiple model adaptive control theory, estimation-based multiple model

switched adaptive control (EMMSAC) (Buchstaller part-I, II [21, 22]), based on the

aforementioned framework (the gap metric) developed by Georgiou and Smith [73]. Be-

fore a more detailed description of the EMMSAC methodology is provided, a number of

features of MMAC schemes that encourage their use are highlighted.

2.4.3 Features of MMAC Algorithms

MMAC algorithms provide advantages over their continuously-tuned counterparts. Some

of these relate to their structure, analysis, and implementation [2]. In general, physical

system model identification, and the implementation of feedback control, are separate

in that they are only joined by the switching signal (although, of course, they share the

feedback signal y2). Therefore, MMAC allows freedom in the selection of the underlying


controller, the only restriction being the chosen control design produces stable closed-

loop pairs [Pp, Cp], 1 6 p 6 N . Due to this, any existing control design can be imple-

mented with MMAC. Conversely, the control design for continuously-tuned algorithms

is constrained by the structure of the algorithm itself. The ability to jump between

physical system models (and controllers) also allows MMAC algorithms to overcome the

simultaneous stabilisation problem, which concerns the ability of a single controller C

to ensure closed-loop stability for two different physical systems, P1 and P2.

Likewise, MMAC schemes are easily applied to multiple-input multiple-output (MIMO)

control problems due to lack of restriction on the dimension of the associated signals.

Moreover, changes to one component do not necessarily require changes to the other,

which is of benefit when performing analysis or applying the algorithm practically. Note

that the restrictive nature of existing analytical developments for observer-based algo-

rithms mean that the above properties are not preserved (Buchstaller [21, 22]). EMM-

SAC is an example of such an algorithm. This suggests that a model identification

hardware architecture be designed for LTI and LTV systems, based on MMAE used in

EMMSAC.

2.5 EMMSAC

EMMSAC is one of the multiple model switched adaptive control schemes, which uses op-

timal disturbance estimation to evaluate the physical system model performance. EMM-

SAC was developed from the key ideas in Fisher-Jeffes [70] as a general multiple model

for adaptive control design methodology in Buchstaller [21, 22], in which efforts are

directed towards the development of a systematic design approach that is grounded in

theory and provides a principled procedure by which physical system model sets can be

selected. EMMSAC is a generalised algorithm that can be applied to a wide class of

linear systems (both SISO and MIMO), and also to non-linear systems exhibiting linear

growth. It allows almost complete freedom in the choice of the underlying controller

design. The resulting algorithm is completely deterministic, i.e. there are no stochastic

assumptions made of the disturbances, only that they are bounded in the appropriate

lp, 1 6 p 6 ∞ norm. Analysis is independent of the uncertainty objects associated

with traditional (robust control) methods, which allows the analysis to be performed for

any lp, 1 6 p 6 ∞ norm. Additionally, the features that encourage the use of MMAC

algorithms, given in Section 2.4.3, are preserved by EMMSAC. Details of the algorithm,

including the estimation and switching processes from [2, 20], are given in the following

sections.


Figure 2.5: EMMSAC block diagram (Source [2])

2.5.1 Disturbance Estimation

For the EMMSAC as shown in Figure 2.5, given the system with

y1 = Ppu1 (2.11)

u0 = u1 + u2 (2.12)

y0 = y1 + y2 (2.13)

the disturbance estimation procedure produces, for each physical system hypothesis Pp

1 6 p 6 N , a measure of the size of the disturbance estimates, w0 (associated with

physical system p), that explain the observed signals, w2. Attention focuses on the

physical system model disturbances w0 for which (2.8) to (2.10) are compatible with the

measured signals w2 over the interval [a, b]; a 6 b, a, b ∈ Z.

Based on the disturbance estimate results, residuals for each physical system are cal-

culated. Estimators are broadly classified into two categories, the infinite-horizon and

the finite-horizon. N [a,b]p (w2) represents the set of all disturbance signals, w0, that are

compatible with the observed signals, w2, and signal relationships (2.17) to (2.19) for

the physical system Pp, over the interval [a, b], a 6 b, a, b ∈ Z. The infinite-horizon

estimator (estimator A) generates disturbance estimates at each time interval, and is


given by French and Trenn [72].

EpA(w2)(k) = dpA[k] ∈ map(N,Rh) (2.14)

dpA[k] = Tk argminwp0∈N [0,k]p (w2)

‖wp0‖ (2.15)

where Tk is an operator used to truncate signals at time step k. The estimator structure

is such that the estimation of disturbances is, in general, not a recursive procedure. This

means that disturbance estimates up to time k, computed at time k2, are not necessarily

equal to the same disturbance estimates produced at an earlier time, k1, i.e.

Tkdp[k2] 6= Tkdp[k1], k2 > k1 > k > 0 (2.16)

Here dp[k2] is the time series of disturbance estimates for physical system model p over

the interval [0, k2], produced at time k2, i.e.

dp[k2] = (dp[k2](0), .......dp[k2](k2)) (2.17)

and Tkdp[k2] is the truncation of this time series up to time k2, i.e.

Tkdp[k2] = (dp[k2](0), .......dp[k2](k2)) (2.18)

The residual operator for the infinite-horizon estimator is given by

RpA(w2)(k) = rpA[k] = infr > 0|r = ‖v0‖, v0 ∈ N [0,k]p (w2) (2.19)

This states that the residual for the physical system Pp at time k is given by the size of

the smallest disturbance estimate that is a member of the set of all disturbance estimates

that explain the observation (i.e. satisfy relationships (2.11) to (2.13) for the particular

physical system model. The infinite-horizon estimator considers the full time series of

the disturbance estimates when computing the residual. Thus computation of rp[k], in

general, will result in a growth in computational complexity with increasing k.

However, there is a special case for which the computation of rp[k] is recursive, when

the estimation is performed in an l2 setting using a Kalman filter with an LTI physical

system. In that case, the computational complexity of the resulting estimation depends

only on the order of the physical system model (since this order determines the dimen-

sions of the associated state-space matrices used to implement the filter). Note that

the estimator is then identical to the observer-based performance function employed in

MMSAC, where the observer takes the form of a Kalman filter. Since the only known

practical implementation of the infinite-horizon estimator performs the estimation in l2,

use of the infinite-horizon estimator restricts practical implementation of the algorithm

to the l2 setting.

To overcome this problem, a finite window of observed signals, w2, can be considered,


so that the estimation is performed on a finite-horizon. The resulting finite-horizon

estimator (estimator B) is given by

EpB(w2)(k) = dpB[k] ∈ map(N,Rh) (2.20)

dpB[k] = Tk argminw0∈N [k−λ,k]

p (w2)

‖w0‖ (2.21)

with residual operator

RpB(w2)(k) = rpB[k] = ‖rpB[k − 1], ip[k]‖, (2.22)

ip[k] = infr > 0|r = ‖v0‖, v0 ∈ N [k−λ,k]p (w2) (2.23)

This minimisation can be written in a more general form as a constrained (convex)

optimisation problem. Although the solution is non-unique (convexity implies that any

local minimum, of which there may exist more than one, is a global minimum) in both l1

and l∞, it is the size of the disturbance estimate that is of interested, which is unique for

all solutions. To solve the optimisation in l1 and l∞, linear programming techniques, such

as the ellipsoid method, the interior point method, or the simplex algorithm (see [74]),

can be used. The problem can be solved in lp, 1 6 p 6 ∞ or in the non-linear domain

using one of gradient descent algorithms, Newtons method, or geometric programming

(see [75]). These methods for solving convex optimisation problems are well-studied for

various nonlinear scenarios. In contrast, the construction of observers for a wide class

of nonlinear systems is relatively unclear, which gives estimation-based algorithms a

significant advantage over their observer-based counterparts.

2.5.1.1 Disturbance Estimation using Kalman filter

Dynamics of cyber-physical systems often depend on random events and operate in

noisy environments. Therefore, it is difficult to model these dynamics in mathematical

form. Due to the accurate prediction of model output by using simple observers, without

use of statistical tools and concept of probability, it becomes a challenging task. The

filtering problem is then to estimate one state information using another measured state

information, which often has uncertainties. The solution is to use an observer that takes

into account the underlying stochastic nature of the system, for example a Kalman filter

(Kalman, 1960), which uses knowledge of the system and the measured signals to form

optimal estimates of system variables. The filter is optimal in the sense that it seeks to

minimise the residual error between the prediction of the system state at the next sample

instant and the actual measured value when the system reaches that sample instant.

The main feature of EMMSAC is the use of observers to form estimates of the small-

est disturbances for physical system. To yield a recursive solution to this constrained

optimisation problem in discrete-time, Fisher-Jeffes [70] used dynamic programming.


Willems [76] showed the equivalence of the Kalman and least squares filtering problems

in continuous-time. These results enable the use of the Kalman filter as a purely deter-

ministic state observer. The Kalman filtering equations are given below in detail. For

given physical system model, Pp, with initial state x(0), and discrete-time state space

representation described by

xp(k + 1) = Apxp(k) +Bpu1(k) (2.24)

yp1(k) = Hpxp(k), k ∈ N (2.25)

where xp(0) has the possibility of being non-zero. The corresponding discrete-time

Kalman estimator is,

Ip(k) = y2 (k)−HpXpestimate(k) (2.26)

Kp(k) = Σpestimate(k)HT [HpΣp

estimate(k)HpT + Ip(k)]−1

(2.27)

Xpupdate(k) = Xp

estimate(k) +K(k)Ip(k) (2.28)

Σpupdate(k) = Σp

estimate(k)−K(k)HpΣpestimate(k) (2.29)

Xpestimate(k) = ApXp

update(k) +Bpu2(k) (2.30)

Σpestimate(k) = ApΣp

update(k)ApT +BpBpT (2.31)

with initial conditions Σpestimate(0) = 0 and Xp

estimate(0) = 0, and observable signals w2.

The correction step, in which measurements from the physical system are used to update

the state estimate, Xpestimate, and covariance, Σp, is represented by (Equations 2.28 and

2.29). The prediction step, in which the model of the physical system is used to form

an estimate of the state (and covariance) at the next sample instant, is represented by

(Equations 2.30 and 2.31).

The filter produces an estimate, yp1 , of the physical system output, y2, for the physical

system model Pp with initial conditions xp(0), driven with disturbances (u0, y0). Im-

portantly, (u0, y0) are the optimal disturbance estimates that are consistent with the

physical system model and the observed signals (u2, y2). The Kalman filter also pro-

duces a residual, which is related to the optimal disturbance estimates, and is computed

recursively. For this implementation, the residual is given by the following theorem,

from Buchstaller et al. [21, 22].

Theorem 2.1. Let Pp = (Ap, Bp, Hp, 0) be the state-space representation of an LTI

physical system model. Let the Kalman estimator described by (equations 2.26-2.31) be

used to perform the estimation for physical system model Pp with interconnections. Let

Σpestimate(0) = 0 and Xp

estimate(0) = 0. Then the (scaled) residual for physical system

model Pp at sample instant T is given by the weighted l2-norm

RpA(w2)(k) = Rp(T ) =

[T∑t=0

‖y2 −Hpxp‖2[HpΣpHpT+1]−1

]1/2

, T ≥ 0 (2.32)


Proof: The proof can be found in Buchstaller [21, 22]. It is based on Willems [76],

which develops a deterministic interpretation of the Kalman filter that is related to the

least squares estimation problem. In equation 2.32, y2 is the measured physical system

output; y1 is the Kalman filter estimate of the output of the physical system model Pp

before disturbance, y0 and Σp(k) is the covariance of the updated state estimate. It can

be shown that Σp(k) > 0 for all k ∈ N provided Σp(0) > 0, and hence [HpΣpHpT + I]−1

exists. The calculation can be performed recursively using

Rp(T ) =[Rp2(T − 1) + ‖y2 −Hpxp‖2[HpΣpHpT+1]−1

]1/2(2.33)

The recursive nature of the residual calculation allows a computationally tractable im-

plementation of the infinite-horizon optimal disturbance estimator (estimator A) in l2

with an LTI physical system. In this case, the computational complexity depends not

on k, but on the order of the physical system model Pp. Thus the ability to use the

Kalman filter as an optimal disturbance estimator is a significant result that allows the

EMMSAC algorithm to be applied practically in l2 with an LTI physical system. How-

ever, since only the final magnitude of residuals is of interest, to reduce the hardware

complexity, this thesis considered summation of innovations over the period of time as

a residuals2. Note that estimation- and observer-based algorithms have identical per-

formance functions in this special case. Therefore, there is some overlap between the

applied EMMSAC algorithm and the observer-based MMSAC, but also their predeces-

sors, MMAE and MMAC, which use Kalman filters (albeit in a stochastic setting) to

generate estimates and performance measures.

2.5.2 Switching Algorithm

For the physical system model set P1, P2, .....PN, the switching signal, q is defined by

following equation

qf (k) = argmin16p6N

Rp[k],∀k ∈ N (2.34)

where q indicates the physical system Pp, 1 6 p 6 N with minimal residual Rp[k] at

sample instant k, and qf represents the free switching signal. Hence qf (k) is a direct

function of the magnitude of the residuals. In some instances there may be multiple

residuals with minimum values. In such cases, given an ordered physical system model

set, the switching algorithm indicates the physical system model Pp with minimal index

p, having the minimal residual Rp[k] value at sample k. An additional consideration

when implementing a switching algorithm is the presence of disturbances, w0, which

might cause the algorithm to switch rapidly between controllers, leading to instability.

Liberzon et al. [77] showed the effect of a fast switching sequence and that it could

make a stable system into an unstable system. To avoid this fast switching effect, a

2Equation 26 in algorithm-1 and equation 29 in algorithm-2


delay operator, D can be introduced. This delay operator assigns to every physical

system model, Pp, 1 6 p 6 N , a minimum delay that has to elapse before q(k) is allowed

to switch, i.e.

q(k) =

qf (k) if k − ks(k) > 4(q(ks(k)))

q(ks(k)) else(2.35)

where q(k) is the delayed form of the free switching signal, qf (k), and ks(k) returns the

sample at which the last switch occurred.

2.5.3 Uncertainty and physical system model set selection

Uncertainty of a physical system can be represented by uncertainty set U which contains

the physical system models representing the uncertainty. A key question in MMAC is

how the uncertainty set, U, should be sampled (e.g. the number of models and their

distribution) to produce a plant model set, ∆s = P1, P2, .....PN where N is the number

of physical system models, that provides robust stabilisation for all possible Pp ∈ U . For

xbP,C

bP,C

U𝑥 ∈ Δ𝑠

xP2 P1

Figure 2.6: Uncertainty (U) and an example sampling that produces ∆s(Source [2])

example, in Figure 2.6 observe that the elements in ∆s, together with the robust stability

margin, bP,C , specify a cover for the uncertainty, as illustrated by the discs centred on

the plant models. A key result established in the development of EMMSAC is that

gain bounds and robust stability margins do not scale with the size of the plant model

set, i.e. ∆s is allowed to be as large as required (within computational limits) without

weakening the bounds on the gain from the external disturbances, w0, to the internal

signals, w2. Instead, the gain bound is dependent on the complexity of U as defined

by the cover (e.g. see [21]). This challenges previous results (e.g. see [72]) that the

gain bounds scale with the number of elements in the physical system model set, which

led to the belief that the size of the physical system model set should be minimised.

Therefore the designer has freedom to select a ∆s that, given a desired robust stability


margin bP,C , forms a cover for U . One possible method for selecting such a physical

system model set is to use knowledge of the probability distribution of the uncertain

parameters associated with Pp. This will potentially lead to a nonlinear distribution of

physical system models within ∆s, with higher density regions representing the locations

where the true physical system is more likely to exist.

To conclude, note that, given sufficient computational resource, it is always possible to

implement an EMMSAC design. If the plant Pp ∈ U is not stabilised by the resulting

algorithm then, as long as a finite cover exists, this can be resolved by increasing the

density of the physical system model set. Furthermore, under certain conditions that are

dependent on the magnitude of the disturbances (e.g. in noisy environments) a static

plant model set will provide tighter gain bounds than a dynamic physical system model

set.

2.6 Applications of MMAE/MMAC

Due to the advantages associated with an MMAE/MMAC-based algorithm (discussed in

section 2.4.3 above), many researchers are attempting to use it for various CPS applica-

tions to improve performance in the presence of uncertainties [78]. For example, MMAE

was used for inertial navigation during Mars entry to accurately estimate position and

velocity states [25]. Khan et al. [26] presented the use of MMAC to avoid human in-

tervention by automatically tuning a proportional integral controller which controlled

an atomic force microscopic vertical loop. Brend et al. [27] provided the feasibility of

multiple-model switched adaptive control to regulate functional electrical stimulation

for upper limb stroke rehabilitation. Here, a general MMAC scheme was developed by

analysing experimental data taken from a sample of the population (sample X1), and

using it to construct a model set. They showed that the resulting controller could be

applied to multiple participants (sample X2) with limited prior identification and no

visible degradation in performance. Statistical analysis of the acquired data showed

that the ability to switch between controllers resulted in improved tracking performance

compared with more conventional non-switched methods.

Control of a high-speed train is often a challenging task, with their uncertain constants

and time-variant parameters such as masses of cars, elastic and damping coefficients

of buffers between cars, coefficients of rolling resistance and air drag, and slopes and

curvatures of railway lines. Recently, Zhou et al. [38] studied the feasibility of MMAC

in controlling a high-speed train in the presence of such uncertainties. They showed

that good performance could achieved with multiple controllers in tracking errors, in-

train forces and input signals, which benefit the reliability and safety of high-speed train

operations.


Freeman et al. [29] developed a rigorous adaptive framework that provides comprehen-

sive robustness guarantees for a general class of iterative learning control (ILC) algo-

rithms, called estimation based multiple model ILC (EMMILC). It was used for stroke

rehabilitation to precisely assist patients voluntary completion of functional tasks [30].

Rolls-Royce Corporation’s research team proposed a MMAE-based closed loop control

for gas turbine engines that satisfied both performance and stability requirements, and

validated it through simulations. Here, target performance was to maintain the output

power at the level required in the presence of disturbances and uncertainties [39].

MMAE is also used in fault detection and isolation (FDI) which plays a critical role

in enhancing the safety and reliability, and reducing the operating costs, of CPS ap-

plications. Cyber-physical systems are often complex structures and harsh operating

environments make the interpretation of the available information difficult. Therefore,

achieving high reliability in the FDI is a challenging problem. Faults may occur with

various degrees of severity at various locations, and numerous fault scenarios are thus

possible. To deal with such problems, the introduction of analytical redundancy has

become common and is considered more cost-effective than hardware redundancy. With

the increase of digital computational power, more sophisticated approaches such as the

use of models has become possible, thereby applicability of MMAE-based FDI is en-

hanced. For example, Ali et al. [32, 33] explored the use Kalman filter-based MMAE to

identify fault positions and fault types in an HVDC transmission system. Robustness of

the five model based MMAE algorithm in the presence of disturbances and unmodelled

dynamics was demonstrated using synthetic data from high fidelity simulations as well

as field data from a real HVDC transmission system.

Sing et al. [34] proposed a MMAE-based fault diagnosis of Li-Ion batteries. A bank of

Kalman filters were used to estimate the states of the fault models while considering the

noise. Fault scenarios of over charge and over discharge were created using two models

in MMAE and simulated to show the effectiveness of the technique. Simulation results

showed that the MMAE algorithm was able to detect the battery faults in real-time, thus

providing an effective way of diagnosing Li-Ion battery failure. In addition, some recent

studies used MMAE to estimate the accurate state of charge of batteries [35, 36, 37]. A

NASA research group has explored the use of MMAE for fault detection and isolation

in aircraft gas turbine engine sensors and actuators [79]. Afshin et al. [80] proposed

fault diagnosis based on a bank of Kalman filters for DC-DC boost converters using

time-averaging models. In this work, a two model based MMAE used to identify the

variations in capacitance and inductance of DC-DC boost converter.

A procedure for system faults identification was developed using MMAE techniques for

a nuclear power plant (generic pressurised water Reactor simulator) [40]. The system

models were obtained using system identification techniques for a specific set of fault

conditions. This technique used sensor measurements from the simulation to identify


appropriate parameters for the system models The MMAE algorithm was then used to

identify similar faults using the identified model. This combination of model-based, and

data-driven, techniques can ultimately be used to create robust fault models that take

advantage of both the models created during the design and validation process, and real

plant data.

Most of the works mentioned were validated in simulations, and real-time validation

on resource-constrained platforms has yet be addressed. It can be seen that MMAE

has numerous real-time applications, but its full potential in resource-constrained CPS

applications with fast dynamics can be achieved only when custom dedicated hardware

is available to run high complexity MMAE.

2.7 Boost Converter Accurate Mathematical Model

This section provides the details about the power electronic application boost converter

which is used to validate LTV model identification architecture. The accurate circuit

diagram DC−DC boost converter shown in Figure 2.7 is a converter that increases the

(typically uncontrolled) dc input voltage Vin(t) to a higher (controlled) dc output volt-

age Vo(t). The converter consists of two power semiconductors the controllable switch

S (MOSFET) with switching on resistance RDS , and the diode D1 with conduction

resistance RD. The inductor L with the internal resistor RL is used to store and deliver

energy depending on the operating mode of the converter, while the filter capacitor Co

equivalent series resistor (ESR) of RC is connected in parallel with the load resistor Rload

so, to ensure a constant output voltage during steady-state operation of the converter.

Vin

L

CRload

SD1

PWM

RL RDRc

RDS

Figure 2.7: Accurate model of boost converter

Setting inductor current iL(t) and capacitor voltage VC(t) as the state variables, the

system state the function is derived as follows. When the switch S is ON (S = 1, shown

in Figure 2.8), energy is stored in the inductor L and the inductor current iL(t) increases.

This Switch is operated by applying a pulse width modulated signal (PWM). When the

switch S is OFF (S = 0, shown in Figure 2.9), the inductor is connected to the output

and energy is released through it to the load, resulting in a decreasing iL(t). During the


switch, S is ON (S = 1) the capacitor is discharged to supply energy to load, with state

equations defined as

Vin

L

CRload

RL Rc

RDS

S=1

Figure 2.8: Boost converter circuit in switch is closed mode

LdiL(t)

dt= −iL(t)(RL +RDS) + Vin (2.36)

CdVC(t)

dt= − VC(t)

Rload +RC(2.37)

(2.38)

Vin

L

CRload

D1RL RDRc

S=0

Figure 2.9: Boost converter circuit in switch is open mode

During the switching off period, the charging current of the capacitor is iL(t)−VO(t)/R,

the system state function is

LdiL(t)

dt= (RL +RD +

RloadRCR+RC

)iL(t)− RloadRload +RC

VC(t) + Vin − VD

CdVC(t)

dt=

RloadRload +RC

iL(t)− VC(t)

Rload +RC

It is to be noted that, boost converter output voltage is directly proportional to duty

cycle (D) of PWM signal [81].

2.7.1 Boost converter operating modes

The last section was presented basic functionality of the boost converter. In this sub-

section describes the operating modes of boost converter based on inductor current and


switching operation.

2.7.1.1 Continuous conduction mode (CCM)

If the boost converter inductor current is continuous, meaning that it is always greater

than zero, then it is called continuous-current operation (shown in Figure 2.10). A

boost converter designed for the continuous-current operation will have an inductor

value greater than Lmin. It is defined as follows (proof can be seen in [81]). Where f is

boost converter operating frequency, D is the duty cycle.

ON OFF ON OFF

Region-1 Region-2 Region-1 Region-2

Regi

on-3

Regi

on-3

t

t

IL

PWM

Figure 2.10: Boost converter inductor current with respect to the PWM

Lmin >D(1−D)2Rload

2f(2.39)

2.7.1.2 Discontinuous conduction mode (DCM)

When the average value of the output current is low (high R) and or the switching

frequency f is low, the converter may enter the discontinuous conduction mode. In

the DCM, the inductor current is zero during a portion of the switching period. State


equations defined as

diL(t)

dt= 0

CdVC(t)

dt= − VC(t)

Rload +RC

Therefore boost converter operation, completely depend on the inductor current. As

mentioned at beginning of Section 2.7, inductor current iL(t) changes (increasing or

decreasing) depend on the switch S position. The inductor current variation with respect

to switch S (PWM) position is shown in Figure 2.10, the operation of the boost converter

is divided into three regions. During region-one the switch is on and the inductor current

increases and it considered as CCM mode. In region-two the switch is off and inductor

current decreases, maintaining iL(t) > 0. Finally, in the third region, the switch is off

and inductor current iL(t) = 0. If region 3 present then the inductor current reaches

zero and is in DCM mode, else if iL(t) > 0 for all t > 0, then region three must decrease

and the converter is in CCM mode. Next section discusses about various computing

platforms.

2.8 Computing Platforms

Previous section (2.6) explained the various advantages and applications of MMAE

algorithms, which suggested the applicability of the algorithm to real-time resource-

constrained applications. The choice of hardware platform to develop such a MMAE

algorithm has significant impact on execution time, hardware resources, and power con-

sumption. This section addresses the most-used computing platforms in real-time com-

putation, including the general purpose processing unit, the microcontroller, the graphics

processing unit, the digital signal processing unit, and field programmable gated arrays

(FPGA). It discusses their applicability for implementing MMAE architecture.

2.8.1 General purpose Central Processing Unit

The first silicon integrated circuit was invented by Robert Noyce in 1959 [82]. Since

then the rate of performance imporvement in computing platforms has been incredible.

Moore predicted that the number of transistors in a given silicon area would double every

18 months [83] which still holds today. The dominant architecture for general-purpose

computing has been the x86 instruction set, first realised on the 16-bit Intel 8086 in

1978, with the 32-bit introduced on the 80836 in 1985, and the 64-bit in the mid 1990s.

A general purpose CPU architecture mainly consists of the arithmetic unit, control

unit I/O. ALU performs arithmetic and logic operations on integer binary numbers. A


Control unit extracts instructions from memory, and decodes them to direct operation

of the ALU and memory. The CPU is able access data from main memory via the cache.

All these units execute in a sequential manner to perform the given task. To achieve

higher speeds, these units may be executed in a pipeline manner. A basic instruction

has a five-stage pipeline; these are fetching an instruction from the instruction memory,

decoding it, executing it, storing the result in memory, and updating the local registers.

However, as the CMOS technology shrank, power dissipation became a limiting factor

[84]. Dynamic power dissipation is defined as P = C.V 2.f2 where C is capacitance of

transistor, V is supply voltage and f is operating frequency [85]. As the compenents get

smaller, supply voltage and capacitance is scaled down, so the clock frequency had to stop

scaling to reduce power dissipation. To meet the performance requirements, the general

approach has been to design multicore chips consisting of two or more microprocessors in

the same die, attached to a shared memory bus. These are called multicore preprocessors.

These platforms are limited to offline computing due to their unpredictable execution

time. Cerati et al. [86, 87] have explored the implementation of parallel Kalman filters

on a Xeon Phi multicore processor for offline tracking detector systems with application

to the Large Hadron Collider.

2.8.2 Microcontrollers

The microcontroller is a single chip which includes the processor, memory, ADC/DAC,

and programmable peripherals. By using these convertors, sensors and actuators can

be directly connected to the microcontroller. Due to limited processing capability and

memory, it could perform one or a few dedicated tasks efficiently, with lower power

consumption than the equivalent CPU. Microcontrollers are typically useful for robotic

embedded applications which run on simple algorithms. For example, model predic-

tive control (MPC) algorithms were implemented using the STM32 microcontroller by

[88], while optimal H-infinity algorithms were implemented using low-cost mechatronic

applications [89].

2.8.3 Digital signal processors

Digital signal processors (DSP) have a multiply-accumulate unit to perform multiplica-

tion and addition in one cycle, allowing for extended precision in the intermediate result.

Generally, DSPs are useful for filtering the stream of data operations like in equation

2.40.

y[n] =

N−1∑k=0

ckx[n− k] (2.40)


DSPs are based on a Harvard architecture, i.e. they have different instruction and data

buses, and they support simultaneous fetching of several data items from memory. DSPs

are complex instruction set (CISC) machines. An example of one complex instruction

could be: fetch two pieces of data and put them in registers A and B, multiply them

together and add them to the contents of register C, store the result in the same register

and increment the pointers to fetch the next data. Details of DSP architectures are given

in [90]. Many control applications have used DSPs due to their low power consumption,

high computational efficiency when handling certain kinds of computation, and lack of

hardware features that introduce timing uncertainty.

A few attempts have recently been made to implement EMMSAC on DSP platform, as

discussed below.

1. Khan et al. [26] used a DSP platform and EMMSAC to develop an automated

online proportional integral (PI) controller tuning procedure for an atomic force

microscope (AFM). The AFM input-output signals were constantly observed to

determine the closest second-order linear model using 121 deterministic Kalman

filters sequentially. The scan rate was 0.5Hz for 27 minutes. Once the best match

physical system had been determined, a predetermined controller, corresponding to

that physical system model, was switched into the AFM control loop [26]. Through

this work authors proven that EMMSAC provides a promising solution for AFM

control. This work was limited by the number of models, and its execution time

of 27 minutes was far too slow for practical use.

2. Brend et al. [27, 20] investigated the feasibility of EMMSAC for stroke rehabilita-

tion and suggested its extension to the non-isometric case with movement control.

FES is a second-order system comprising both non-linear and time-varying ele-

ments, so EMMSAC was extended to a non-linear time-varying setting. They

implemented two dynamic models with 1000 static models for the non-linearity.

The static part was realised with low computational overhead in the MMAE on

the DSP platform. The sampling rate was 160Hz and the computations operated

in real-time. However, to extend this work to the elderly, because they have re-

duced muscle tone, a more representative set of physical system models for each

participant was needed, and this was beyond the availability of the resources on

the DSP platform.

In both cases, the results given have shown “proof of concept” only: EMMSAC has

the potential, but these can only be fully realised for these applications with parallel

real-time implementation. Both these applications [26, 27] have implemented a limited

number of models on their DSP platforms. It can be concluded that the DSP can be used

to implement very few models if they have to meet critical deadlines. However, a larger

number of models can be implemented only when there is no deadline on execution time.


Moreover, AFM controller implementation underlying challenges such as reduction in

computational time (high-speed hardware execution) and implementation of the higher

number of models for full beam AFM are yet to be addressed. FES for rehabilitation

is progressing towards wearable, low-cost technology, which naturally requires smaller,

low power hardware and greater number of models (since ideally, the same model set

needs to work with as wide a set of patients as possible). This is clearly motivating us

to design custom hardware architecture of the MMAE to implement the larger number

of models.

2.8.4 Graphics processing units

Graphics processing units (GPUs) are designed to provide the high efficiency necessary

to render graphics applications. In general, GPUs have fixed architectures with up to

several hundred processing units that can perform operations in parallel, and execute the

same instruction on different data in a single instruction multiple data (SIMD) fashion.

To achieve maximum throughput, several hundreds or even thousands of independent

threads are available at all times. GPUs have several additional properties that make

them problematic for embedded applications. Firstly, the order of execution is scheduled

by hardware on-the-fly, which given the performance sensitivity of the architecture leads

to very unpredictable timing. Secondly, a GPGPU cannot be a standalone component.

It requires an additional general-purpose host to transfer data and start execution,

hence the cost and, more importantly, the power requirements of the system are very

high, typically well above 100 Watts. Recently, a plasma control system for Columbia’s

HBT-EP Tokamak [91], and the model predictive control algorithm for controlling a

crystallizer unit operation [92], have been implemented on a GPU. However, due to the

higher power requirement, these processors are not suitable for achieving the goal of

extending to on-the-fly decision-making to real-time resource-constrained applications,

hence they will not be directly considered in the remainder of this thesis.

2.8.5 Field-programmable gate arrays

In 1984, Xilinx developed the first field-programmable gate-arrays (FPGAs). This was

based on the CMOS technology, and SRAM cells used for configuration purpose. It

mainly consists of an array of configurable logic blocks (CLB), as shown in Figure 2.11.

The CLBs are arranged in matrix form and these are interconnected using the SRAM

cells. CLBs are designed by using look-up tables LUTs and FFs as shown in Figure 2.12.

LUTs are useful for forming a combinational logic function, shift registers and memory.

FFs are useful for designing sequential logic. For example, LUT was required to perform

the function y Equation 2.41 [3].

y = (a&b)||!c (2.41)


Figure 2.11: FPGA fabric structure (Source [3])

Figure 2.12: FPGA configurable logic block structure (Source [3])

Function y is doing an OR operation on a AND b with !c. This could be designed in way

shown in Figure 2.13. FPGAs also have DSP units to perform multiplication operations

Figure 2.13: Execution of function y = (a&b)||!c on CLB (Source [3])

efficiently with the lesser area. Overall, an FPGA allows the user to implement compu-

tational units according to the requirements of the algorithm, unlike CPUs which have

a fixed pipeline architecture. By hardwiring a particular algorithm into an FPGA, the


highest level of customisability can be achieved. Moreover, by using dedicated hardware

architecture for executing only one algorithm, redundant speculative circuits burning

power unnecessarily can avoided completely.

Because the FPGA be be easily reconfigured, non-recurring engineering costs are smaller

than the application-specific integrated circuit, while FPGA is preferred for smaller pro-

duction requirements. The leading FPGA suppliers are Xilinx, Altera, and Microsemi.

Hardware design flows rely on slow error-prone tools that require low-level hardware

expertise. FPGAs are traditionally programmed using hardware description languages

such as VHDL or Verilog [93]. FPGAs are also used in signal processing and healthcare

applications to meet resource constraints and power requirements [94].

Recent advances in the fields of machine learning, artificial intelligence, and computer

vision have tremendously increased the demand for high-speed hardware accelerators.

This has resulted in the FPGA becoming the primary choice in the design of dedicated

hardware for deep neural networks (DNNs) [95, 96, 97], and stereo vision [98, 99, 100].

to meet real time performance requirements. Global communication networks are one of

the major application areas of FPGAs due to their high throughput requirements [101].

They are also used for demanding radar, and have become common for implementing

simple control loops with very tight real-time requirements [102].

In general, FPGA enables particular algorithms to be mapped onto hardware, and thus

can achieve maximal computational efficiency. Moreover, hardware implementations

have cycle-accurate predictable timing, which is a significant advantage for guaranteeing

tight real-time deadlines. Thus, FPGAs are the most suitable platform for optimal

decision-making and control, in resource-constrained applications [103].

Floating-point operations remain expensive to implement in FPGAs, mainly because

there is no hard support in the FPGA architecture to facilitate the normalisation and

de-normalisation operations required before and after every floating-point addition or

subtraction [104]. Therefore, this thesis considers only fixed-point implementation using

the Xilinx Virtex ultra scale plus FPGA [105], programmed with a Vivado-2018.2 tool

[106].

2.9 Discussion

This chapter presented an overview of classical adaptive control algorithms and mul-

tiple model adaptive control literature and its historical developments. The features

associated with MMAC algorithms were given in detail. The recently proposed estima-

tion based multiple model switched adaptive control algorithm was discussed in detail.

Details regarding the estimation and switching processes were provided, with specific

focus given to the Kalman filter implementation as the estimator. MMAE-based CPS


applications were also addressed. This concluded that MMAE based algorithms could

be applied to real-time resource-constrained applications.

An insight was given into various hardware implementation platforms, such as CPUs,

DSPs, GPUs, and FPGAs. These limitations of CPU and DSP platforms for imple-

menting MMAE algorithms were outlined. The advantages of FPGA platforms over

other platforms for implementing the multiple model adaptive estimation algorithms

were addressed.

The literature review of control algorithms suggested that MMAE should be chosen as

the model identification scheme for both LTI and LTV systems. The shortcomings of

the CPU, microcontroller, DSP, and GPUs for meeting real-time deadlines and resource

requirements were highlighted To overcome these limitations, the alternative solution

identified was direct mapping of MMAE model identification algorithms onto an FPGA.

Chapter 3

Hardware Architecture for Linear

Time Invariant System Model

Identification

The literature review presented in the last chapter motivated us to design a hardware

architecture for MMAE based model identification algorithm. This chapter considers a

hardware architecture for the implementation of the MMAE based LTI model identi-

fication, with an objective to demonstrate architecture which can implement the large

number of filters whilst meeting real time constraints. As discussed in chapter 2, EMM-

SAC comprises two sub-blocks, one is model identification using MMAE and the second

is the controller selection from a bank of controllers. MMAE is comprise a bank of deter-

ministic Kalman filters and forms the most computationally intensive part of EMMSAC.

Therefore, this chapter is to investigate the hardware architecture for MMAE based LTI

model identification. The FPGA implementation is illustrated by a simple autonomous

vehicle application. This example is not chosen to be potentially realistic we operate on

far faster timescales for switching than the realistic but, the purpose of this chapter and

the example developed, illustrate the methodology and implementation mainly to a fully

realistic applied example in power electronics application later chapter. This application

serves as a simple illustration of an example as a precursor to our main power electronics

application considered in the later chapter of this thesis.

To maximize the efficiency of the implementation and there to permit the maximum

number of filters, the complexity of the implementation is carefully addressed. The

proposed architecture is developed with reused multiplier units, shifting operations and

fixed point operations to compute Kalman gain and the Xpupdate and Σp

update equations

for each model in the filter banks of the MMAE algorithm. The proposed architecture

is implemented using FPGA for 16, 32, 64 filter banks with an autonomous vehicle

application.

39

40Chapter 3 Hardware Architecture for Linear Time Invariant System Model

Identification

It is shown that theoretically up to 78% reduction in multiplications is possible by using

the reusable multiplier architecture and fixed computations, which translates to the

reduction of 39% LUTs, 13% FFs, 27% DSPs, and 43% power reduction when compared

with the directly mapped architecture (without reusable multipliers and multiplications)

at the 100MHz operating frequency. Furthermore, the proposed architecture is able to

identify an accurate model of auto-mobile application within 510ns, in the presence of

external disturbances and abrupt changes.

The reminder of this chapter as organised in the following manner. Section 3.1 provides

the details of the multiplication reduction in each equation of MMAE algorithm pre-

sented in Chapter 2 and also discuss the proposed architecture and Section 3.2 validates

the architecture using data generated from a Matlab simulator and discusses the exper-

imental results, compares performance, in terms of time, resource utilization and power

consumption of the proposed architecture with directly mapped architecture. Finally,

Section 3.3 provides the summary of the chapter. Material from this chapter has also

been published in IEEE TCAS-II as Charan et. al [107].

3.1 Proposed Architecture

The block diagram of the proposed architecture is shown in Figure 3.1, physical system

(Pp∗) represented as discrete-time linear time-invariant system in the form

xp(k + 1) = Apx(k) +Bpu1(k) (3.1)

yp1(k) = Hpxp(k), k ∈ N (3.2)

Where ( Ap, Bp, Hp ) ∈ Rnxn x Rnxm x Roxn are state-space matrices, state x is ∈Rnxm, u2 is input and y2 is measured output signal, (u2, y2)T are the measured signals,

(u0, y0)T are the external disturbances and (u1, y1)T are the original signals at the input

and output side of a physical system (Pp∗) respectively. Cyber-component comprises

the hardware architecture of the MMAE based model identification algorithm. The

Cyber-component processes the input signals (u2, y2)T from the physical component and

processes these signals for identifying the model of the physical system. As we discussed

applications of the MMAE in Section 2.6, MMAE is used for inertial navigation during

Mars entry to accurately estimate position and velocity states [25, 108], therefore in

this chapter auto-mobile vehicle position and velocity estimation applications is used for

validating proposed architecture. The physical system auto-mobile vehicle state space

model is described by the following equations

Pk+1 = Pk + T.Vk + 1/2.T 2.uk + 1/2.T 2.De.Vk + η1 (3.3)

Vk+1 = Vk + T.uk + T.De.Vk + η2 (3.4)

Chapter 3 Hardware Architecture for Linear Time Invariant System ModelIdentification 41

Physical Component

Cyber Component

Residuals-N

Residuals-2

Innovation

Innovation

Innovation

PhysicalPlant (Pp*)

𝑢0 𝑦0

++− −

Model-1 (DKF-1) Residuals-1

𝑢2 𝑢1 𝑦1 𝑦2

ComparatorAnd Model Selection

Output

Model-2 (DKF-2)

Model-N (DKF-N)

Filter Bank

Figure 3.1: Proposed architecture for MMAE based LTI model identification.Each model represents the deterministic Kalman filter with a particular statespace matrices. Here (u2, y2)T are the measured signals, (u0, y0)T are the exter-nal disturbances and (u1, y1)T are the original signals at the input and outputsignals of a physical system (Pp∗) respectively. The cyber component designalso corresponds to the MMAE part in Figure 1.2 shown in chapter 1

respectively where P = position, V = velocity, k = time, T = time constant uk=

Input acceleration, De= External disturbances. x(k) = [Pk, Vk]T , Hp = [1, 0] uk = u2,

u1 = u0 − u2 u0 = η2, y0 = η1, y2 = y0 − y1.

Ap =

[1 T + T 2

2 .De

0 1 + T.De

]

Bp =

[T 2

2

T

]

The vector x contains all of the information about the present state of the system, but

we cannot measure x directly. Instead, we measure y2, which is a function of x that is

corrupted by the noise. The output information y2 used to obtain an estimate of x, but

we cannot necessarily take the information from y2 at face value because it is corrupted

by noise. We can use the information that it presents to a certain extent, but we cannot

afford to grant it our total trust. In general, systems are perturbed by uncertainties due

to gusts of wind, potholes, and other unfortunate realities, which is represented as De

as shown in Figure 3.2.


Identification

x=[pk, vk]T

+De

-De

Down hill

Up hill

Figure 3.2: Auto-mobile vehicle with uncertainties De

3.1.1 Cyber-Component

Model identification is performed on Pp∗ for robust estimation of Pp. In this regard, each

model runs recursively on computationally intensive Deterministic Kalman Filter (DKF)

in the presence of external disturbances (as discussed in Chapter 2 from equation 2.26 to

2.31). Thus the complete model identification comprises of N -DKF modules where each

DKF processes (u2, y2)T at every time instance to provide an estimated outcome. Then

the difference between the estimated and the measured output is computed (known as

Innovation equation 2.26) at every time instance for each model-physical system. Next

step is the computation of the weighted sum of m-a number of such innovations per

each model is known as Residuals (equation 2.33). The minimum Residual among

such N model represents the best match of the physical system Pp (known as Model

Selection). For ease of understanding, the aforementioned algorithm is shown in the form

of pseudo-code in Algorithm− 1. The inputs of DKF module are Ap(i), Bp(i), Hp(i)

with initial conditions Xpestimate(0) (state variables), Σp

estimate(0) (covariance) and y2(i),

u2(i). The DKF module computes innovation, Kalman gain, update and estimation

of the state variable (x), covariance Σp recursively (same as equations 2.26-2.31). As

shown in Algorithm−1 from line 1-22, all these computations involve in 32-bit matrices

multiplications, inversion, additions and subtractions.

3.1.2 Multiplications reduction in Algorithm− 1

A reduction of multiplications in the above steps is achieved as follows:

1. The first equation involves multiplication matrices Hp and Xpestimate, since Hp is

constant, it can be performed by shifting operations. For example, considering


Algorithm 1 model adaptive estimation MMAE based model identification

1: Kalman Filter:

2: INPUT: State Space Matrices of LTI System Ap(i), Bp(i), Hp(i), Xpestimate(0),

Σpestimate(0), u2(i), y2(i)

3: for i = 1, i < final time, i = i+ 1 do

4: do in parallel

5: for p =1 to N do

6: Sub-module 1

7: Ip(i) = y2(i)−Hp(i).Xpestimate(i)

8: abs(Ip(i))

9: Sub-module 2

10: Sp(i) = Hp(i).Σp(i).Hp(i)T

11: S−1(i) = scale/Sp(i)

12: Call Residuals

13: Kalman Gain:

14: Sub-module 3

15: Kp(i) = Σp(i).Hp(i)T .S−1(i)

16: Sub-module 4

17: Xpupdate(i) = Xp

estimate(i) +Kp(i).Ip(i)/scale

18: Sub-module 5

19: Σpupdate(i) = Σp(i)−Kp(i).Hp(i).Σp(i)/scale

20: Sub-module 6

21: Xpestimate(i) = Ap(i).Xp

update(i) +Bp(i).u2

22: Sub-module 7

23: Σ(P )estimate(i) = Ap(i).Σpupdate(i).A

pT (i) +Bp(i).BpT (i)

24: end for

25: Residuals:

26: Rpl (i) =

∑Tt=T−l abs(I

p(i))[HpΣp(i)HpT +1]−1 , T ≥ l27: end parallel

28: Model Selection:

29: for j =1 to N do

30: qf (k) = argmin16p6N

Rpl [k],∀k ∈ N

31: end for

32: end for

33: OUTPUT: Identified Model

h1x1 where h1 = 13, multiplication can be removed by expressing the equation as

h1x1 = 13x1 = (8x1) + (4x1) + (1x1). (3.5)

= 23x1 + 22x1 + 20x1 (3.6)

= ls(x1, 3) + ls(x1, 2) + x1 (3.7)

where ls(a, b) signifies a left-shifted by b bits. In this example, the multiplier is


Identification

replaced by just three adders and two shifters. These shifters can be implemented

by simple hardware wiring. Thereby in this architecture n multiplications in each

DKF.

2. In the second sub-module, Sp are computed. This consists of the multiplication of

three matrices Hp.Σp.HpT . This is also computed by reusing the same structure

discussed in the first submodule and explained further using equation 3.7.

3. Similarly in the second equation Sp = Hp.Σp.HpT also eliminated the n2 multipli-

cations. The Kalman gain is computed by Σp, Hp and S−1, these variables change

in every iteration of DKF, therefore, it requires n multipliers.

4. The Xpupdate involves the multiplication of Kalman gain and Innovation, to com-

pute this the architecture requires n2 number of multipliers, here by reusing the

multipliers, n number of multipliers are eliminated.

5. The next equation Σpupdate involves the multiplication of the Kalman gain, Hp and

Σpupdate, except Hp remaining variables changes on the fly, we need n2 multipliers.

However, by reusing multipliers units, th number of multipliers reduced to n2−n.

6. The next equation Xpestimate depends on multiplication Ap, Σp and Bp, u2, since

Ap and Bp are constant we performed by shifting operation on there by this ar-

chitecture eliminated the n2 + n multipliers. The Σpestimate mainly depend on

computation of ApΣpApT since Ap is constant, this computation is performed by

using shifting operations and reduced n2 + n multipliers.

7. The term BpBpT conferred in the Σpestimate is pre-computed and reused in ev-

ery iteration of DKF, thereby proposed architecture able to reduce n2 number of

multipliers.

8. The term S−1 computation requires a division that increases the hardware com-

plexity. For instance, in a Xilinx FPGA, fixed-point addition takes one cycle,

whereas a single precision floating-point adder would require 14 cycles while using

one order of magnitude more resources for the same number of bits [109]. There-

fore, here we have used the LUT based method. However, to retain the precision

of this LUT based division, up-scaled the numerator first and then use the de-

nominator as the address to fetch the appropriate data from the LUT. The scaling

factor was decided based on the empirical simulations running for various scaling

factors and the error rates are shown in Figure 3.3. For the scaling factor 210, 211,

212, 213, and 214 the error rates 7.78, 6.12, 6.36, 5.59, and 5.58 for mode identifi-

cation respectively observed. As the scaling factor increases, the size of LUT also

increases.

Overall the total number of multiplications involved in MMAE algorithm is equal to the

(1 + 4n + 3n2 + 2n3)N where N , n represents the total number of models and states


0

1

2

3

4

5

6

7

8

1 2 3 4 5210 211 212 213 214

erro

r %

Scaling factor

Figure 3.3: Error rate comparison for various scaling factors

respectively and by using shifting operation and pre-computation we reduced them down

to (2n+n2)N multiplications. MMAE hardware architecture have many design choices

that can be made, typically to trade off time (throughput, latency) against area by using

the number of multipliers ranging from minimum n to maximum (2n + n2). However,

due to the data dependency between the equations mentioned in Table 3.1, choosing

the maximum (2n + n2)N number of multipliers in architecture is not an ideal choice.

Therefore this architecture is proposed to compute maximum state-space elements in

Σpupdate (n2) in single clock cycle, for n = 2, Σp

update has four state-space elements. By

0

5000

10000

15000

20000

25000

30000

35000

40000

1 129 257 385 513 641 769 897

Nu

mb

er

of

mu

ltip

licat

ion

s

Number of models

No. of multiplications in MMAE

Reduced No. of multiplications in the proposed hardware architecture

No. of multipliers used in the proposed hardware architecture

Figure 3.4: Multiplications reduction using the proposed hardware architecture:comparison for 1 to 64 models (Note: Number of multipliers used in the proposedarchitecture are even less than the number of multiplications required)

using reusable multipliers the proposed architecture reduced the number of multipliers

required to use on hardware architecture from (2n + n2)N to n2N as shown in Figure

3.4. In this hardware architecture for N = 64 number of models with n = 2, we have

used only 256 multipliers whereas directly mapped architecture used 512 multipliers.


Identification

The detailed comparison of the number of multiplications involved in MMAE algorithm

and proposed hardware architecture is given in Table 3.1. Most of the multiplications

conferred in DKF. This is evident that N -DKF modules contains a significant number

of multiplications and this chapter proposed an architecture to eliminate most of these.

Table 3.1: Comparison between the MMAE algorithm (Shown in algorithm-1) and proposed hardware modules in terms of the number of multiplications.Where sub-module 1-7 are associated with DKF, N= Number of models, n=number of states to be estimated, No. of mul=Number of multiplications,H.W.A= Hardware architecture

Sub-Module No. of mul No. of mul inin MMAE algorithm proposed H.W.A

(1) Innovation (Ip) Nn 0

(2) Sp Nn2 0

(3) Kalman Gain (Kp) Nn2 Nn

(4) Xpupdate Nn Nn

(5) Σpupdate Nn3 Nn2

(6) Xpestimate N(n2 + n) 0

(7) Σpestimate N(2n3 + n2) 0

(8) Residuals (Rp) N 0

Total (1 + 3n+ 4n2 + 3n3)N (2n+ n2)N

The hardware mapping of the MMAE algorithm is shown in Figure 3.5a. It comprises of

two modules one containing DKF (line no: 1-24 in algorithm 1) with Innovation com-

putation (line no: 7 in algorithm 1) and the other one involving Residual computation

(line no: 26 in algorithm 1) along with model selection (line no: 30 in algorithm 1) as

shown in Figure 3.5b. These modules are pipelined to achieve higher throughput. The

controller block is designed to monitor the data flow between the intra sub-modules of

module-1 and module-2.

Figure 3.5: (a) Proposed multiple model estimation based model identificationarchitecture: deterministic Kalman filter architecture, (b) residuals, argmin,comparator and model selection


3.1.3 Deterministic Kalman Filter (DKF)

To explain DKF equations in algorithm 1 for computing one of the variables of both

Xpestimate and Σp

estimate matrices, the equations to hardware mapping is shown in Figure

3.6. During the first iteration it takes Xpestimate(0), Σp

estimate(0) and y2(1) as input and

from the second iteration onwards it takes measured signal y2, the first iteration outputs

Xpestimate and Σp

estimate feedback to input. The detailed operation explained as follows.

1. The innovation equation (line−7 in algorithm−1 and equation 2.26 in chapter−2), it is computed by using shifting operation and subtracter, the output innovation

indicated as 5 in Figure 3.6. In parallel the term Sp is calculated by using the

shifting operations and its inverse is computed by using LUT.

2. By using a reusable multiplier, Kalman gain (2.27) is computed by sending S−1

and ΣpHpT as an input to the multiplier. It is also indicated as 13 in Figure 3.6.

The architecture for the reusable multiplier is shown in Figure 3.7.

Where a, b, c, d, e are the inputs of multiplexer (MUX) and c1, c2, c3, c4 are the

control bits to the MUX.

3. After computing Kalman gain, by using same multiplier, the term Kp ∗ Ip is

computed output of this indicated as 15a in Figure 3.6, outcome of this down-

scaled and added with Xpestimate to obtain the Xp

update (line− 17 in Algorithm−1 and equation 2.28 in chapter − 2), it also indicated as 15 in Figure 3.6.

4. In parallelKp and Σpestimate are multiplied and downscaled, subtracted from Σp

estimate

to obtain the Σpupdate (line−19 in algorithm−1 and equation 2.29 in chapter−2),

it also indicated as 17 in Figure 3.6.

5. The step ApXpupdate is computed by using shifting operations, in parallel u2B also

computed by using shifting operations and these terms are added to obtain the

Xpestimate (line − 21 in Algorithm − 1 and equation 2.30 in chapter − 2), it also

stored in the register to send as a feedback for next iteration. it is also indicated

as 19 in Figure 3.6.

6. In parallel Ap.Σpupdate.A

pT is computed by using shifting operation and added pre-

computed BpBpT to it, to obtain the Σpestimate (equation 2.31 in chapter-2 and line

number 23 in algorithm−1). These results are stored in registers for providing in-

put to DKF in the next iteration. In the similar fashion n2-Σpestimate and n-Xp

update

values are computed in single DKF for every iteration. Similarly, 64-DKF modules

were designed for each state-space matrices set Ap, Bp, Hp where 1 ≤ p ≤ 64.

The 64 absolute values of innovations are stored in a buffer and send to module-2

for selecting the appropriate model.


Identification

shift

𝑦2

mul1

Reg

abs

Regm

ul1

Kpg

HpT

Reg

mul1

Shift

Hp

>>

Xpupdate

+>>

∑pU

pdate

ApA

pT

+

Ap∑

p ApT

A

+

Bp

shift

u2

Xpestim

ate

shift

Reg

Reg

BBT

∑pestim

ate

Input to module 2

I p

∑pestim

ate

∑pestim

ate

Xpestim

ate

DIV

∑pestim

ate

Feedback to input

Feedback to input

Xpestim

ate

shift

HpT

shiftH

pHpT

shift

∑pestim

ate

519

21

17

13

6

9

15

8

Reg 15a

Figu

re3.6:

Determ

inistic

Kalm

an

filter

detailed

architectu

refor

comp

utin

gXpestim

ate

and

Σpestim

ate

recursively,

inp

aralleln

similar

arch

itectures

forN

mod

elsare

used

com

pu

teth

ep

arameters.

Th

enum

bers

correspon

dto

the

line

nu

mb

ersinAlgorith

m−

1


REG

*

a

bc

c3

c2c1

d1

m2

m3

m1

d

out

e

c4

Figure 3.7: Reusable multiplier architecture

Table 3.2: Reusable multiplier operation. Kp=Kalman gain,AI=abs(Innovation) and SM=Sub module OTM=Output to the sub-module

Inputs to multiplier Control BitsOTM

a b c d e c1 c2 c3 c4

S−1 - - ΣpHpT - 0 0 0 1 SM3

- - AI - Kp - 1 1 0 SM4

- HpΣp - - Kp 1 0 1 0 SM5

7. The architecture shown in Figure 3.5b was used for computing the residuals and

model selection (line no: 26 in algorithm-1). This module takes input (Innovation)

from the DKF module and computes the final model which is close to the physical

system. The operation of the residual sub-module is explained as follows.

8. Initially, innovations from N -DKF modules are forwarded to the N -residual sub-

modules (Figure 3.5b). Each residual sub-module stores these innovations in their

respective shift registers. At each clock cycle, these innovations are shifted their

location by one place. Once the shift registers filled by m innovations, it starts

the computation of residual. In this interval, the model selection block sends the

default identified model as 1 and after filling all the shift registers, each value in

the shift register multiplied with weights (w1, w2, w3) as shown in Figure 3.5b and

then added together for getting final residual. To reduce hardware complexity,

the weights w1, w2, w3 are chosen as multiples of two such that the residuals can

be computed just by left shifting the innovations and only considered a summa-

tion of innovations. This module comprises the shift register, adders and shifting

operations.

9. Subsequently, N -residuals are forwarded to argmin (Figure 3.5b) module for com-

puting the minimum location among all. This argmin sub-module is a pipelined

architecture with log2Nmax stages of comparators organized in tree structures.


Identification

3.2 Results and Discussion

3.2.1 Physical system data generation

Proposed architecture is considered 64 uncertainty levels such that Dexternal, ∈[−

31.3, 68.5], Noise ∈

[− 5.64, 6.05

]for validation and corresponding state space models

with matrices set Ap, Bp, Hp were generated where 1 ≤ p ≤ 64. Based on these models,

64 bank of DKFs are designed on the hardware by using the architecture discussed in

the above section. To obtain the original physical system data (y2 in Algorithm − 1),

we emulated using equation 3.2, by changing the uncertainty level randomly in equation

3.4 by adding external disturbances and noise changes every sample drawn from[−

5.64, 6.05]

for both η1 and η2 in the system.

3.2.2 Matlab implementation

To compare the performance of the proposed architecture with sequential execution

hardware platforms, algorithm 1 is also implemented in Matlab with a 64-bit floating-

point for performance comparison. It has taken 20sec time on an Intel Core i7-6700-

CPU @3.4GHz to run 64 models sequentially. Hence by the time of one DKF iteration

(0.3125sec) in MATLAB simulation, we can compute 4.46x106 DKF iterations on FPGA.

3.2.3 FPGA implementation

The proposed architecture has been coded in Verilog, synthesized using Xilinx′s Vivado

2017.4 and prototyped on Virtex ultra-scale plus FPGA (VCU118 evaluation platform

with xcvu9p Device). The block diagram of the experimental setup is shown in Figure

3.8 and FPGA was connected to the PC through the Xilinx platform JTAG Cable. The

design was programmed into the FPGA through the Vivado hardware manager. The

global system reset was given by an onboard push button (SW12[0]). Onboard clock

generator U122 Silicon Labs SI5335A-B03426-GM (CLK0A 300 MHz) is used in this

architecture. For the validation purpose of this prototype, we considered position and

velocity estimation models for autonomous auto-mobile is one of the major applications

in CPS. It is to be noted that the cyber component architecture shown in Figure 3.1

is implemented on FPGA. Matlab emulated data were stored in the BRAM of FPGA

and fed to the architecture at every clock cycle at a sampling rate of 70ns which acts

as a physical system. Xilinx Block memory generator IP was used to crate BRAM on

FPGA. The proposed architecture is designed using 32-bit word length and it was found

to be able to identify the physical system model by processing the system’s input and

output in the presence of external disturbances. Vivado integrated logic analyser (ILA)

was used for verifying the obtained results from the proposed architecture.


Figure 3.8: Experimental setup for the LTI model identification architecturevalidation

Table 3.3: Module wise breakdown of the FPGA resource utilization of theproposed LTI model identification architecture

Module LUT FF DSP

DKF 847 887 16

Residuals 152 0 0

Comparator 36 40 0

Division 40 0 0

Model Selection 10 10 0

Table 3.4: Resource utilization comparison in-terms of LUT between the pro-posed architectures with respect to the model size. Directly mapped = Directlymapping of the MMAE algorithm without a reduction in multiplications,

Proposed = proposed architecture, % percentage with respect to the total availableresources on VCU118-FPGA

Model Size (N)LUT

Directly mapped Proposed

16 26019 (2.2%) 15760 (1.3%)

32 50942 (4.3%) 28593 (2.4%)

64 100813 (8.5%) 60989 (5.15%)


Identification

0 51

01

52

02

53

03

54

04

55

05

56

06

51

62123

184

245306

367

428

489

550611

672

733794

855

916

977

10381099

1160

1221

12821343

1404

1465

1526

15871648

1709

17701831

1892

1953

2014

20752136

2197

22582319

2380

2441

2502

25632624

2685

27462807

2868

2929

2990

30513112

3173

Model number (1 to 64)

Tim

e (n

s)

Org

ina

l ph

ysical syste

mP

rop

ose

d a

rchite

cture

0 51

01

52

02

53

03

54

04

55

05

56

06

5

1122243364485606727848969

10901211133214531574169518161937205821792300242125422663278429053026314732683389351036313752387339944115423643574478459947204841496250835204532554465567568858095930605161726293

Model number (1 to 64)

Tim

e (n

s)

Org

ina

l ph

ysical syste

mP

rop

ose

d a

rchite

cture

(a)

(b)

x70

x70

Figu

re3.9:

(a)S

how

sth

eid

entifi

edm

od

elby

the

prop

osedarch

itecture

wh

enm

od

elssw

itched

forevery

3µs

and

(b)

switch

edfor

every6µs


Table 3.5: Resource utilization comparison in-terms of FF between the pro-posed architectures with respect to the model size. Directly mapped = Directlymapping of the MMAE algorithm without a reduction in multiplications, Pro-posed = proposed architecture, % percentage with respect to the total availableresources on VCU118-FPGA

Model Size (N)FF


16 22292 (0.94%) 16544 (0.69%)

32 39244 (1.6%) 30601 (1.2%)

64 69980 (2.9%) 60860 (2.5%)

Table 3.6: Resource utilization comparison in-terms of DSP and power, betweenthe proposed architectures with respect to the model size. Directly mapped =Directly mapping of the MMAE algorithm without a reduction in multiplica-tions, Proposed = proposed architecture, % percentage with respect to the totalavailable resources on VCU118-FPGA

Model Size (N)DSP


16 352 (5.4%) 256 (3.9%)

32 704 (10.8%) 512 (7.9%)

64 1408 (21.7%) 1024 (15.8%)

Table 3.7: Resource utilization comparison in-terms of power between the pro-posed architectures with respect to the model size. Directly mapped = Directlymapping of MMAE algorithm without a reduction in multiplications, Proposed= proposed architecture, % percentage with respect to the total available re-sources on VCU118-FPGA

Model Size (N)Power in mW


16 582 329

32 1104 613

64 2145 1203

3.2.4 Performance

3.2.4.1 Original physical system vs proposed architecture

In order to assess the performance of proposed architecture in-terms of model identifi-

cation, we consider the two case studies here, when emulated physical system changes

at 3µs , 6µs and corresponding results were shown in Figure 3.9. It is observed that

the aim of these graphs is to show that, how quickly the proposed design is able to

identify the physical system after it changes from one uncertainty level to another un-

certainty. To illustrate, considering at 12µs time instant in Figure 3.9 (a), the original

physical system changes its model from 59 to 9 (shown in dotted blue) which is accu-

rately identified by the proposed architecture (shown in brown) at 12.6µs. Similarly, the


Identification

original physical system, as shown in Figure 3.9 (b), changes the model from 59 to 58 at

30µs time instant and it was also accurately identified by the architecture at 30.36µs.

The delay between the original physical system and FPGA values is the time required

for the proposed architecture to identify the model after the original physical system

changed from one model to another model and is defined as Nas.Nclk/fclk. Where Nclk

is the number of clock cycles required for each DKF iteration and fclk is operating fre-

quency. The proposed FPGA architecture main contribution is for the terms Nclk = 7

and fclk = 100MHz. The term Nas is the number of average samples required for the

algorithm to identify the correct model after the physical system changes its model, it

also depend on the size of the residuals window, for the above cases it is ≈7.29 samples.

It is to be noted that all DKF models are running in parallel on FPGA at 100MHz fre-

quency, this is the main advantage of implementing MMAE on FPGA over the existing

DSP implementations [27, 26]. The proposed FPGA architecture is able to identify the

models in ≈510ns between 1 ≤ N ≤ 64 corresponding to the changing physical system

and overall model identification accuracy is the average difference between the physical

system model and identified model is ≈ 92% for above cases, next section discusses the

hardware resource utilization.

3.2.5 Hardware Resource Utilization

The proposed architecture conferred 16 DSP units for multiplication operation in each

DKF, whereas the directly mapped architecture conferred 22 DSP units for the multi-

plication operation. Due to the reusing of multipliers this DSP reduction is achieved

in the proposed architecture. Theoretically, it achieved 78% reduction in multiplication

however, the synthesis tool trimmed constant multiplications and thereby proposed ar-

chitecture achieves only 27% improvement in the number of multipliers, 39% for LUTs

and 13% for FFs.

To show the performance improvement of the proposed architecture, since there is no

reported architecture present, the MMAE algorithm also implemented using directly

mapped architecture it is a direct mapping of the MMAE algorithm to the hardware

without reusing the multipliers. It is also designed for the first time, which results in

100813 LUT’s, 69980 FF’s and 1408 DSP’s resource utilization for 64 models.

3.2.5.1 FPGA

The breakdown of FPGA resource utilization of the proposed architecture is presented

in Table 3.4. Among all modules, 78% of LUT’s, 94% of FF’s and 100% of DSP’s

are utilized by DKF. This is evident to say that DKF is computationally intensive.

In order to assess the variation of resource consumption with respect to model size and

resource utilization shown in Table 3.4, 3.5, 3.6 and 3.7. It can be observed that resource


utilization linearly increases with respect to model size for a fixed word length. However,

for fetching the original physical system data from BRAM to the FPGA and to capture

the output data from architecture, Vivado ILA is incorporated and total consumption

is 62328 (5.27%) of lookup table (LUT), 63070 (2.67%) of Flip-Flops, 1024 (14.97%) of

DSP’s and 28 (1.3%) Block RAM Tile on Virtex ultra-scale plus FPGA (VCU118) at

100MHz operating frequency for 64 number of models.

It can be noticed that the proposed architecture improved by 39%, 13% and 27% of

LUT’s, FF’s, DSP’s resource utilization respectively when compared with the directly

mapped architecture, detailed utilization with respect to the various bank of filter models

is given in Table 3.4, 3.5, 3.6 and 3.7. The utilization percentage is with respect to the

total available resources on VCU118 also give in the same table.

3.2.5.2 Power

0.039

0.083

0.062

0.016

0.124

0.006

0.053

0.189

0.172

0.02

0.144

0.006

Clocks

Signals

Logic

BRAM

DSP

I/O

(a) (b)

Figure 3.10: FPGA power consumption results for 16 models between the di-rectly mapped and proposed architecture

0.065

0.161

0.114

0.017

0.251

0.006

0.087

0.363

0.341

0.02

0.287

0.006

Clocks

Signals

Logic

BRAM

DSP

I/O

(a) (b)

Figure 3.11: FPGA power consumption results for 32 models between the di-rectly mapped and proposed architecture

The detailed breakdown of FPGA power consumption using the Xilinx power analyser

between the directly mapped and proposed architectures are shown in Figure 3.10, 3.11


Identification

0.151

0.71

0.683

0.02

0.575

0.006

Clocks

Signals

Logic

BRAM

DSP

I/O

0.114

0.32

0.244

0.017

0.503

0.006

(a) (b)

Figure 3.12: FPGA power consumption results for 64 models between the di-rectly mapped architecture and proposed architecture

and 3.12. The proposed architecture showed that 64%, 54%, 24%, 12% power con-

sumption reduction in logic, signals, clocks, and DSP respectively. The overall power

consumption of the proposed architecture reduced by 43% when compared with the di-

rectly mapped architecture for 64-bank of filters. Similarly, detailed power consumption

for 16 shown in Figure 3.10 and 32 number of models is shown in Figure 3.11. Whilst

power reduction is not important per scaling this application, it is important in other

“edge” computing application which do operate on battery-based backup.

3.3 Resource utilization analysis

To estimate resource utilization for the higher number of models in the MMAE, a linear

regression analysis method is used. An example derivation of the LUT resource uti-

lization regression equation for directly mapped architecture based on data presented in

Table 3.4 is given below. To show the regression analysis accuracy, outcome of regression

equations and original data comparison plots for number of models 16 to 64 are shown

Figure 3.16, 3.17 and 3.18 for LUTs, FFs and power respectively.

SumN = 16 + 32 + 64 = 112 (3.8)

SumLUT = 17774 (3.9)

MeanN = 37.33 (3.10)

MeanLUT = 59258 (3.11)

Sum of squares(SSN ) = 1194.6 (3.12)

Sum of products(SP ) = 1861584 (3.13)

(3.14)


0 200 400 600 800 1000 1200

Number of models (1 to 1024)

0

2

4

6

8

10

12

14

16

Num

ber

of r

esou

rces

105

LUT conventionalLUT proposedFF conventionalFF proposed

Figure 3.13: LUTs and FFs resource utilization of the proposed LTI MMAEarchitecture for number of models 1 to 1024

Regression Equation(LUTcon) = bN + a (3.15)

b = SP/SSN = 1861584/1194.6 = 1558.2 (3.16)

a = MY − bMN = 59258− (1558.25 ∗ 37.33) = 1083.5 (3.17)

LUTconv = 1558.2N + 1083.5 (3.18)

LUTconv = 1558.2N + 1083.5 (3.19)

LUTlow = 952.2N − 438 (3.20)

FFconv = 988.7N + 6924 (3.21)

FFlow = 926.4N + 1414.5 (3.22)

DSPconv = 22N (3.23)

DSPlow = 16N (3.24)

Powerconv = 32.5N + 61.5 (3.25)

Powerlow = 18.2N + 34 (3.26)

Similarly, linear regression equation for other resources are computed by using the data

given in Tables 3.5, 3.6 and 3.7 and results are given below. These regression equations

are useful for estimating the required number of resources and power to the required

number of models (N) in LTI MMAE. For N = 1 to 1024 LUTs and FFs resources

are illustrated in Figure 3.13, for DSPs resources illustrated in Figure 3.14 and power


Identification

0 200 400 600 800 1000 1200


0

0.5

1

1.5

2

2.5

Num

ber

of r

esou

rces

104

DSP conventionalDSP proposed

Figure 3.14: DSPs utilization of the proposed LTI MMAE architecture for num-ber of models 1 to 1024

consumption is illustrated in Figure 3.15 it is observed that as the number of models in

MMAE increases LUT, FF, DSP and power consumption linearly increasing.

0 200 400 600 800 1000 1200


0

0.5

1

1.5

2

2.5

3

3.5

Pow

er C

onsu

mpt

ion

104

Power - conventionalPower - proposed

Figure 3.15: Power consumption of the proposed LTI MMAE architecture fornumber of models 1 to 1024


10000

20000

30000

40000

50000

60000

16 32 64

Nu

mb

er

of

reso

urc

es

Number of models

LUTOriginal data Regression data

Figure 3.16: Comparison between the original data and regression analysis datafor LUT utilization

10000

20000

30000

40000

50000

60000

16 32 64

Nu

mb

er

of

reso

urc

es

Number of models

FFOriginal data Regression data

Figure 3.17: Comparison between the original data and regression analysis datafor FF utilization

3.4 Discussion

This chapter presented an investigation of architecture for LTI model identification based

on MMAE, for a large number of models. The proposed architecture was implemented

on Virtex ultra scale+ FPGA. By using shifting operation and reusing multiplier units

in the computation of the Kalman gain, Xupdate, and ΣPupdate equations of each model

in the filter banks of the MMAE algorithm, the required number of multipliers reduced.

It showed that the proposed architecture was able to achieve an improvement of 39%

LUT’s, 13% FF’s, 27% DSP’s and 43% power consumption respectively when com-

pared to the directly mapped architecture for 64 models. The proposed architecture can

identify the physical system averagely within 510ns of time when operated at 100MHz


Identification

200

400

600

800

1000

1200

16 32 64

Po

we

r (m

W)

Number of models

PowerOriginal data Regression data

Figure 3.18: Comparison between the original data and regression analysis datafor FF utilization

frequency. Due to the parallel implementation on FPGA, DKF iteration time does not

depend on the number of models in design, it can be scaled to any number of models,

therefore state-of-the-art DSP implementations [52, 27] trade-off between the number

of models and execution time overcome by using the proposed architecture on FPGA.

Therefore, this work justifies the first research objective. This chapter main aim is to

understand and analyse the hardware mapping of the MMAE algorithm and resource

utilization for the various number of filter banks to implement our main real-time power

electronics application in the next chapter. Some of the modules are also reused in the

next chapter LTV application design. The proposed architecture can be also utilized in

CPS application like adaptive estimation [110, 111], intelligent adaptive plant control

[1], position and velocity estimation [25]. Following chapter presents the LTV model

identification architecture for boost converter.

Chapter 4

Linear Time Variant System

Model Identification Architecture

The last chapter presented the hardware architecture for LTI model identification. This

chapter presents the hardware architecture for LTV model identification and its valida-

tion on power electronic application aiming to broaden the use of the MMAE for LTV

system applications. Due to the time-varying nature of the LTV physical system, the

mathematical model of the LTV system changes with time therefore, for the LTV model

identification most computation complexity is associated with the Kalman filter bank,

which involves several matrices multiplications. The hardware architecture performance

trade-off depends on the number of multipliers used in the architecture. In this in-

vestigation, an eight and four multipliers based filter bank designed within the model

identification architecture. For obtaining robust model identification the architecture

also needed to be store a considerable number of previously processed information. Due

to the limited availability of LUT’s and FF’s on FPGA, utilization of BRAM gives bal-

ance to larger filter bank designs. This chapter also presents an architecture to utilize

BRAM memory for residual computation of larger depth. The proposed architecture

experimentally validated against a range of DC-DC converter load parameters, repre-

senting typical operating loads. The FPGA implementation area, power and speed are

reported for various banks of parallel Kalman filters of sizes between 16 to 256. From the

experimental results, it is proven that the proposed four multipliers based architecture is

area-efficient and 17% LUTs, 14% FFs, 50% DSPs resource and 32% power consumption

reduction when compared with eight multipliers version architecture with an increase

in the number of clock cycles for execution. The proposed architecture implementation

on FPGA broadens the applicability of LTV model identification to systems with high

levels of uncertainty, or where the precision of model identification is paramount, and

for applications that were so far considered out of reach.

61

62 Chapter 4 Linear Time Variant System Model Identification Architecture

The remainder of this chapter is organised as follows. Section 4.1 provides an introduc-

tion, Section 4.2 provides details about the LTV model identification algorithm, Section

4.3 describes the proposed architecture, Section 4.4 provides LTV state-space matrices

of boost converter, Section 4.5 provides the details of the experimental methodology

and discusses the results and performance in terms of area, speed and power. Finally,

Section 4.6 provides details about filter bank resources utilization for the higher number

of models and finally, Section 4.7 ends the chapter with a discussion.

4.1 Introduction

There is continuing interest in developing online LTV system multiple model identifi-

cation (MI) implementations for applications such as intelligent control systems [39],

[112, 113], target tracking and detection [78], system fault detection and isolation [32,

34, 114, 79, 40]. This chapter considers a real-time model identification procedure for

a demanding application in power electronics, targeted as a component of a closed-loop

EMMSAC controller [21, 24]. This application requires rapid computation due to the

fast dynamics and hence required a fast sampling rate. The model identification pro-

cedure comprises a parallel bank of Kalman filters, each tuned to a different candidate

model. The computed residuals assess the fit of the candidate models to the real-time

observed data, thus yielding the online model identification procedure by the real-time

selection of the model of best current fit. The physical system modelled is a DC-DC

boost converter with an uncertain load [115]. To achieve the highest performance of the

converter, it is necessary to tune the controller accurately, thus motivating the need for

high-speed real-time model identification to determine the (unknown) load and other

electrical parameters to permit this tuning to be done automatically, example MMAC

scheme [21, 24]. Furthermore, the boost converter is a switched linear system and has

an LTV characteristic, hence introducing further complexity to the implementation of

the filter bank. At present, there are no reported hardware architectures for tackling the

relevant LTV system identification. This chapter provides the first-ever hardware ar-

chitecture for LTV model identification based on the recently developed multiple model

adaptive estimation (MMAE) algorithm [21]. The results build on previous work by the

authors on an LTI system identification architecture [107].

4.2 LTV model identification algorithm

The MMAE based model identification algorithm endeavour to find the best match of a

mathematical model of the physical system with the following discrete state-space model

Chapter 4 Linear Time Variant System Model Identification Architecture 63

Multiple model Adaptive Estimation (MMAE)

outputInput

Physical system

Identified model

𝑦0

+𝑦1 𝑦2

𝑢0+

−𝑢2 𝑢1

Figure 4.1: Proposed model identification block diagram

representation.

xp(t+ 1) = Apjx(t) +Bpj u1

yp1(t) = Hpj x(t)

y0 = y1 + y2

u0 = u1 + u2

u2 = Hpj y2

(4.1)

where (Apj , Bpj , H

pj ) ∈ Rnxn x Rnx1 x R1xn are the time-varying state-space matrices,

p ∈ 1, 2, ....N, j ∈ 1, 2, 3, state x is ∈ Rnx1, and (u2, y2)T are the measured signals,

(u0, y0)T are the external disturbances and (u1, y1)T are the original signals at the input

and output side of a physical system respectively as shown in Figure 4.1. The internal

structure of MMAE unit is shown in Figure 4.2, it consists of N -number of deterministic

Kalman filters (m1, m2, ... mN ) in the stage-1. Each filter runs with distinguished time-

varying system state-space matrices, these filters estimate state variables by utilizing

measured information (y2). The difference between measured and estimated signals

called as innovation (I1, I2, ...IN ). The summation of this innovation over the period

is called as residuals (R1, R2.... RN ), it is computed in the stage-2 and finally, in the

stage-3 minimum residuals represents the best-matched model of physical system, its

model number (N) sent to output stage. The pseudo-code given in Algorithm − 2,

where Apj , Bpj are state space matrices of physical system which changes with time, Ip

is innovation, Kp is Kalman gain, Σp is co-variance and l is residuals window size.

At the stage-1 (shown in Figure 4.2) computation fo DKF most expensive, its equations

are given in algorithm-2 (same as equations 2.26-2.31). The inputs of DKF module

are Apj , Bpj , H

pj with initial conditions Xp

estimate(1) (state variables), Σpestimate(1) (co-

variance) and y2, u2. The DKF module computes innovation (4.2), Kalman gain (4.3),

update and estimation of the state variable Xpupdate (4.4), Xp

estimate (4.5) co-variance

Σpupdate (4.6) and Σp

estimate (4.7).


m1(DKF) R1

R2

RN

minm2(DKF)

mN(DKF)

I1

I2

In

Stage-1 Stage-2 Stage-3

Figure 4.2: Block diagram of the proposed 3 stage architecture for MMAEbased LTV system model identification. Stage-1 is DKF computation, stage-2is residuals computation and stage-3 is minimum residuals identification. Thisarchitecture also corresponds to the MMAE part in Figure 1.2 shown in chapter1

Ip = y2 −Hpxpestimate (4.2)

Kp = ΣpHpTS−1 (4.3)

Xpupdate = Xp

estimate +KpIp/scale (4.4)

Σpupdate = Σp

estimate −KpHpΣp

estimate/scale (4.5)

Xpestimate = ApkjX

pupdate +Bp

kju2 (4.6)

Σpestimate = ApkjΣ

pupdate(A

pkj)

T +Bpkj(B

pkj)

T (4.7)

recursively. The computation of the aforementioned equations involves matrices multi-

plications, inversion, additions and subtractions. Moreover, for the LTV system, state-

space matrices change with respect to time. Due to this, the number of online mul-

tiplications in the computation of DKF is increasing when compared to LTI model

identification architecture.

4.3 Proposed architecture

The number of multiplications involved in the computation of algorithm-2 are given in

Table 4.1, most of the computational complexity is associated with the DKF module

in the computation of the estimation, Kalman gain and update equation of x and Σp

(equation 25−28 in algorithm 2). The total number of multiplications involved in these

equations is (3n+ 2n2 + 2n3)N where n is the number of states and N is the number of

models. The latency of DKF architecture directly depends on the number of available

multipliers in each cycle, to achieve maximum throughput it requires n3 +n multipliers,

however, due to resource limitation, this work investigated resource trade-off by using


Algorithm 2 Algorithm for linear time-variant CPS model identification

1: Input Apj , B

pj , H

pj where j ∈ 1, 2, 3 and p ∈ 1, 2, ....N l = window size


3: if if(mod(i,Nsamples) == 0) then

4: do in parallel

5: for p = 1, p < N, p = p+ 1 do

6: State-space matrices selection (pre-computed)

7: if case1 then

8: Apj (i) = A1

9: Bpj (i) = B1

10: end if

11: if case2 then

12: Apj (i) = A2

13: Bpj (i) = B2

14: end if

15: if case3 then

16: Apj (i) = A3

17: Bpj (i) = B3

18: end if

19: Continuous to discrete conversion (pre-computed)

20: Apkj(i) = I +Ap

j (i)Ts

21: Bpkj(i) = Bp

j (i)Ts

22: Deterministic Kalman filter

23: Sp(i) = Hp(i)Σpestimate(i)H

p(i)T

24: S−1(i) = scale/S(i)

25: Innovation (Ip(i))

26: Kalman gain (Kp(i))

27: Xpupdate(i),Σ

pupdate(i)

28: Xpestimate(i),Σ

pestimate(i)

29: Rpl (i) =

∑Tw

t=Tw−l ‖Ip(i)‖, Tw ≥ l

30: end for

31: end parallel

32: qf (i) = argminpi∈P

(‖Rpl (i)‖) for given l

33: end if

34: end for


0 50 100 150 200 250 300

Number of models

0

500

1000

1500

2000

2500

3000

Num

ber

of m

ultip

liers

ConventionalProposed mul-8Proposed mul-4

Figure 4.3: Number of multipliers comparison between the conventional andproposed eight, four multipliers version architectures for n = 2 and modelsranging form 1 to 256

n3 and n2 number of multipliers. The required number multipliers detailed comparison

is shown in Figure 4.3 with n=2 and a number model ranging from 1 to 256. It is

clear evidence that by using eight and four multipliers in DKF, a significant amount

of resources can be saved when compared with the conventional way. The proposed

hardware architecture for computing a single variable inXpupdate and Σp matrices is shown

in Figure 4.4, which mainly consists of a sequence of addition/subtraction, multiplication

and shifting operations. Dedicated registers were used to store the computed values

for reusing in subsequent operations. For n = 2, DKF latency is 10 and 15 clock

cycles respectively. Due to the resource limitation on FPGA, DKF was designed by

using reusable multipliers. For investigating hardware trade-off, each DKF was designed

using n3 and n2 reusable multipliers half of them are performs operation on bs bit-size

multiplicands, it is represented with mulv1 in Figure 4.4 and remaining half performs

operations on multiplicands with bit size bs and 2bs − 1, it is represented as mulv2 in

Figure 4.4. The structure of the reusable multiplier is shown in Figure 4.5 and details

of the architecture are described below.

In the first stage, innovation (Ip) is computed by subtracting x from y2, immediately its

absolute value also computed and the outcome of this stored in the register to perform

next stage computations. In parallel, S−1 is computed by using the division module. In

the second stage, to compute Kalman gain, n-mulv1 type multipliers are used with multi-

plicand set (Σp, S−1). Subsequently, in the third stage, the result of the aforementioned

multipliers and innovation values are fed to two mulv2 multipliers to compute KpIp.


Table 4.1: Total number of multiplication operations in model identificationarchitecture, N= Number of models, n= number of states to be estimated, No.of mul= Number of multiplications

Equation name Required No. of mul on hardware

Kalman gain (Kp) Nn2

Xpupdate Nn

Σpupdate Nn3

Xpestimate N(n2 + n)

Σpestimate N(2n3 + n2)

Total (2n+ 3n2 + 3n3)N

The final result is downscaled by scale times and stored in the registers. In the next

stage, values of Xpestimate variables are added to the obtained results respectively to get

Xpupdate values and these values are stored in the registers to utilize in the next stages.

In the same stage, n2 mulv2 multipliers are used to to compute the KpHpΣp which

is sub equation of Σpupdate. In the next stage, using four mulv1 multipliers with input

vectors given in Table 4.2 and in parallel to compute Σpupdate, outcome of four mulv2 is

subtracted from the Σpestimate. Input vectors and control bits of mulv2 are given in Table

4.3. In the next stage outcome of these multipliers are added together and subsequently

downscaled to get final Xpestimate values. It is also stored in the registers to utilize in

the next iteration of the Kalman filter. In parallel, four mulv1 are used to compute

the first column of ΣpApT with input vectors given in Table 4.2. Similarly, in the next

stage mulv1 are used to compute the second column of ΣpApT by changing input vectors

of multipliers. In the same stage, to compute ApΣpApT , n2-mulv2 are used with input

ΣpApT and Ap, in the next stage results of these multipliers downscaled and added with

BpBpT to obtain the first column of final Σpestimate. The 10 state-based state machine

is used to coordinate the data path and control path of the proposed architecture. In

the similar fashion n2-Σpestimate and n-Xp

update values are computed in single DKF for

every iteration. Similarly, N-DKF modules were designed for each state-space matrices

set Ap, Bp, Hp where 1 ≤ p ≤ N . The N -absolute values of innovations are stored in

the buffer and send to residuals module-2 (shown in Figure 4.6) for computing residuals.

Subsequently, using the argmin module, the appropriate model is been selected.

It is to be noted that, in the 1st step the state-space matrices are chosen depending on

system parameters (line number 6-18 in algorithm 2). After selecting the matrices, we

need to convert them into discrete domain by using the equation in line 20 and 21. In

algorithm 2, steps 19-21 are precomputed and stored in registers, for the brevity of under-

standing only they are presented. Here sampling time Ts, the outcome of these equations

are floating-point values, due to this, the preceding operations need to be performed us-

ing the floating-point computations. However, floating-point computation requires more

hardware resources when compared to fixed-point operations. For instance, in a Xilinx

FPGA, fixed-point addition takes one cycle, whereas a single precision floating-point


absI p

Xpestim

ateshift

Reg

DIV

∑Pestim

ate

shiftH

pHpT

mulv1

mulv1

>>>>

mulv2

mulv2

++

Xpestim

ate

Xpestim

ate

mulv1

mulv1

+

Xpupdate

Xpupdate

>>

Xpestim

ate

Input to module 2

Ap

+

Bp

mulv1

u2

y2

HpT

Reg

Kp2

Feedback to input

∑Pestim

ate

∑Pestim

ate

ApT

Kp1

Ap

mulv1

-m

ulv2

mulv1

mulv2

mulv2

++

Ap-

mulv2

ApT

∑Pestim

ate

∑Pestim

ate

∑Pestim

ate

Reg

+

BpB

pT

∑pupdate

>>>>

Figu

re4.4:

Prop

osedd

etermin

isticK

alman

filter

detailed

architectu

refor

comp

utin

gxpestim

ate

and

Σpestim

ate ,

inp

aralleln

similar

architectu

resare

used

forN

mod

elsto

com

pute

the

param

eters.(m

od

ule

2is

show

nin

Figu

re4.6)


adder would require 14 cycles while using one order of magnitude more resources for the

same number of bits [109]. Therefore, for implementing the architecture on hardware

algorithm is modified by using a scaling factor namely scale = 215 is used in algorithm 2,

this value is empirically chosen to retain precision. The scale factor converts the discrete

state-space matrices to integer values and it also helps to avoid the floating-point value

during the S−1 computation. To reduce the hardware complexity these scaling factors

are chosen as multiples of two.

*

c1

m1

c2

m1

e

f

c5

m1

c

d

c4

m1

a

b

c3

m1

e

f

c6

m1

mulv1/v2

Figure 4.5: Reusable multiplier architecture

Table 4.2: Multiplier version-1 input data, where cx is the control bit and mulxis the multiplier number

c1 c3 c4 input mul1 mul2 mul3 mul40 0 - a Σp

01 Σp11

0 1 - b xp00 xp10 xp00 xp10

1 - 0 c Σp00 Σp

01 Σp10 Σp

11

1 - 1 d Σp00 Σp

01 Σp10 Σp

11

c2 c5 c6

0 0 - e S−1 S−1

0 1 - f Ap00 Ap01 Ap10 Ap11

1 - 0 g Ap00 Ap01 Ap00 Ap01

1 - 1 h Ap10 Ap11 Ap10 Ap11

4.3.1 Control block

Since the same computational units are being reused to perform many different opera-

tions, the necessary control is rather complex. The controller block decides to choose the


Table 4.3: Multiplier version-2 input data, where cx is the control bit and mulxis the multiplier number

c1 c3 c4 input mul1 mul2 mul3 mul40 0 - a Kp

00 Kp10

0 1 - b ΣpAp00 ΣpAp10 ΣpAp00 ΣpAp10

1 - 0 c Kp00 Kp

00 Kp10 Kp

10

1 - 1 d ΣpAp01 ΣpAp11 ΣpAp01 ΣpAp11

c2 c5 c6

0 0 - e Ip Ip

0 1 - f Ap00 Ap01 Ap10 A11

1 - 0 g Σp10 Σp

11 Σp10 Σp

11

1 - 1 h Ap00 Ap01 Ap10 Ap11

input matrices values from the memory, it also needs to provide the correct sequence

data to the multiplier units and store the results in dedicated registers. This unit is

also responsible for taking the measured data and sending innovation data to the resid-

uals module for every iteration of DKF. To perform this, the proposed architecture is

designed using a one-hot state machine. In the initial state, it starts by selecting the ap-

propriate state-space matrices and subsequently sends/receives data from the multiplier

units after updating the Xp, Σp it goes back to the first state.

4.3.2 Residuals computation unit

Residual is the summation of the absolute difference between the measured voltage and

estimated voltage over the period of time and it is defined by the following equation.

Rpl (i) =

Tw∑t=Tw−l

‖Vmeasured(i)−HpXpestimate(i)‖[HpΣpHpT+1]−1 , Tw ≥ l (4.8)

where l is the length of the residuals selected based on the empirical experiments that

will be discussed in the next section and p is the model number for the corresponding

load 1 < p < N . The performance of the controller depends on the size of the residuals.

Ideally, the residuals are computed from the initial time to the current time but, since

the residuals memory requirements make impose practical applications, the window size

is to be fixed based on the trade-off between the memory and accuracy.

The residuals computation unit is shown in Figure 4.6, which is mainly consists of an

increment counter with a maximum count of l − 1. For the initial l number of DKF

iterations, innovation values are summed up using the recursive adder, in parallel in-

novation data also stored in BRAM with the address generated by the aforementioned

counter. After l − 1 number of clock cycles, the first residual output is available. To

compute subsequent residuals, the architecture adds the input innovation data and sub-

tract innovation stored at address an where n is corresponding to nth residuals. Same


Counterclk

n n-1

-

+

n-2

Abs (Innovation)

n-3 n-l

Comparator

l

0

1

1

0

0

0Residual output

REG

1

0

Figure 4.6: Proposed residuals computation architecture

time the input innovation data has stored in BRAM with address location an. By taking

advantage of the read first mode of BRAM, before writing data into the given address

location of BRAM, the data was read from the same address location. Subsequently,

N-residuals are forwarded to the argmin module for computing the minimum location

among all. This argmin sub-module is a pipelined architecture with log2Nmax stages of

comparators organized in tree structures. Argmin block individually designed for each

bank (16, 32, 64, 128, 256) and resource utilization is reported in Table 4.4.

Table 4.4: Argmin module resource utilization

No. of models LUT FF

16 92 186

32 205 401

64 433 835

128 1522 892

256 2877 1607

512 5178 2892

4.3.3 Pipelining

The modules DKF, residuals and argmin are pipelined to achieve higher efficiency, it

is shown in Figure 4.1. Stage 1, stage 2 and stage 3 are running continuously. The

processing time of each stage is mainly governed by the latency DKF module (stage-

1). For n = 2 DKF latency is 10 and 15 clock cycles respectively. In addition, due to

the parallel architecture, the latency is independent of the number of models used in

the filter bank of MMAE and it can be scalable to any number of models (N) without

impacting the execution speed.


4.4 Boost Converter Application and Model

Given an input voltage Vin the function of a boost converter is to regulate the output

voltage Vout across the load Rload to a specified value higher than Vin. This is achieved

by an appropriate choice of the PWM signal η(t) driving the MOSFET which can be

modelled as acting as an ideal switch causing the circuit to switch between two circuits

illustrated in Figure 4.7 bottom left and bottom right. Alternately switching at an

appropriate rate between these two configurations can achieve the desired regulation.

In our setting Rload is unknown, and the function of the MMAE is to determine the

model dependent on the uncertain load Rload from real-time measurements of Vout and

knowledge of input signals corresponding to Vin and the switching PWM signal.

For a fixed RL, RC , L,RDS , we now define a model p, 1 ≤ p ≤ N for a given resistive load

Rload. Assuming ideal components, the state-space representation of a boost converter

shown in Figure 4.7, is given in the continuous time domain as follows.

For each state of the switch, (on or off), the converter circuit is LTI, with the corre-

sponding SISO continuous time state-space description

xp(t) = Apjx(t) +Bpj u(t) (4.9)

yp(t) = Hpj x(t) (4.10)

where the state x(t) is given by:

x(t) =[iL(t), VC(t)

]ᵀ, (4.11)

and where the input u(t) is the input voltage and the output y(t) is the output voltage:

u1(t) = Vin, (4.12)

y1(t) = Vout(t) (4.13)


Vin

L

CRload

RL Rc

RDS

PWM=1Vin

L

CRload

D1RL RDRc

PWM=0

Vin

L

CRload

SD1

PWM

RL RDRc

RDS

PWM=1 PWM=0

(a) (b)

Figure 4.7: The boost converter circuit diagram. When the PWM signal is 1,the MOSFET acts as a closed switch (S = 1) giving rise to the left-hand circuit.When the PWM signal is 0, the MOSFET acts as a closed switch (S = 0) givingrise to the right-hand circuit

the index j describes the state of the switch: j = on,off and the state-space equations

are given by:

Apon =

[− (RL+RDS)

L 0

0 − 1C(Rload+RC)

](4.14)

Apoff =

[−Rload‖RC

L + (RL+RDS)L − Rload

L(Rload+RC)

− RloadC(Rload+RC) − 1

C(Rload+RC)

](4.15)

Bpon =

[1L

0

](4.16)

Bpoff =

[Vin−VD

L

0

](4.17)

Hpon = Hp

off =

[0

RloadRC+Rload

](4.18)

The LTV model is complete by setting

s(t) =

on if η(t) = 1,

off if η(t) = 0,(4.19)

where η(t) is taken throughout this chapter to be a 10kHz PWM signal with the 50%

duty cycle, switching between 0 and 1.

For the remainder of the chapter, the boost circuit parameters are taken to correspond


Residual-1

PWM

Voltage

Vout

ADC

Select minimum

Residual-2

Residual-N

Vin

L

CRload

SD1

PWM

RL RDRc

RDS

Model-1

Model-2

Model-N

Output

1

2

Vin

L

CRload

RL Rc

RDS

PWM=1

Vin

L

CRload

D1RL RDRc

PWM=0

Vin

L

CRload

RL Rc

RDS

PWM=1

Vin

L

CRload

D1RL RDRc

PWM=0

Vin

L

CRload

RL Rc

RDS

PWM=1

Vin

L

CRload

D1RL RDRc

PWM=0

Vin

Figure 4.8: The detailed block diagram of the boost converter model identifi-cation, 1 depicts the accurate model of the boost converter and 2 shows theMMAE block diagram in Fig. 4.1, where N is the number of models. ThePWM determines whether the top or bottom circuit is switched into the systemat any time

to the following values to operate in CCM mode: L = 330µH,RL = 0.3Ω, Ω, RD = 0.1Ω

and C = 220µF . The input voltage is Vin = 5V , resulting output voltages for various

load resistances are shown in Table 4.5. It is to be noted that, in general, boost converter

with a resistive load, the current always has the same polarity as the voltage, and this

assumption vastly simplifies the design of power circuits in general. However, with a

reactive load, the inductance or capacitance sometimes returns energy to the source,

which means that the current can have the opposite polarity from the voltage at times

during the AC cycle. This is much more difficult to handle in a power circuit. Therefore,

this thesis considered only resistive load as an uncertain parameter.


4.5 Results and discussion

The proposed architecture RTL was developed in Verilog with bit length bs=32-bit size,

synthesized using the Vivado 2018.2 and prototyped on Virtex ultra-scale plus FPGA

(VCU118). The detailed block diagram is shown in Figure 4.8 where (1) represents the

physical system and (2) represents the MMAE corresponding to Figure 4.1. The ADC

is implemented with the sample rate is taken to be 0.2MHz, i.e. a sample period of

h = 5µs and the sampling is synchronized with the 10kHz PWM signal. The bit size

is selected to retain the boost converter state-space matrices precision while converting

floating pint to fixed-point operation.

The discrete time model [116, 115] is then given by using the Euler’s first order dis-

cretization:

Xp(k + 1) = ApjXp(k) +Bp

j u(k) (4.20)

y(k + 1) = HpjX

p(k + 1) (4.21)

where h is the sample period, and where each of n models 1 ≤ p ≤ N are defined as

follows, where the matrices Apon, Apoff , Bpon, Bp

off , Hpon, Hp

off are dependent of the circuit

parameters for each model (in particular Rload is chosen to be different for each p):

Ap0 = I + hApon (4.22)

Ap1 = I + hApoff (4.23)

Bp0 = Bp

on (4.24)

Bp1 = Bp

off (4.25)

Hp0 = Hp

1 = Hpon = Hp

off (4.26)

i(k) = η(hk) (4.27)

u(k) = Vin (4.28)

y(k) = Vout(hk) (4.29)

This defines the system matrices for each Kalman filter.

4.5.1 Experimental set-up

The experimental setup of the proposed work is shown in Figure 4.9, the continuous

boost converter is emulated in MATLAB and output voltage is sampled at the rate of

0.2MHz, in a single PWM cycle 20 samples were taken. A Xilinx coefficient file (coe)

is used to store the sampled data and subsequently an FPGA BRAM IP is created

to fed Vout to core MMAE architecture on FPGA. The filter bank is operated at the

frequency of fclk=2MHz FPGA is communicated by using Vivado tool with JTAG cable


Figure 4.9: Experimental setup for FPGA in loop, where coe stands for Xilinxcoefficient

at an operating frequency of 500kHz. The integrated logic analyser (ILA) is used to

collect the computed data from FPGA. The cosponsoring design constraints file is given

in appendix A. To validate the proposed architecture, three case studies were used and

these are discussed in the following sections.

4.5.1.1 Case study-1

In this case, 5 models M1 to M5 with load resistance values R1 = 5Ω (M1), R2 =

10Ω (M2), R3 = 15Ω (M3), R4 = 42Ω (M4), and R5 = 102Ω (M5) were used in

MMAE. The boost converter load switched in following order for every 52msec time

R1, R3, R2, R4, and R5. Initially, boost converter started with 5Ω resistance, at time

instance 52msec load changed to 15Ω and at 54msec proposed architecture identified

as model-3, at 104msec load changed to 10Ω and at 106.1msec proposed architecture

identified as model-2, at 156msec load changed to 42Ω and at 157.6mec proposed ar-

chitecture identified as model-4 and finally at 208msec load changed to 102Ω and at

209.7msec time proposed architecture is identified as model-4. In all instances model

is identified by the proposed architecture. An example illustration is depicted in Fig-

ure 4.10 and corresponding residuals are shown in Figure 4.11, it can be observed that

during the time 0 − 52msec the original boost converter load is 5Ω so the residuals of

model-1 are lesser than remaining models. At 52msec time instance the load changed


0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5Time (0.005msec) 104

1

2

3

4

5

Mod

el n

umbe

r

Original modelProposed architecture

Figure 4.10: Model identification comparison between the original model andidentified by the proposed architecture with load resistance as an uncertainparameter, load started with R1 = 5Ω and changed to R3 = 15Ω at 52msec,R2 = 10Ω at 104msec, R4 = 42Ω at 156msec and at 208msec R5 = 102Ω

to 15Ω due to this residuals of model-3 is started decreasing and residuals for model-1 is

started increasing after 52msec time. A similar trend can be observed in the remaining

instances as well.

0 1 2 3 4 5Time (0.005msec) 104

0

2

4

6

8

10

Resi

duals

105

Res1

Res2

Res3

Res4

Res5

M1 M3

M2 M4M5

Figure 4.11: Residuals plot for the 5 model MMAE architecture with residualswindow size 500 where Resn= residuals for corresponding model number


Table 4.5: Steady state output voltage for the test loads with the 10kHz and70% duty cycle PWM signal

Model Rload Steady state VoutM1 5Ω 3.87V

M2 10Ω 6.3V

M3 15Ω 7.9V

M4 42Ω 11.9V

M5 102Ω 14.2 V


In this experiment, 50 models were used in MMAE to evaluate the proposed architecture

performance. These 50 models are mapped to the load resistance range 1Ω to 105Ω

as shown in Figure 4.12. Boost converter load resistance is changed Rload = 40 +

35sin(wt) where w = 2π/T where T = 260msec. As it can be seen Figure 4.13, the boost

converter original load resistance is changing in sinusoidal form 5Ω to 75Ω within 0 −260msec time-space. For the ease of understanding of the proposed architecture model

identification performance, obtained model numbers are re-mapped to the corresponding

load resistance value and it is plotted in Figure 4.13, it can be observed that it is

closely following the original load resistance. As the load resistance crosses 30Ω, the

difference between load resistance identified by the proposed architecture and original

load resistance is slightly deviating the reason is while mapping boost converter into

the discrete mathematical model the difference between the matrices is decreasing as a

result of this load resistance 30Ω − 32Ω have same state-space model. As load crosses

39Ω this difference increases even more due to this at load resistance 75Ω, proposed

architecture identifies load is 80Ω.


In this experiment, 45 models were mapped to the load resistance range 5Ω to 250Ω it

is also illustrated in Figure 4.14. The boost converter load changed with respect to time

between 5Ω to 35Ω in a sinusoidal wave manner and this sinusoidal wave repeated five

times in the time window of 260msec. The load resistance is represented as Rload =

20 + 15sin(wt). The obtained final results of model identification are remapped to load

resistance and the corresponding plot is shown in Figure 4.15. The delay between the

original and identified is induced due to the residuals window size.

4.5.2 Residuals window size impact on model identification time

To show the residuals window size impact on model identification, obtained residuals

were plotted for window size 200 (Res200), 500 (Res500), and 800 (Res800) for case


0

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100105110115

Model number

Figure 4.12: Mapping of the 50 models to boost converter load resistance range1Ω− 105Ω (case study-2)

study-1 in Figure 4.16 when the load changing from Model-1 5Ω to Model-2 15Ω, time

for the model identification is represented as T1, T2, T3 respectively for each residual

window size. The boost converter load is changed from 5Ω to 15Ω at 52msec time

instant, Res200 is identified at T1 = 52.9msec, Res500 is identified at T2 = 53.55msec

and Res800 is identified at T2 = 54.25msec. This is a clear evidence to say that the

model identification time is directly proportional to residuals window size. This work

has chosen residuals window (Nw=500) size, detailed model identification time for the

each load change mentioned in case study-1 is given in Table 4.6.

4.5.3 Performance analysis in-terms estimation

To validate the accuracy of the proposed architecture, the boost converter with the

specifications given above section are used and the generated voltage with various load


0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

Time (0.005msec) 104

0

10

20

30

40

50

60

70

80

90R

esis

tanc

e (o

hm)

Original Rload

Proposed architecture identified Rload

Figure 4.13: Boost converter load resistance and identified load resistance byproposed architecture (case study-2)

Table 4.6: Proposed architecture detailed model identification time for casestudy-1

Load change No of samples Time (msec)

5Ω to 15Ω 320 1.6

15Ω to 10Ω 400 2

10Ω to 42Ω 360 1.8

42Ω to 102Ω 340 1.7

resistance values 27Ω, 52Ω and 102Ω. The comparison between the measured voltage

and estimated voltage using the proposed architecture when changing the load resistance

from 5Ω to 15Ω is shown in Figure 4.17 and when changing the load resistance from

42Ω to 102Ω is shown in Figure 4.18. To evaluate the accuracy of estimation, the

average value estimated and measured voltage, mean square error (MSE) corresponding

equation is given below, where Nts represents the total number of samples. The proposed

architecture is achieved 99% estimation accuracy.

Accuracy =1

Nts

Nts∑i=1

(Vmeasured(i)− Vestimated(i))2 (4.30)


0

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

0 14 28 42 56 70 84 98 112 126 140 154 168 182 196 210 224 238 252 266

Model number

Figure 4.14: Mapping of the 45 models to boost converter load resistance from1Ω− 250Ω (case study-3)

4.5.4 Model identification performance

To evaluate the accuracy of identification following formula is used.

MIaccuracy =1

Nts

Nts∑i=1

|Om(i)− Im(i)| (4.31)

Where MI is model identification, Om is the original model number and Im identified

model number using proposed architecture in Figure 4.10. Model identification accuracy

for aforementioned case study 1, 2, and 3 are 99%, 92% and 91% respectively.


0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5


0

5

10

15

20

25

30

35

Res

ista

nce

(ohm

)Original R

load

Proposed architecture identified Rload

Figure 4.15: Boost converter load resistance and identified load resistance byproposed architecture (case study-3)

4.5.5 Performance analysis in-terms of area, speed and power

The detailed resource utilization comparison between an eight and four multipliers based

DKF architecture is given in Table 4.8. It is observed that, 50% improvement in DSP,

17% improvement in LUTs and 14% in FFs utilization in model identification architec-

ture using the four multipliers based DKF. This 50% DSP utilization reduction achieved

by reducing the number of multipliers from eight to four in the architecture. The pro-

posed architecture reused the four multipliers several times as explained operation in the

above section. Due to this, the four multipliers based DKF architecture number of clock

cycles for each iteration increased from 10 to 15 cycles and both eight and four multi-

pliers based architectures can operate at a maximum frequency of fclk 200MHz system

frequency. However, due to application limitation for these experiments, architecture

is operated at fclk=2MHz. The time required for the proposed architecture to identify

the model after the original physical system changed from one model to another model

is defined as NwNclk/fclk. Where Nw is residuals window size, Nclk is number of clock

cycles required for each DKF iteration and fclk is operating frequency. The proposed

architecture main contribution is for the terms Nclk=10 or 15. The detailed comparison

of model identification time at the various operating frequencies is given in Table 4.7.

It is to be noted that by using the proposed architecture, us order model identification

time can be achieved with the operating frequency of 100 and 200MHz. The high-speed

and lower resource utilization achieved by of proposed method enables the usage of the

proposed architecture on CPS edge computations FPGA platform.


1.04 1.06 1.08 1.1 1.12 1.14


0

5

10

15

Res

idua

ls

105

M1-Res

200

M1-Res

500

M1-Res

800

M3-Res

200

M3-Res

500

M3-Res

800

T1

T2

T3

Figure 4.16: Model-1 (5Ω) and Model-3 (15Ω) residuals comparison for variouswindow sizes, where Res200, Res500 and Res800 represents the residuals withwindow size of 200, 500, 800 respectively. T1 = 52.9msec, T2 = 53.55msec andT3 = 54.25msec, load is switched from M1 to M2 at 52msec time instance

0.4 0.6 0.8 1 1.2 1.4 1.6Time (0.005msec) 104

0

2

4

6

8

10

Vol

tage

Vmeasured

M1-V

1

M3-V

3

Figure 4.17: Estimated voltage using the proposed architecture when loadchanging from 5Ω to 15Ω, where Vmeasured represents the measured output volt-age from boost converter, M1 − V1 and M2 − V2 represents estimated voltageby using model-1 with 5Ω load and model-2 with 15Ω load respectively

4.5.6 Resource utilization analysis

Resource utilization for the 16, 32, 64, 128 and 256 DKFs in MMAE is given in Table

3.4 3.5 and 3.6, it is observed that as the number of DKFs increases resource utilization

linearly increasing. The proposed architecture was able to accommodate 380 second-

order DKF on Virtex ultra scale+ FPGA, whereas eight multipliers based architecture


3.5 4 4.5 5


9

10

11

12

13

14

15

Vol

tage

Vmeasured

M4-V

4

M5-V

5

Figure 4.18: Estimated voltage using the proposed architecture when loadchanging from 42Ω to 102Ω, where Vmeasured represents the measured outputvoltage from boost converter, M4−V4 and M5−V5 represents estimated voltageby using model-4 with 42Ω load and model-5 with 102Ω load respectively

Table 4.7: Proposed architecture LTV model identification average time

fclk (MHz)Model identification time8-mul 4-mul

200 25us 37.5us

100 50us 75us

2 2.5msec 3.75msec

Table 4.8: Resource utilization comparison between 8 and 4 multipliers basedarchitecture for single DKF, where mul= multiplier and Nclk is number of clockcycles required for each DKF iteration

Resource 8-mul 4-mul

LUT 1583 1354

FF 618 549

DSP 36 18

Nclk cycles 10 15

accommodated only 190 second-order Kalman filters with 10 clock cycles for each iter-

ation and 461,232(39%) of LUT’s, 322,430 (13.64%) of FF’s, 6840 (100%) of DSP’s and

95 (4.4%) BRAM’s are utilized. On the other hand, four multipliers version architec-

ture utilized 247,161 (7.9%)of LUTs, 241,099 (8.9%) of FFs, 3420 (50%) of DSPs and

95 (4.4%) of BRAMs on VCU118 FPGA with 15 clock cycles for each DKF iteration.

Details of LUTs, FFs and DSPs utilization for various number of models is shown in

Figure 4.19, 4.20 and 4.21 respectively. Note that the percentage is with respect to the

total number of available resources available on VCU118 FPGA. It is evident that the

proposed four multipliers version architecture has reduced 46% of LUTs, 25% of FFs

and 50% DSPs when compared with the 8 multipliers version architecture of filter bank.


0

100000

200000

300000

400000

500000

600000

16 32 64 128 190 256

8mul 4mul

Figure 4.19: Resource utilization of look-up tables for various number of modelsfrom 1 to 256

0

50000

100000

150000

200000

250000

300000

350000

400000

450000

500000

16 32 64 128 190 256

8mul 4mul

Figure 4.20: Resource utilization of flip-flops for various number of models from1 to 256

4.5.7 Power consumption analysis

In this work, Xilinx power analyser is used to extract the detailed power. The detailed

power consumption is given in Table 4.12. It is observed that 30%, 36%, 25%, 28% and

42% reduction achieved for 16, 32, 64, 128 and 190 models respectively by using the

four multipliers version architecture when compared with an eight multipliers version

architecture in filter banks when operating at 100MHz by penalising the number of clock

cycles for each iteration of DKF and for ease of understanding it also depicted in Figure

4.22, 32% reduction observed in power consumption. For 190 models case the detailed

power consumption analysis between eight and four multipliers version architecture in-

terms of clocks, signals, logic and DSP is given in Figure 4.23. It is to be noted that


0

1000

2000

3000

4000

5000

6000

7000

8000

9000

10000

16 32 64 128 256 512

Nu

mb

er

of

DSP

s o

n V

CU

11

8

Number of models

DSP

8mul 4mul

Figure 4.21: Resource utilization of DSPs for various number of models from 1to 256

0

2

4

6

8

10

16 32 64 128 190 256

8mul 4mul

Figure 4.22: Power consumption analysis for various number of models from 1to 256

46%, 40% and 46% power reduction achieved for signals, logic and DSP respectively.

4.6 Resource utilization for higher number of models

To estimate resource utilization and power consumption for the higher number of mod-

els, linear regression equation are derived (procedure described in chapter 3 section 3.3)

and final equations are given below (4.32-4.35).


Table 4.9: Resource utilization comparison in-terms of LUTs between eight mul-tipliers (8-mul) and four multipliers (4-mul) based architectures with respect tothe model size (N). Where N= number of DKF models in MMAE, †=estimatedLUT resources and percentage % with respect to the total number of availableresources on Virtex ultra scale+ FPGA

Model Size (N)LUT

8-mul 4-mul

16 24,859 (2.1%) 20,282 (1.7%)

32 49,422 (4.1%) 40,548 (3.1%)

64 101,312 (8.3%) 86,656 (6.8%)

128 197,908 (16.7%) 162,584 (13.7%)

190 461,232 (38.9%) 241,099 (20%)

256 571,120 (48.1%)† 325,141 (27%)

Table 4.10: Resource utilization comparison in-terms of FFs between eight mul-tipliers (8-mul) and four multipliers (4-mul) based architectures with respect tothe model size (N). Where N= number of DKF models in MMAE, †=estimatedFF resources and percentage % with respect to the total number of availableresources on Virtex ultra scale+ FPGA

Model Size (N)FF

8-mul 4-mul

16 24,516 (1%) 20,853 (0.8%)

32 48,821 (2%) 41,508 (1.7%)

64 97,414 (3.5%) 82,790 (3.39%)

128 195,992 (8.2%) 166,702 (7%)

190 322,430 (13.4%) 247,161 (10%)

256 486,876 (19%) † 332,903 (13.8%)

0

0.5

1

1.5

2

2.5

3

3.5

Clocks Signals Logic DSP

0.404

3.41

2.42

1.57

0.37

1.83

1.44

0.84

8-mul 4-mul

Figure 4.23: Detailed power reduction comparison between eight and four mul-tiplier version filter bank for 190 models MMAE at operating frequency of100MHz. An eight and four multipliers version architecture takes 10 and 15clock cycles respectively

LUT4−mul = 1274.17N + 1381.87 (4.32)

FF4−mul = 1290.99N + 38.47 (4.33)


Table 4.11: Resource utilization comparison in-terms of DSPs between the 8multipliers (8-mul) and four multipliers (4-mul) based architectures with re-spect to the model size (N). Where N= number of DKF models in MMAE,†=estimated DPSs and percentage % is with respect to the total number ofavailable resources on Virtex ultra scale+ FPGA

Model Size (N)DSP

8-mul 4-mul

16 576 (8.4%) 288 (4.21%)

32 1,152 (16.8%) 576 (8.4%)

64 2,304 (33.6%) 1,152 (16.8%)

128 4,608 (67.3%) 2,304 (33.6%)

190 6,840 (100%) 4,608 (67.3%)

256 9,216 † 6,840 (100%)

Table 4.12: Power consumption comparison between the 8 multipliers (8-mul)and 4 multipliers (4-mul) based architectures with respect to the model size.Where N= number of DKF models in MMAE, †=estimated power and percent-age % is with respect to the total number of available resources on Virtex ultrascale+ FPGA

Model Size (N)Power (W)

8-mul 4-mul

16 0.572 0.4

32 1.13 0.712

64 2.1 1.57

128 4.2 3

190 7.8 4.46

256 10.6 † 6.14

Table 4.13: BRAM utilization for the 8 multipliers (8-mul) based and 4 multi-pliers (4-mul) architectures with respect to the model size. Where N= numberof DKF models in MMAE, % is with respect to the total number of availableresources on Virtex ultra scale+ FPGA

Model Size (N) BRAM for 8-mul/4-mul

16 8(0.37%)

32 16(0.74%)

64 32(1.48%)

128 64(2.96%)

190 95(4.3%)

256 128(5.9%)

DSP4−mul = 18N (4.34)

Power4−mul = 0.02383N + 0.012 (4.35)


4.7 Discussion

This chapter presented the hardware architecture for linear time-variant CPS model

identification with an eight and four multiplier based DKF in the filter bank of MMAE.

The proposed architecture is validated on the most demanding power electronics appli-

cation and model identification results were presented for the three case studies. Results

were shown that the proposed four multipliers based architecture improved 17% LUTs,

14% FFs, 50% DSPs and 32% power consumption when compared with an eight mul-

tipliers based architecture with a cost of increase in the model identification time. The

proposed architecture is generic and scalable to any filter bank size and it can be oper-

ated at frequency of 100MHz and achieved model identification time in the orders of us

and also broadens the real-time MMAE to power electronics [31, 32], fault detection and

isolation for power electronics devices [33] and batteries [34], state of charge estimation

for batteries [35, 36, 37], high speed train control [38], gas turbain control [39], and nu-

clear power plants [40] applications. Thereby, enhancing the safety and reliability and

reducing the operating cost of CPS applications. This architecture can be used in the

real-time resource-constrained edge computing embedded and cyber-physical systems at

high execution speed. This work broadens the applicability of the LTV model identifi-

cation to the large uncertainty systems, in custom hardware platforms that have been

considered out of reach to date.

Chapter 5

Multiple Model Adaptive

Estimation Based Control with

an application of DC−DC Boost

Converter

The last chapter presented the hardware architecture for LTV system model identifica-

tion based on multiple model adaptive estimation. This chapter presents an investigation

of the EMMSAC approach to regulate DC−DC boost converter output voltage which

involves both model identification and closed-loop control. This is the first-ever at-

tempt to apply EMMSAC for power electronic application. Through the simulations, it

is proven that EMMSAC able identify the load of the DC−DC converter and selected

the right controller from the bank of pre-designed controller set to maintain the target

output voltage. The control objective, i.e. the regulation of the voltage to its reference,

is achieved by directly manipulating the DC-DC converter switch. The simulation re-

sults shows that EMMSAC achieves improved control time, transient and steady-state

performance for DC-DC boost converter in the presence of load resistance uncertainties

when compared to traditional PID controller. The second part of this chapter provides

real-time model identification for the two model-based DC-DC boost converter. To

evaluate the real-time performance of the two benchmarks with various load resistance

values. Through experiments, it is identified that the proposed architecture is taking an

averagely of 0.31msec time to identify the physical system changes.

The organisation of this chapter as follows. Section 5.1 begins the discussion with the

necessity of EMMSAC based control for the boost converter, Section 5.2 provides details

about the proposed methodology, Section 5.3 provides simulation results for various

benchmarks. Section 5.4 discuss the two model-based real-time model identification and

91

92Chapter 5 Multiple Model Adaptive Estimation Based Control with an application of

DC−DC Boost Converter

their implementation details along with final results. Finally, Section 5.5 summarises

the chapter with a discussion.

5.1 Introduction

Over the past decades DC-DC boost converter became ubiquitous in CPS applications

such as photovoltaic (PV) power systems [41], offshore wind turbines (OWT) [42], elec-

tric/ hybrid electric/ plug-in-hybrid electric/ fuel cell vehicles (EV/ HEV/ PHEV/ FCV)

[43], medium-voltage DC (MVDC) and high-voltage DC (HVDC) power systems [44, 45],

telecommunication power supply [46], on shipboard power system [47], dc motor drives,

personal computers, home appliances, and portable electronic e.t,c [48, 49]. These con-

verters present several challenges regarding their control issue since modern electronic

systems deeply require high-quality, lightweight, reliable, adaptive, and efficient power

supplies [50, 51]. Early control efforts for these systems contributed to the linear control

methods based on linearised models [117], but it is clear that those control performances

deteriorate under various disturbances in the DC−DC converter circuit. Later research

results are concerned to non-linear control strategies which are frequently studied as

applications into different types of DC−DC converters in the literature, such as back-

stepping control [118], adaptive control [119], model predictive control [120, 121] and

sliding mode control [122], fuzzy logic control [123, 124], optimal control [125], time-

domain design [126], feed-forward control [127, 128] etc. On the other hand, the load

uncertainties in system models are inevitable in practical control problems caused by

modelling errors, uncertain sensor measurement, different operating circumstances, and

so on [129]. Hence, high efficient controllers which pursue smaller steady-state error,

faster dynamical response, lower overshoot are genuinely needed. Besides these common

requirements, the closed-loop control performance of the converter system should have

good uncertainty attenuation ability when system affected by uncertainties and real-

time disturbances [130]. Although existing control approaches have been shown to be

reasonably effective, several challenges have not been fully addressed yet, such as ease

of controller design and tuning, as well as robustness to load parameter variations. In

particular, power electronic applications require control responses in the order of tens

to hundreds of microseconds to work properly [131].

Motivated by the aforementioned challenges this chapter investigates the applicability

of EMMSAC to boost converter [21, 22] for improvising the closed-loop control timing

performance. The main control objective is to regulate the output voltage to the desired

value while rejecting the impact of variations in the load uncertainties. It is be noted

that this is the first-ever attempt to apply EMMSAC in the power electronics domain. It

is to be noted that, an extensive survey on the regulatory controllers used in industries

reveals that 97% of them are of PID structure, due to their simplicity, applicability

Chapter 5 Multiple Model Adaptive Estimation Based Control with an application ofDC−DC Boost Converter 93

and ease of implementations [132]. Therefore, this chapter used the PID controller as a

reference to validate the performance of EMMSAC methodology.

5.2 EMMSAC for DC-DC boost converter

VoltageVout

A/DVin

L

CRload

SD1

PWM

RL RDRc

RDS

Vin

L

CR1

RL Rc

RDS

Vin

L

CR1

D1RL RDRc

S=1

S=0

DKF-1

DKF-2

DKF-N

DKF-3

PWM-1

PWM-2

PWM-N

PWM-3

Residuals-N

Residuals-2

Residuals-1

Residuals-3

Argmin

DSwitch

D/A

Estimator setController set

𝑦0

𝑦2

Figure 5.1: Block diagram of the proposed multiple model adaptive estimationbased control of boost converter, where DKF1, DKF2,−−−DKFN

represents the deterministic Kalman filter which estimates output voltage ofthe boost converter for various load resistance values, N is the number of load

resistors, D is the switching delay

The block diagram of EMMSAC for DC-DC boost converter is shown in Figure 5.1,

major computation units are boost converter model identification and controller acti-

vation unit. In most of the applications, DC-DC boost converter load is unknown and

time-varying. Hence, to control the boost converter efficiently, accurate knowledge of



load is necessary. The estimator set shown in Figure 5.1 is identifying the accurate load

resistance of the boost converter. This estimator set is similar to the model identifi-

cation architecture presented in chapter 4. Boost converter estimator set consists of

deterministic Kalman filters and state-space matrices for each of these filters are derived

based on the load resistance value of boost converter during the switch ON and OFF

period for region-1, 2 and 3 as discussed in section 2.7. Based on the difference between

measured (y2) and estimated voltage Kalman filters compute the innovation. The sum-

mation of these innovations over the period of time is called residuals and the smallest

residuals represent the best-matched load of the boost converter. After identifying the

best-matched model, the required PWM signal fed to the boost converter switch from

the bank of the controller unit to maintain the required output voltage. The description

of each unit explained clearly in the following subsections and detailed pseudo-code is

given algorithm 3.

5.2.1 Physical system model set generation

Section 2.7 explained the boost converter operating regions and their corresponding

state-space matrices in the continuous-time domain. Moreover, the operation of the

boost converter is defined by three different state-space matrices, which mainly depend

on the inductor, capacitor and load resistance of the boost converter. In this work,

the load resistance is considered as uncertainty in the physical system, which changes

randomly and the goal of EMMAC is to provide the constant reference output voltage

irrespective of change in the load. This work considered the following L = 330µH,C =

220µF to operate boost converter in CCM mode and by using various load resistances

(Rload), system models are generated. The physical system model shown in Figure 5.1

are defined as

Xp(k + 1) = (I + TsApj )X

p(k) + TsBpj u1 (5.1)

y(k + 1) = HpXp(k + 1) (5.2)

Where p is the system model number ∈ 1, 2, 3, ............N. Apj and Bpj are the physical

system (boost converter) continuous domain state-space matrices and j ∈ on, off1, off2.Boost converter will switch among the three state-space matrices for each PWM cycle.

5.2.2 Control Problem for DC-DC boost converter

The main control objective of the boost converter is to maintain the output of the

boost converter to a reference voltage despite changes in the load resistance. This can

be achieved by controlling the MOSFET switch with a pulse width modulated signal.


Algorithm 3 EMMSAC based controller for DC-DC boost converter

1: Input Apj , B

pj where j ∈ on, off1, off2 and p ∈ 1, 2, ....N l = window size

2: Global variable PWM

3: options = odeset(′MaxStep′, 10−5)


5: [t, xcts] = ode23(@cts function name, [t1 : h : t2], xk(r, :), options);

6: xk(i+ 1, :) = xcts(length(t), :);

7: if if(mod(i,Nsamples) == 0) then

8: for p = 1, p < N, p = p+ 1 do

9: State-space matrices selection

10: if PWM = 1 then

11: Ap(i) = Apon

12: Bp(i) = Bpon

13: end if

14: if PWM = 0 and xestimate(i)(1, 1) > 0 then

15: Ap(i) = Apoff1

16: Bp(i) = Bpoff1

17: end if

18: if PWM = 0 and xestimate(i)(1, 1) <= 0 then

19: Ap(i) = Apoff2

20: Bp(i) = Bpoff2

21: end if

22: Continuous to discrete conversion

23: Apk(i) = I +Ap(i)Ts

24: Bpk(i) = Bp(i)Ts

25: Deterministic Kalman filter

26: Ip(i) = y2(i)−HpXpestimate(i)

27: S−1(i) = scaleHpΣp(i)HpT

28: Kp(i) = Σp(i)HpTS−1(i)

29: Xpupdate(i) = Xp

estimate(i) +Kp(i)Ip(i)/scale

30: Σpupdate(i) = Σp(i)−Kp(i)HpΣp(i)/scale

31: Xpestimate(i) = Ap

k(i)Xpupdate(i) +Bp

k(i)u2

32: Σpestimate(i) = Ap

k(i)Σpupdate(i)A

pTk (i) +Bp

k(i)BpTk (i)

33: Rpl (i) =

∑Tw

t=Tw−l ‖Ip(i)‖[HpΣpHpT +1]−1 , Tw ≥ l

34: end for

35: qf (i) = argminpi∈P

(‖Rpl (i)‖) for given l

36: end if

37: Controller activation

38: if if(mod(i, 100) == 0) then

39: PWMout = PWM(qf (i))

40: end if

41: end for



During transients, the output voltage should be regulated to its reference value within

msec of time with little overshoots.

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 66 69 72 75 78 81 84 87 90 93 96

PWM duty cycle

Figure 5.2: Required PWM duty cycle for various load resistance values in range7Ω to 90Ω

5.2.3 Controller Set

The controller set main functionality is to generate the appropriate PWM signal for each

load to maintain the desired output voltage level. As shown in Figure 5.1, controller set

having bank of PWM generators which generates the required PWM for each identified

load. For EMMSAC controller set is to be designed before usage. Therefore in this work,

a PID controller was used to determining the required PWM for various systems. The

PWM generation equations are given below.

PWM(i) = PWM(i− 1) +KpVerror(i− 1) + Ierror(i− 1)KI +Derror(i− 1)Kd if Ve > 0

(5.3)

PWM(i) = PWM(i− 1)− (kpVerror(i− 1) + Ierror(i− 1)KI +Derror(i− 1)Kd) if Ve < 0

(5.4)

Where Ve is the difference between reference voltage and measured voltage, Ierror, Derror

are the integral and differential error respectively. Kp = 0.004,KI = 0.0002,Kd = 0.0068

are the proportional, integral and differential coefficients respectively, these values were

empirically found. The final PWM values for various load resistances, obtained by

above procedure are plotted in Figure 5.2 and values are given in Table 5.1 for range of

7Ω to 90Ω. The controller set is pre-designed by using the obtained PWM duty cycle


values. It is observed that as the load resistance decreases the required PWM value is

increasing.

Table 5.1: The controller set PWM values for boost converter with various loadresistances

Model number Rload(Ω) PWM duty cycle (0-1)

1 7 0.74

2 8 0.69

3 9 0.634

4 10 0.62

5 11 0.6

6 12 0.59

7 15 0.57

8 18 0.559

9 20 0.54

10 25 0.54

11 30 0.53

12 35 0.527

13 40 0.52

14 45 0.52

15 50 0.518

16 55 0.515

17 60 0.49

18 65 0.47

19 70 0.45

20 75 0.43

21 80 0.427

22 85 0.41

23 90 0.399

5.2.4 Closed loop operation using EMMSAC

The model identification mainly involves three operations, which are an estimation of

boost converter output voltage using the deterministic Kalman filter, computation of

innovation and residuals and minimum residuals selection. These operations are already

clearly explained in chapter 4. Model identification unit output is subsequently for-

warded to the controller set unit. Controller set consists of the bank of pre-designed

PWM generates which are designed based on the reference voltage. As shown in Figure

5.1, the controller activation unit takes inputs from the model selection block. Based on

the identified model appropriate pulse width is generated to maintain the desired output

voltage under various load conditions.



5.3 Simulation Results

In this section, the application of EMMSAC to boost converter simulation results are

presented to illustrate the performance of the EMMSAC based controller over the PID

controller. The performance metric of the boost converter is the time required for the

controller to produce the required PWM duty cycle to maintain boost converter out-

put voltage to a target voltage. The circuit parameters are L= 330µH, RL = 0.3 Ω,

RC=0Ω, RD=0.1Ω, and C = 220µF chosen to operate boost converter in CCM mode.

Input voltage is Vin = 5V and reference output voltage is Vout = 10V . Load resis-

tance of boost converter is considered as an uncertain parameter. The boost converter

switched at 10kHz and output voltage sampled at 5µs to feed it to the estimator set. To

evaluate the performance of the proposed methodology, simulations were carried out on

various benchmarks in MATLAB by changing boost converter load resistance abruptly.

MATLAB was executed on an Intel Core i7-6700-CPU @3.4GHz sequentially. It is to

be noted that the control time information provided in this section is relative to boost

converter operating time, it is not real CPU hardware processing time.

During the simulations, the original system is simulated in a continuous domain by using

the ode23 function [133] with a step size of h. The output voltage obtained from the

system is stored in an array, subsequently, the output voltage is feed to the estimator set

(shown in Figure 5.1) which runs based on the discrete model (given in section 4.4), with

sampling time Ts = 5µs. The bank of Kalman filter computes the innovation (equation

4.2 ) it is forwarded to residuals computation block. It is to be noted that during the

initial stage, a minimum PWM duty cycle 0.3 was given to the estimator unit and the

same value is continued until it gets the first model identification output. The residuals

calculation block have the arrays for various window sizes, which stores the summation of

absolute innovation value for every model. By using an argmin function, the minimum

position of residuals among all model residuals values is evaluated. This minimum value

is forwarded to the controller unit with the delay of D = 1msec such that it allows a

minimum of 10 PWM cycles. Based on this minimum value controller set chosen the

PWM duty cycle to control the continuous domain boost converter.

5.3.1 Performance during abrupt load change

5.3.1.1 Benchmark-A

This benchmark is developed by using the 3 models in EMMSAC with boost converter

load resistance (Rload) 8Ω, 25Ω, and 55Ω. Further, based on the equation 5.1 and 5.2,

state-space model matrices are computed and required PWM duty cycles are 0.559,

0.54 and 0.515 (given in Table 5.1) respectively for each load resistance. The algorithm

3 is simulated for total time of 200msec. Initially, at 0th time the boost converter is


Tab

le5.

2:B

ench

mark

-A:

Boos

tco

nver

terRload

chan

ged

to2nd

load

at50msec

and

to3rd

load

at10

0msec

Ben

chm

ark

-AL

oad

resi

stan

cech

an

gin

gor

der

(Ω)

1st

load

Tim

e(msec)

2nd

load

Tim

e(msec)

3rd

load

Tim

e(msec)

EM

MS

AC

PID

EM

MS

AC

PID

EM

MS

AC

PID

125,

8,

5525

319

851

7355

101

127

235,

12,

80

353

198

5159

8010

114

3

330,

10,

70

303

3310

5162

7010

114

3

440,

15,

75

403

3415

5160

7510

214

3

535,

10,

65

353

2010

5163

6510

214

3

625,

12,

60

253

1912

5157

6010

3.5

143

718,

7,

4518

318

751

6045

103

116

815,

9,

2515

318

952

5825

101

114

915,

8,

3015

318

851

7230

101

115

10

30,

8,

6030

318

851

7360

101

144

Tab

le5.3

:B

ench

mar

kB

:B

oost

conve

rterRload

isch

ange

dto

2nd

at50msec,

3rd

at10

0msec,

4th

at15

0msec

and

5th

at20

0msec.‡

Inth

isca

se5th

load

issw

itch

edat

230m

sec

Ben

chm

ark

-BL

oad

resi

stan

cech

angin

gord

er(Ω

)1st

load

Tim

e(msec)

2ndlo

adT

ime

(msec)

3rd

load

Tim

e(msec)

EM

MS

AC

PID

EM

MS

AC

PID

EM

MS

AC

PID

1‡10

,30

,8,

85,

15

103

20.9

3052

668

103

122

210

,18

,70

,7,

35

103

1918

5160

7010

312

2

312

,20

,80

,8,

50

123

1920

5462

8010

114

2

415

,25

,75

,9,

45

153

1825

5360

7510

114

3



0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

105

0

5

10

15

Vol

tage

(V)

vout

EMMSAC

v out

PID

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2Time (us) 105

0.3

0.4

0.5

0.6

0.7

PWM

EMMSAC PWMPID PWM

Figure 5.3: Comparison between the proposed methodology and PID controllerin-terms of boost converter out voltage and PWM duty cycle, when loadchanged from 25Ω to 8Ω and 8Ω to 55Ω. Benchmark-A1: Rload=8Ω (Model -1),Rload=25Ω (Model-2), Rload=55 Ω (Model-3). Total simulation time 0-200msec,initially boost converter stared with load 25Ω, at time instance 50msec loadchanged to 8Ω and at 100msec load changed to 55Ω. Plots for Benchmark A10were given in appendix B

stared with load resistance 25Ω and both the EMMSAC and PID controllers were set to

default minimum PWM 0.30. After a switching delay of 1msec PID controller PWM

duty cycle changed to 0.32 and EMMSAC is not changed. At the time of 2.52msec

estimator set is identified as original load resistance as model-2. Since the controller

delay is 1msec, EMMSAC takes new model identification value only at 1, 2, 3 ...tn

msec. At the time of 3msec EMMSAC is activated PWM duty cycle 0.54 to maintain

boost converter voltage at 10V whereas PID controller took 19msec time. Similarly, at

time 50msec, boost converter load changed to 8Ω and EMMSAC identified a change in

the model at 50.4msec and at 51msec, PWM duty cycle changed to 0.69 to maintain

output voltage 10V whereas PID controller is reached changed at 73msec. At time

instance 100msec, boost converter load changed to 55Ω and EMMSAC identified the

change in load resistance at 100.5msec and activated PWM duty cycle 0.515 at 101msec

time whereas PID controller is changed its PWM duty cycle at 127.6msec time. The

final output voltage and PWM duty cycle with respect to time are shown in Figure

5.3, it is observed that the EMMSAC methodology is controlling output voltage (10V)

faster than the PID controller with less overshoot and undershoot voltages. Similarly,

ten different benchmarks were evaluated to justify the performance of EMMSAC over


the PID controller and tabulated them in Table 5.2, where closed-loop, required duty

cycle activation time for every load change is given as time (msec). It is observed that

for smaller change in load resistance the closed-loop timing of EMMSAC is improved by

ten times and for larger change in load resistance, EMMSAC improved by twenty times

when compred to the PID controller.

To show the tracking error in terms of residuals ( equation 33 in algorithm 3) between

the boost converter physical system and multiple models for benchmark-A, residuals

plots were shown in Figure 5.4. It is observed that when the physical system load

resistance matches to the corresponding model, its error is less and thereby residuals of

the corresponding model is smaller than the other models. For examples in Figure 5.4,

for the window size 500 between 0 − 50msec time, the physical system load resistance

is matched to model-2 and its residuals is smaller than other models-1, 3. Similarly,

from 50 − 100msec time load resistance is matched to model-1, its residuals is smaller

than the remaining models-2, 3. Finally, from 100−200msec time, physical system load

resistance is matching to model-3 and its residual smaller than the reaming models-1, 2.

5.3.1.2 Residuals window selection

The EMMSAC closed-loop performance depends on model identification time which

directly proportional to the residuals window size and residuals computed by using

equation-33 in algorithm 3. To select appropriate window size for the residuals, several

simulations were carried out with the residuals window size of 100, 200, 300, 400, 500

1000 and these are represented by W100,W200,W300,W400,W500 and W1000 respectively.

For Benchmark-A with load resistance set 8Ω,25Ω, 55Ω obtained residuals were plotted

in Figure 5.4 where R1, R2 and R3 are residuals of model 1, 2 and 3 respectively. It

can be observed that, as the residuals window size increases, the residuals value is also

increasing. To explain impact of window size the same Figure 5.4 is shown for the

shorter time period (100msec to 200msec) in Figure 5.5. With the window size 100

and 200, residuals corresponding to the model-2 and model-3 are overlapping each other

due to this the final output of model identification keep changes between model 2 and 3

and in a closed-loop, the controller block also changes its controller, thereby the boost

converter becomes unstable. As the window size increase 300 and 400 the separation

between model 1 and 2 residuals is also increasing. For window size 500, 1000, residuals

of model 2, 3 are clearly separated thereby output of the model identification unit will be

constant. It to be noted that as the residuals window size increases, model identification

time also increase therefore in this work empirically chosen 500 is the window size for

all benchmarks validation.



0 1 2 3 4Time (0.005msec) 104

0

0.5

1

1.5

2

Resid

uals

(V)

105 Window 100

R1

R2

R3

0 1 2 3 4Time (0.005msec) 104

0

1

2

3

4

Resid

uals

(V)

105 Window 200

R1

R2

R3

0 1 2 3 4Time (0.005msec) 104

0

1

2

3

4

5

Resid

uals

(V)

105 Window 300

R1

R2

R3

0 1 2 3 4Time (0.005msec) 104

0

1

2

3

4

5

6

Resid

uals

(V)

105 Window 400

R1

R2

R3

0 1 2 3 4Time (0.005msec) 104

0

1

2

3

4

5

6

Resid

uals

(V)

105 Window 500

R1

R2

R3

0 1 2 3 4Time (0.005msec) 104

0

2

4

6

8

Resid

uals

(V)

105 Window 1000

R1

R2

R3

Figure 5.4: Residuals plots for the 3 model EMMSAC based boost con-verter. Where Rn represents the residuals for model n. Rload=8Ω (Model -1),Rload=25Ω (Model-2), Rload=55 Ω (Model-3). Total simulation time 0-200msec,initially boost converter stared with load 25Ω, at time instance 50msec loadchanged to 8Ω and at 100msec load changed to 55Ω (same graph from time100msec to 200msec is shown in Figure 5.5)

Table 5.4: Boost converter Rload is changed to 2nd at 50msec, 3rd at 100msec,4th at 150msec and 5th at 200msec. ‡ In this case 5th load is switched at230msec

Bench-mark-B

Rload changingorder (Ω) (Ω)

4th loadTime (msec)

5th loadTime (msec)

EMMSAC PID EMMSAC PID

1 ‡ 10, 30, 8, 85, 15 85 152 204 15 231 249

2 10, 18, 70, 7, 35 7 151 171 35 202 210

3 12, 20, 80, 8, 50 8 151 174 50 202 224

4 15, 25, 75, 9, 45 9 151 164 45 203 216

5.3.1.3 Benchmark-B

In this benchmark, the 5 model based EMMSAC were considered, models 1-5 designed

with a load resistance of 8Ω, 10Ω, 15Ω, 30Ω and 85Ω respectively. Controllers were de-

signed to generate PWM duty cycle 0.69, 0.62, 0.57, 0.53 and 0.41 for each associated

load resistance to maintain 10V output voltage. Boost converter load is changed among

the aforementioned five load resistance values within the time window of 270msec. Ini-

tially, the boost converter started with load resistance 10Ω both the EMMSAC and PID


2 2.5 3 3.5 4Time (0.005msec) 104

0

1000

2000

3000

4000

5000

6000

Res

idua

ls (

V)

Window 100

R1

R2

R3

2 2.5 3 3.5 4Time (0.005msec) 104

0

2000

4000

6000

8000

10000

Res

idua

ls (

V)

Window 200

R1

R2

R3

2 2.5 3 3.5 4Time (0.005msec) 104

0

5000

10000

15000

Res

idua

ls (

V)

Window 300

R1

R2

R3

2 2.5 3 3.5 4Time (0.005msec) 104

0

0.5

1

1.5

2

Res

idua

ls (

V)

104 Window 400

R1

R2

R3

2 2.5 3 3.5 4Time (0.005msec) 104

0

0.5

1

1.5

2

2.5

Res

idua

ls (

V)

104 Window 500

R1

R2

R3

2 2.5 3 3.5 4Time (0.005msec) 104

0

1

2

3

4

5

Res

idua

ls (

V)

104 Window 1000

R1

R2

R3

Figure 5.5: Residuals plots for the 3 model EMMSAC based boost converter toobserve the residuals window impact on final residuals values between 100msecto 200msec time (same graph from time 0 to 200msec is also shown in Fig-ure 5.4), where Rn represents the residuals for model n. Rload=8Ω (Model-1), Rload=25Ω (Model-2) and Rload=55Ω (Model-3). Total simulation time 0-200msec, initially boost converter stared with load 25Ω, at time instance 50msecload changed to 8Ω and at 100msec load changed to 55Ω

controller are started with a minimum PWM duty cycle of 0.3. EMMSAC identified load

resistance is equivalent to model-2 at 2.88msec and activated PWM duty cycle 0.62 to

maintain target output voltage (10V) and PID controller reached to 0.64 at 25msec. At

50msec boost converter load is changed to 30Ω, EMMSAC has identified it at 51.1msec

time and activated duty cycle 0.53 at 52msec, whereas PID controller PWM is reached

0.53 at 65msec. Similarly, at 100msec load changed to 8Ω, at 102.5msec EMMSAC is

identified a change in load resistance activated duty cycle 0.69 at 103msec and PID con-

troller changed to the same duty cycle at 125msec. At the time instance 150msec load

changed to 85Ω, EMMSAC identified it 151.1msec as model-5 and activated duty cycle

0.41 at 152msec, whereas PID controller is changed to 0.41 at 202msec time. When the

load changed from 8 to 85Ω, the EMMSAC timing performance is 26 times higher than

the PID controller. Finally, at 230msec load changed from 85Ω to 15Ω, EMMSAC iden-

tified it at 230.45msec and activated PWM duty cycle 0.57 at 231msec, whereas PID



00

.51

1.5

22

.5

10

5

0 2 4 6 8

10

12

14

16

Voltage(V)

vo

ut E

MM

SA

C

v o

ut P

ID

00

.51

1.5

22

.5T

ime (u

s)1

05

0.2

0.3

0.4

0.5

0.6

0.7

PWM

EM

MS

AC

PW

MP

ID P

WM

Figu

re5.6

:B

ench

mark

-B:

5m

od

elb

asedE

MM

SA

Cclosed

loop

comp

arisonb

etween

the

prop

osedm

ethod

ologyan

dP

IDcon

trollerin

-terms

boost

converter

ou

tvo

ltage

an

dPWM

signal,

Vin

=5V

andVout

=10V

.in

itiallyE

MM

SA

CP

IDPWM

arestarted

with

defau

ltPWM

du

tycy

cle0.3

0.

Loa

dresistan

ce(R

load )

chan

gesfrom

10Ωto

30Ωat

50msec,

30Ωto

8Ωat

100msec,

8Ωto

85Ωat

150msec

an

d85Ω

to15

Ωat

230msec


controller reached at 251msec. It is observed that when load changed from 85 to 15Ω

EMMSAC timing performance is 20 times higher than the PID controller. The output

voltage and PWM duty cycle with respect to time are depicted in Figure 5.6. Similarly,

4 different benchmarks were evaluated to justify the performance of the EMMSAC over

PID controller and tabulated them in Table 5.3 for load 1-3 and Table 5.4 for load 4-5,

where closed-loop controller activation time for every load change is given in msec.

5.3.2 Wrong controller effect on model identification

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

105

0

5

10

15

Vol

tage

(V)

vout

EMMSAC

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2Time (us) 105

0.3

0.4

0.5

0.6

0.7

PW

M

EMMSAC PWM

Figure 5.7: Plot to show the effect of EMMSAC when wrong controller activated,when load changes from 25Ω to 8Ω and 8Ω to 55Ω. Benchmark-A1: Rload=8Ω(Model -1), Rload=25Ω (Model-2), Rload=55 Ω (Model-3). Total simulationtime 0-200msec, initially boost converter stared with load 25Ω, at time instance50msec load changed to 8Ω and at 100msec load changed to 55Ω

To show the effect of the wrong controller on EMMSAC model identification perfor-

mance, simulations were performed on Benchmark-1 with load resistance 8, 25 and 55Ω

(Model-1, 2, 3). Controller set pulse width values 0.69, 0.54 and 0.515 are used, these

values are corresponding to the model 1, 2 and 3 respectively to maintain targeted output

voltage 10V. However, in this experiment model-1, 2, 3 are controlled by controller-2, 1,

3 respectively to observe the model identification performance. The system change order

is 2, 1, 3 and the corresponding controller PWM order is 3, 1 and 2. Initially, the boost

converter started with load 25Ω and at the time 2.52msec EMMSAC identified load

is corresponding to model-2, at 3msec time instant controller is activated controller-2

duty cycle 0.69. At time instance 50msec boost converter load changed from 25Ω to 8Ω.

At 50.55msec EMMSAC identified as model-1 and 51msec controller-1 duty cycle 0.515



is activated. Finally, the load resistance is changed from 8Ω to 55Ω at 100msec time

instance and EMMSAC identified as model-3 at 101.4msec time instance and activated

the controller-2 PWM at the 102msec time instance. The output voltage and duty

cycle plots are shown in Figure 5.7 due to the wrong controller activation, the output

voltage is not regulated to targeted voltage however, model identification is performed

accurately.

5.4 Two model based real time model identification

This experiment aims to investigate the performance of model identification when the

system running with completely two opposite models. The detailed block diagram is

given Figure 5.1. The LTV model identification presented in Chapter 4 is reused in the

estimator set. DKF Model-1 is running with Hp1=[0, 1] and DKF model-2 is running

with Hp2=[0, -1]. The measured boost converter output voltage (Vmeasured) is given to

the model identification unit. Boost converter specifications:

Input voltage=5V

Inductance L = 326uH

Capacitance C = 204uF

Diode forward resistance RDS = 0.2

Inductor internal resistance RL = 0.3ohm

Operating frequency fpwm = 10kHz

Target output voltage Vref = 10V

The experimental setup block diagram is shown in Figure 5.8, by using ADC boost con-

verter output voltage is sampled at the rate of 0.2MHz and PWM value is generated by

using DAC module. The filter bank is operated at a frequency of fclk = 2MHz, FPGA

is communicated by using Vivado tool with JTAG cable at a frequency of 500kHz. A

dip switch on FPGA is used to change the physical system sign. The integrated logic

analyser is used to collect the computed data from FPGA. The real-time experimental

setup is shown in Figure 5.9 which shows FPGA and boost converter along with AD-

C/DAC interconnections. A detailed description of each block is given in the following

subsections.

5.4.1 ADC implementation on VCU118 FPGA using AD7476A

The real-time boost converter output voltage is sampled by using the ADC IC AD7476A

(12bit) used for analog to digital conversion. AD7476A is a successive approxima-

tion ADC, the input and output pins of AD7476A and FPGA interfacing pins are

shown in Figure 5.10. FPGA PMOD female head (J52) pins-0, 1, 2, 3, GND and Vcc

are used for connecting the ADC. Since it is a two-channel ADC, it has 2 analog in-

puts (Analog1, Analog2), the node which we are intended to measure its voltage is to


Figure 5.8: Block diagram of the experimental setup

Figure 5.9: Real-time experimental setup

be connected to Analog1orAnalog2. The ADC operating voltage range is 2.2V to 3.3V,

therefore we need to use a voltage divider. In these experiments, R1 = 10kΩ and

R2 = 2.2kΩ are used for the voltage divider, voltage is measured between the 2.2kΩ and

ground.

The communication between ADC and FPGA is established by using the serial periph-

eral interface (SPI) protocol. Handshaking is involved based on the signals chip select

(CS) and system clock (Sclk). The detailed timing diagram is given in Figure 5.11.



ADC

Analog1

GND

Analog2

GND

GND

Vcc

GND

Vcc

Sclk

Input

Data1

Data2

CS

Output

Vcc

FPGA PMODFemale Head(J52)GND

0

1

2

3

Figure 5.10: ADC input/output pin details

Figure 5.11: ADC timing (Source: AD7476A data sheet [4])

Based on this timing diagram a state machine based SPI protocol RTL code was de-

veloped. The detailed readings for input voltage 0.25V to 3.25V is given in Table 5.5.

This module took 28 clock cycles for each conversion. The implemented design utilized

30 LUT’s and 65 FF’s on FPGA.

5.4.2 DAC implementation on VCU118 FPGA using AD7303

In general control signals generated by the hardware control unit are in the digital

domain, these signals must be converted into the analog domain to control the physical

system. Therefore, analog devices 8-bit DAC AD7303 was used in these experiments to

convert digital data into analog. The input-output pin and interfacing with the FPGA

diagram are shown in Figure 5.12. To connect DAC module top FPGA PMOD male

head (J53) pins-4, 5, 6, 7, GND and Vcc are used.


Table 5.5: ADC module output data (Input range 0v-3.3v and output range0-4096)

Input Voltage (V) ADC data

0.25 310

0.5 620

1 1241

1.25 1551

1.5 1861

1.75 2174

2 2482

2.5 3102

3 3723

3.25 4033

DAC

Analog1a

Analog1b

GND GND

Vcc

Sclk

Input

Data1

Data2

CS

Output

Analog2a

Analog2a

VccVcc

FPGA PMODmale Head(J53)

GND

4

5

6

7

Figure 5.12: DAC input/output pin details

Figure 5.13: Timing digram of DAC AD7303 (Source AD7303 data sheet [5] ).

The communication between DAC and FPGA is established by using the serial peripheral

interface protocol. Handshaking is involved based on the signals CS and Sclk. The

detailed timing diagram is given in Figure 5.13. This module took 18 clock cycles to

convert 8-bit data.



5.4.3 Moving Average Filter

Ma(n) =ad(n) + ad(n− 1) + ad(n− 2) + ad(n− 3)

4(5.5)

The measured output voltage must be filtered before sending it to the MMAE unit. The

filtering step is performed using a simple four tap moving average (MA) filter (given

in equation 5.5), where ad is ADC 12-bit output data. This filter removes the noise

introduced by ADC. This architecture is shown in Figure 5.14 and coded in Verilog and

it is utilized 35 LUT’s and 82 FF’s on VCU118 FPGA.

n n-2 n-3

++

+

n-1

Shift RegisterADC data

>>2 >>2

Output

Figure 5.14: Proposed moving average filter architecture

5.4.4 PWM signal generator

Counterclk Comparator

PWMin

DAb ‘1 Comparator

Reset

DAb ‘0 DAC module inputMax count

1

0

Figure 5.15: Proposed PWM signal generation architecture

In this work, a counter-based PWM is implemented, the design mainly uses a counter

and comparator. The count value is compared with reference PWMin in every clock

cycle, the output of the comparator is given to a mux to send output either zero or

one as shown in Figure 5.15. The second comparator is responsible to reset the count

value after reaching the maximum count. In Figure 5.15, DAb is the DAC module bit

length, max count is used to adjust the PWM signal frequency and PWMin is used

for changing the pulse width of PWM signal. The counter is set to reset when the

count reaches the max count value. It is be noted that the DAC module is an 8-bit I/O


module, so to generate the logic high signal, the design sent all 8-bits as ones and zero

to generate logic zero signal. The implemented design utilised 37 LUT’s and 30 FF’s on

FPGA.

5.4.5 Obtained results

Table 5.6: Real-time closed loop model identification time for various load re-sistance values

Load resistance (Ω)System 1 to 2 System 2 to 1no. of samples Time (msec) no. of samples Time (msec)

33 62 0.31 64 0.32

40 64 0.32 65 0.32

50 64 0.32 63 0.31

60 63 0.31 64 0.32

68 63 0.31 63 0.31

89 61 0.30 64 0.30

100 62 0.31 63 0.31

Average time 0.31 0.31

0 2000 4000 6000 8000 10000 12000-15

-10

-5

0

5

10

15

Vol

atge

Measured and estimated voltage for load 33ohm

0 2000 4000 6000 8000 10000 12000

Time (0.005msec)

-15

-10

-5

0

5

10

15

Vol

atge


V1

V2

Vmeasured

Figure 5.16: Plot to show the real-time measured and estimated voltages forthe model identification when model changed from system-1 to system-2, whereVmeasured represents the measured boost converter output voltage, V1 representsestimated voltage by model-1 and V2 represents estimated voltage by model-2

To validate the performance of the two model based model identification, experiments

were conducted under various Rload conditions. Estimated and measured voltage plots

are shown in Figure 5.16 and 5.17 for load resistance 33Ω when system changed 1 to



0 2000 4000 6000 8000 10000 12000-15

-10

-5

0

5

10

15

Vol

atge


0 2000 4000 6000 8000 10000 12000

Time (0.005msec)

-15

-10

-5

0

5

10

15

Vol

atge


V1

V2

Vmeasured

Figure 5.17: Plot to show the real-time measured and estimated voltages for themodel identification when the model changed from system-2 to system-1. whereVmeasured represents the measured boost converter output voltage, V1 representsestimated voltage by model-1 and V2 represents estimated voltage by model-2

6400 6450 6500 6550 6600 6650 6700 6750 68000

100

200

300

400

Volt

age

Residuals

R1

R2

6400 6450 6500 6550 6600 6650 6700 6750 6800Time (0.005msec)

1

1.5

2

Model

num

ber

Model identification

IMOM

Figure 5.18: Residuals and model identification plots with load resistance 33Ω,when the system changed from 1 to 2. At time instance 32.77msec systemchanged from 1 to 2, after 0.31msec time EMMSAC identified the change inmodel


6400 6450 6500 6550 6600 6650 6700 6750 68000

100

200

300

400

Vol

tage

Residuals

R1

R2

6400 6450 6500 6550 6600 6650 6700 6750 6800Time (0.005msec)

1

1.5

2

Mod

el n

umbe

r

Model identification

IMOM

Figure 5.19: Residuals and model identification plots with load resistance 33Ω,when the system changed from 2 to 1. At time instance 32.77msec systemchanged from 1 to 2, after 0.32msec time EMMSAC identified the change inmodel

2 and 2 to 1 respectively. It is observed that in all cases DKFs are achieving 99%

estimation accuracy.

Furthermore, to show the model identification performance for the 33Ω load resistance,

the time difference between system switch and EMMSAC identification and the number

of samples taken by EMMSAC for model identification when EMMSAC switched from

system-1 to system-2 and system-2 to system-1. Residuals and model identification are

plotted in Figure 5.18, at time 32.77msec system changed from 1 to 2, residuals of model-

1 started increasing and after 62 samples or 0.31msec time model-2 residuals crossed

the model -1 residuals and model identification output also changed. Residual and

model identification plots when the system changed from 2 to 1 is shown in Figure 5.19.

Similarly, the system changed from 2 to 1 at 32.77msec and it is identified at 33.09msec

time, it has taken 64 samples. Similarly, for the remaining cases, model identification

time and the number of samples are tabulated in Table 5.6. The corresponding graphs

for each load resistance were also plotted in Figure 5.20, when the physical system

changed from 1 to 2 and in Figure 5.21 when the physical system changed from 2 to

1. The average model identification time when the system switched from 1 to 2 is

0.313msec and from 2 to 1 it is 0.318msec time. It is to be noted that the main aim of

these experiments is to validate the real-time model identification performance i.e. how

quickly change in the physical system is identified by the proposed architecture. For

example, when the physical system switched from system-1 to system-2, it is identified



Figure 5.20: Plots to show the time difference between the original model (OM)and identified model (IM) when physical system changed from 1 to 2 underload resistance Rload 33Ω, 40Ω, 50Ω, 60Ω, 68Ω, 89Ω and 100Ω. Model iden-tification time 0.32, 0.32, 0.31, 0.32, 0.31, 0.32 and 0.31msec respectively foraforementioned load resistances

within 0.31msec time as shown in Figure 5.18. If the change in the physical system

is not identified, the identified model number in Figure 5.18 would have not changed

from model 1 to 2. Therefore from these experiments, it is concluded that the proposed

architecture could identify the model.

5.5 Discussion

This chapter presented the multiple model adaptive estimation based controller for the

DC−DC boost converter. A model identification scheme is implemented to identify a


Figure 5.21: Plots to show the time difference between the original model (OM)and identified model (IM) when physical system changed from 1 to 2 underload resistance Rload =33Ω, 40Ω, 50Ω, 60Ω, 68Ω, 89Ω and 100Ω. Model iden-tification time 0.31, 0.32, 0.32, 0.31, 0.31, 0.30 and 0.31msec respectively foraforementioned load resistances

boost converter model under load resistance uncertainties. This is the first attempt to

use the EMMSAC for power electronic applications. It was shown that the EMMSAC

significantly improves the closed-loop output voltage response time and settling time

when compared to PID controller and it is demonstrated by the simulation results by

changing the load resistance of the boost converter abruptly. It is identified that the

EMMSAC method control time averagely improved by 10 times for a smaller change in

load and 20 times improvement for a larger change in load. Due to improved closed-loop

timing performance and the results of the proposed simulation will enable the use of

EMMSAC for wider applications such as applications photovoltaic (PV) power systems



[41], offshore wind turbines (OWT) [42], electric/ hybrid electric/ plug-in-hybrid elec-

tric/ fuel cell vehicles (EV/ HEV/ PHEV/ FCV) [43], medium-voltage DC (MVDC)

and high-voltage DC (HVDC) power systems [44, 45], telecommunication power supply

[46], on shipboard power system [47], dc motor drives, personal computers, home appli-

ances, and portable electronic e.t,c [48, 49]. It is also worth noting that the structure

of the proposed controller is quite generic and the potential advantages of the proposed

methodology demonstrated by simulation results will enable the use of EMMSAC for

other existing DC-DC converters and power electronics applications.

Chapter 6

Conclusion and Future Directions

Applications of multiple model adaptive estimation based controllers are emerging in

cyber-physical systems, due to their improved performance over conventional methods

such as non-adaptive and optimal control methods. Recently proposed estimation-based

multiple-model switched adaptive control is one such method in which a closed-loop con-

troller is activated based on the model identification outcome. The vital bottleneck limit-

ing the EMMSAC applicability in the real-time resource-constrained embedded platform

is its computationally intensive nature. The most computational complexity is associ-

ated with the model identification part of EMMSAC, which build upon the bank of

Kalman filters. Therefore, a dedicated hardware architecture can overcome the limita-

tions of state-of-the-art serial hardware-based implementation [26, 27]. Motivated by

these factors, this thesis investigated the MMAE based model identification architec-

ture and its validation on FPGA for larger number models to overcome the existing

DSP implementation trade-off between the resources and execution time.

This thesis presented the hardware architectures for LTI and LTV model identification

scheme based on the MMAE algorithm and its validation on autonomous vehicle and

boost converter applications respectively. Furthermore, MMAE based closed-loop con-

trol simulation results for boost converter were also presented. The proposed architecture

broadens the use of the MMAE to real-time applications such as fault detection-isolation,

power electronics, airspace, gas turbains, nuclear reactors, and robotics.

The detailed information about contributions given below.

• The hardware architecture for parallel implementation of the multiple model adap-

tive estimation based linear time-invariant model identification and its validation

with an auto-mobile application is presented. It was shown that by reusing the

multipliers and reducing the number of multiplications in the filter banks of the

MMAE algorithm, we could save significant amount of hardware resources. The

architecture has been implemented using FPGA for 16, 32 and 64 filter banks

117

118 Chapter 6 Conclusion and Future Directions

as part of position and velocity estimations of autonomous auto-mobile applica-

tion. It has been found theoretically up to 78% reduction in multiplications is

possible, which translates to the reduction of 39% LUTs, 13% FFs, 27% DSPs,

and 43% power reduction when compared with the directly mapped architecture

(without multiplications reduction and reusable multipliers) at 100MHz operating

frequency. This work justifies the first research objective.

• The second part of this thesis, presented the linear time-variant cyber-physical

system model identification architecture based on multiple model adaptive esti-

mation algorithm, using eight and four multipliers in the estimator filter bank.

Resource utilization of the FPGA implementation of the proposed architecture

are reported for 16, 32, 64, 128, 190 and 256 models and demonstrated its area

and power efficiency. It has been found that using four multipliers in estimator

filter bank, 17% LUTs, 14% FFs, 50% DSPs resource and 32% power consumption

reduction possible when compared with an eight-multiplier version at 100MHz op-

erating frequency with the penalisation of model identification time. The proposed

architecture is validated using the DC-DC boost converter with load resistance as

an uncertainty parameter, it is generic and scalable to any filter bank size. This

architecture is suitable to use in real-time resource-constrained edge computing

embedded and cyber-physical systems at high execution speed. This work enables

the applicability of LTV model identification to large uncertainty systems. This

work justifies the second research objective.

• The third part of this thesis presented an investigation of the applicability of the

EMMSAC algorithm for the boost converter. The EMMSAC algorithm signifi-

cantly improved the closed-loop output voltage response time and settling time

when compared PID controller and it is demonstrated by the simulation results by

changing the load resistance of boost converter abruptly. It is also identified that

the EMMSAC method control time averagely improved by 10 times for smaller

load changes and 20 times improvement for larger load changes. Due to improved

closed-loop timing performance, the simulations results will enable the use of the

EMMSAC for wider applications such as DC micro-grid systems for regulating

output voltage and in photovoltaic battery charge system to improve efficiency

under abrupt load change conditions. It is also worth noting that the structure

of the proposed controller is quite generic and potential advantages of the pro-

posed the methodology demonstrated by simulation results will enable the use of

the EMMSAC for other existing DC-DC converters. Furthermore, the real-time

implementation of two model-based model identification using real-time boost con-

verter and its implementation details are discussed in details along with obtained

results. It is also shown that the proposed implementation is able to identify sys-

tem changes in msec order time. This work justifies the third research objective.

Chapter 6 Conclusion and Future Directions 119

Each contribution in this thesis has been substantiated with several experiments

and underlying benefits of proposed FPGA based architectures such as low power,

area and cost promote the industrial adoption of complex EMMSAC in new

resource-constrained applications such as power electronics, fault detection and

isolation for power electronics devices and batteries, state of charge estimation

for batteries, high-speed train control, gas turbine control, and nuclear power

plants control. The EMMSAC based products for wearable battery-based resource-

constrained health care application FES [27], fault detection and isolation can be

developed in near time. Future research challenges, as will be discussed next, will

motivate researchers to investigate further in these fields.

6.1 Future Work

The following subsections overview the future research challenges identified by the re-

search study undertaken in this thesis.

6.1.1 Closed loop hardware implementation of EMMSAC

The potential future work is closed-loop hardware implementation of EMMSAC, i.e. the

continuation of chapter five into a full hardware implementation of the closed loop for

investigation of large numbers of models in the full closed-loop (i.e. beyond simulation)

and showing the closed-loop timing performance improvement. Thereby the EMMSAC

can be used to other real-time applications such as photovoltaic (PV) power systems

[41], offshore wind turbines (OWT) [42], electric/hybrid vehicles [43], medium-voltage

DC (MVDC) and high-voltage DC (HVDC) power systems [44, 45], telecommunication

power supply [46], and shipboard power systems [47].

6.1.2 An investigation to MMAE reconfigurable architecture with par-

ticular focus on exploring trade-offs between the architecture use

of resources area and time

Table 6.1: Resource utilization for single 2nd order model on FPGA. LTI= lineartime-invariant, LTV= linear time-variant

Resource type LTI LTV

LUT 1085 1583

FF 937 618

DSP 16 36

120 Chapter 6 Conclusion and Future Directions

Table 6.2: Possible approximate number of second order LTV models on variousFPGA boards

BoardPossible numberof LTVmodels

Available LUT DSP

VCU118 197 1182k 6840

Zynq-7000 (Z-7100) 56-65 444k 2020

Kintex-7 (XC7K480T) 53-60 477k 1920

Artix-7 (XC7A200T) 20-25 215k 740

Spartan-7 (XC7S100) 4-7 102k 160

Spartan-6 (XC6SLX75) <5 74k 132

The next-generation CPS applications are going to operate in the open environment on a

larger scale, uncertainties and external disturbances are inevitable. For example, appli-

cations like FES for old population [27] and next-generation air transportation systems

[134] need a large number of models to cover the physical system uncertainty levels. So

1

50

100 200150 500450400

120

50

60 70 80

Stage -1

Stage -2

Stage -370 8371 72 8273

110

Figure 6.1: Illustration of reconfigurable multiple model adaptive estimation

there will always be a demand for more models as accuracy demand increases. From

chapter 3 linear time-invariant and chapter 4 linear time-variant model identification

architecture resource utilization given in Table 6.1. For instance to implement a 500

number of models for the LTI system need 542.5k LUT’s, 468.5k FF’s and 8k DSP’s

are required, if the order of model increase, hardware resources utilization also increases

drastically [135]. Even the high-end FPGA available in today’s market (VCU118) can

accommodate approximately 190-second order LTV models. On a resource-constrained

cyber-space, it is far from possible to accommodate these many resources. The number

of models implemented would be even less on a lower end FPGA board, the detailed list

also given in Table 6.2. So, there is a strong requirement of procedure and architecture,

that would use fewer resources for accommodating more number of models.

Therefore, an alternative solution is to investigate a reconfigurable architecture, such

that by using resources of 10s of models, architecture should be able to identify the exact

model matching the physical system. Another envisaged benefit of this method is the

Chapter 6 Conclusion and Future Directions 121

utilization of lower end FPGA board such as Artix-7, Zynq-7000 and Spartan-7 boards

for implementing a higher number of models. This also enables the implementation of

EMMSAC on CPS limited computational resourced edge devices [136].

An initial investigation of the reconfigurable algorithm is described in [2] however, to

date, there is no attempt made for implementing this architecture on any hardware

platform. Further investigation can be made on a reconfigurable hardware architecture

for EMMSAC. This can be performed by reusing the smaller number (10s) of models

by changing their state-space matrices in several iterations. The detailed procedure of

reconfigurable architecture for 500 models case is explained as follows. In the initial

stage, each model is spaced to cover the uncertainty of 50 models so that it need have a

hardware resource required for 10s of models, it is represented as stage one in Figure 6.1.

For suppose minimum residuals are identified near to model 75, then stage-1 models are

updated with new state-space matrices physical system between the uncertainty range

50-120, this is considered as the second stage. Based on the minimum residuals obtained

in the second stage (shown in Figure 6.1), again it updates the state-space matrices near

to obtained uncertainty range, which is stage-3 in Figure 6.1. Based on the residuals

obtained in the third stage, it selects the best model which matches the physical system

then the corresponding controller will be activated in a closed-loop.

6.1.3 EMMSAC based controller for Buck converter

Switch mode DC−DC buck converters are widely used in a variety of applications, rang-

ing from dc motor drives, personal computers, home appliances, and portable electronic

devices [137, 49]. All of these applications require efficient and cost-effective dynamic

and steady-state voltage or power regulation over a wide range of operating conditions.

Traditionally, pre-designed PID controllers are applied to achieve the required dynamic

performance in these systems. However, poor knowledge of the power converter param-

eters may cause inaccuracies in the controller design. Moreover, unpredicted behaviours

such as sudden load variations, components ageing, noise, and unpredictable changes

in operating mode may degrade the controller performance and can lead to instability

within the entire system [138, 139]. Therefore, to overcome the aforementioned problems

an EMMSAC based controller for a DC-DC buck converter is to be investigated.

Appendix A

FPGA implementation SDC file

# ################################################################

# LEDs

# ################################################################

set_property PACKAGE_PIN AT32 [get_ports led [0]]

set_property IOSTANDARD LVCMOS12 [get_ports led [0]]

set_property PACKAGE_PIN AV34 [get_ports led [1]]


set_property PACKAGE_PIN AY30 [get_ports led [2]]


set_property PACKAGE_PIN BB32 [get_ports led [3]]


set_property PACKAGE_PIN BF32 [get_ports led [4]]


set_property PACKAGE_PIN AU37 [get_ports led [5]]


set_property PACKAGE_PIN AV36 [get_ports led [6]]


set_property PACKAGE_PIN BA37 [get_ports led [7]]


#clk

# ###############################################################

# Clock

# ###############################################################

create_clock -period 10.000 -name clk_n [get_ports clk_n]

create_clock -period 10.000 -name clk_p [get_ports clk_p]

set_property IOSTANDARD DIFF_SSTL12 [get_ports clk_n]

set_property PACKAGE_PIN D12 [get_ports clk_n]

set_property PACKAGE_PIN E12 [get_ports clk_p]

set_property IOSTANDARD DIFF_SSTL12 [get_ports clk_p]

123

124 Appendix A FPGA implementation SDC file

# ################################################################

# ADC

# ################################################################

#PMoD 0-1-2-3

set_property PACKAGE_PIN AY14 [get_ports " AD_CS "]

set_property IOSTANDARD LVCMOS12 [get_ports " AD_CS "]

set_property PACKAGE_PIN AY15 [get_ports "AD0 "]

set_property IOSTANDARD LVCMOS12 [get_ports "AD0 "]

set_property PACKAGE_PIN AW15 [get_ports "AD1 "]

set_property IOSTANDARD LVCMOS12 [get_ports "AD1 "]

set_property PACKAGE_PIN AV15 [get_ports "AD_Sclk "]

set_property IOSTANDARD LVCMOS12 [get_ports "AD_Sclk "]

# ################################################################

# DAC

# ################################################################

#PMOD Side B for DAC

set_property PACKAGE_PIN P29 [get_ports "DA_SYNC "];

set_property IOSTANDARD LVCMOS12 [get_ports "DA_SYNC "]

set_property PACKAGE_PIN L31 [get_ports "DA0 "]

set_property IOSTANDARD LVCMOS12 [get_ports "DA0 "]

set_property PACKAGE_PIN M31 [get_ports "DA1 "]

set_property IOSTANDARD LVCMOS12 [get_ports "DA1 "]

set_property PACKAGE_PIN R29 [get_ports "DA_Sclk "]

set_property IOSTANDARD LVCMOS12 [get_ports "DA_Sclk"]

set_property PACKAGE_PIN B17 [get_ports reset_in]

set_property IOSTANDARD LVCMOS12 [get_ports reset_in]

set_property PACKAGE_PIN D21 [get_ports S0] ;# Bank 72 VCCO - VCC1V2_FPGA -

IO_T3U_N12_72

set_property IOSTANDARD LVCMOS12 [get_ports S0] ;# Bank 72 VCCO - VCC1V2_FPGA -

IO_T3U_N12_72

set_property PACKAGE_PIN J16 [get_ports "S1"] ;# Bank 73 VCCO - VCC1V2_FPGA -

IO_L7N_T1L_N1_QBC_AD13N_73

set_property IOSTANDARD LVCMOS12 [get_ports "S1"] ;# Bank 73 VCCO - VCC1V2_FPGA -

IO_L7N_T1L_N1_QBC_AD13N_73

Appendix B

Boost converter circuit parameter

comparison

Table B.1: Boost converter circuit parameter and load range comparison withthe state-of-the-art designs

Work Year ConverterCircuitparameters

Load (Ω) Vin(V ) Vo(V )

ahmeid et al.[140]

2017 Buck

L = 220uHRL=63m ΩC = 330uFRc = 25m Ω

1, 5 10 3.3

oucheriah et al.[141]

2017 BoostL = 18uHC = 450uF

140, 25 7.5 12

Li et al.[142] 2017 BoostL=1mHC = 1000uF

10, 5, 2.5 12 15 and 20

renaudineauet al. [137]

2015 BoostL = 0.6mHC = 1mF

50, 100 48V 100V

tong et al. [143] 2015 Boost

L = 120uHRL = 250mΩC = 75uFRc = 50m Ω

16, 24 6 12

linares et al. [144] 2014 BoostL = 4mHC = 470uF

89, 38 15 and 24

karamanakoset al.[145]

2013 BoostL = 450uHC = 220uF

7636.5

10 15

Proposed 2019 Boost

L = 330 µ H,RL = 0.3 Ω,RD=0.1ΩCo = 220 µF

7 to 90 5 10

125

126 Appendix B Boost converter circuit parameter comparison

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

105

0

5

10

15

Vo

ltag

e(V

)

vout

EMMSAC

v out

PID

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2Time (us) 105

0.3

0.4

0.5

0.6

0.7

PW

M

EMMSAC PWMPID PWM

Figure B.1: Comparison between the proposed methodology and PID con-troller in-terms boost converter out voltage and PWM duty cycle, when loadchanges from 30Ω to 8Ω and 8Ω to 60Ω. Benchmark-A1: Rload=8Ω (Model -1),Rload=30Ω (Model-2), Rload=60 Ω (Model-3). Total simulation time 0-200msec,initially boost converter stared with load 30Ω, at time instance 50msec loadchanged to 8Ω and at 100msec load changed to 60Ω

Appendix B Boost converter circuit parameter comparison 127

0 1 2 3 4Time (0.005msec) 104

0

0.5

1

1.5

2

Res

idua

ls

105 Window 100

R1

R2

R3

0 1 2 3 4Time (0.005msec) 104

0

1

2

3

4

Res

idua

ls

105 Window 200

R1

R2

R3

0 1 2 3 4Time (0.005msec) 104

0

2

4

6

Res

idua

ls

105 Window 300

R1

R2

R3

0 1 2 3 4Time (0.005msec) 104

0

2

4

6R

esid

uals

105 Window 400

R1

R2

R3

0 1 2 3 4Time (0.005msec) 104

0

2

4

6

Res

idua

ls

105 Window 500

R1

R2

R3

0 1 2 3 4Time (0.005msec) 104

0

2

4

6

8

Res

idua

ls

105 Window 1000

R1

R2

R3

Figure B.2: Residuals plots for 3 model EMMSAC based boost converter.Where Rn represents the residuals for model n. Rload=8Ω (Model-1), Rload=30Ω(Model-2), Rload=60 Ω (Model-3). Total simulation time 0-200msec, initiallyboost converter stared with load 30Ω, at time instance 50msec load changed to8Ω and at 100msec load changed to 60Ω

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