Hadallia Bergeron, Vinod K. Sangwan, Julian J. McMorrow ...bedzyk.mccormick.northwestern.edu/files/publications/215_12E4975064.pdf · 230eV is consistent with the Mo4þ formal oxidation

Chemical vapor deposition of monolayer MoS2 directly on ultrathin Al2O3 for low-power electronicsHadallia Bergeron, Vinod K. Sangwan, Julian J. McMorrow, Gavin P. Campbell, Itamar Balla, Xiaolong Liu,Michael J. Bedzyk, Tobin J. Marks, and Mark C. Hersam

Citation: Appl. Phys. Lett. 110, 053101 (2017); doi: 10.1063/1.4975064View online: http://dx.doi.org/10.1063/1.4975064View Table of Contents: http://aip.scitation.org/toc/apl/110/5Published by the American Institute of Physics

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Chemical vapor deposition of monolayer MoS2 directly on ultrathin Al2O3

for low-power electronics

Hadallia Bergeron,1 Vinod K. Sangwan,1 Julian J. McMorrow,1 Gavin P. Campbell,1

Itamar Balla,1 Xiaolong Liu,2 Michael J. Bedzyk,1,2,3 Tobin J. Marks,1,4

and Mark C. Hersam1,2,4,5,a)

1Department of Materials Science and Engineering, Northwestern University, Evanston, Illinois 60208, USA2Applied Physics Graduate Program, Northwestern University, Evanston, Illinois 60208, USA3Department of Physics and Astronomy, Northwestern University, Evanston, Illinois 60208, USA4Department of Chemistry, Northwestern University, Evanston, Illinois 60208, USA5Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, Illinois60208, USA

(Received 12 October 2016; accepted 17 January 2017; published online 30 January 2017;

publisher error corrected 31 January 2017)

Monolayer MoS2 has recently been identified as a promising material for high-performance electron-

ics. However, monolayer MoS2 must be integrated with ultrathin high-j gate dielectrics in order to

realize practical low-power devices. In this letter, we report the chemical vapor deposition (CVD) of

monolayer MoS2 directly on 20 nm thick Al2O3 grown by atomic layer deposition (ALD). The quality

of the resulting MoS2 is characterized by a comprehensive set of microscopic and spectroscopic tech-

niques. Furthermore, a low-temperature (200 �C) Al2O3 ALD process is developed that maintains

dielectric integrity following the high-temperature CVD of MoS2 (800 �C). Field-effect transistors

(FETs) derived from these MoS2/Al2O3 stacks show minimal hysteresis with a sub-threshold swing

as low as �220 mV/decade, threshold voltages of �2 V, and current ION/IOFF ratio as high as �104,

where IOFF is defined as the current at zero gate voltage as is customary for determining power

consumption in complementary logic circuits. The system presented here concurrently optimizes

multiple low-power electronics figures of merit while providing a transfer-free method of integrat-

ing monolayer MoS2 with ultrathin high-j dielectrics, thus enabling a scalable pathway for

enhancement-mode FETs for low-power applications. Published by AIP Publishing.[http://dx.doi.org/10.1063/1.4975064]

Recently, two-dimensional (2D) semiconducting materi-

als have attracted significant interest for high-performance

electronic applications.1,2 Among the 2D transition metal

dichalcogenides (TMDs), MoS23,4 has been specifically identi-

fied as a promising candidate for low-power devices.5–8 MoS2

field-effect transistors (FETs) exhibit high room-temperature

field-effect mobilities (30–480 cm2/Vs),9–13 high current on/

off ratios (108–109),14,15 and low sub-threshold swings (SS)

(�70 mV/decade).8 Moreover, the realization of large-area

synthesis of monolayer MoS2 via chemical vapor deposition

(CVD)16–18 and metal-organic CVD (MOCVD)13 provides a

pathway to wafer-scale TMD-based circuitry.

The synthesis and processing of new materials for low-

power electronics is guided by key transistor figures of merit

such as threshold voltage VTH, sub-threshold swing SS, and

current ION/IOFF ratio.1,6,19 For modern complementary

metal-oxide-semiconductor (CMOS) digital electronics, low

power consumption is enabled by enhancement-mode devi-

ces that have minimal off-current at zero gate bias (i.e., IOFF

is defined as the current at gate voltage VG¼ 0 V).1,20 The

CMOS ION/IOFF ratio is a relevant low-power electronics

metric that evaluates device performance while taking into

account the standby power consumption. The optimization

of CMOS performance metrics is achieved by integrating

appropriately doped semiconducting materials with high-j

ultrathin dielectrics. However, this integration remains a

challenge for low-dimensional semiconducting TMDs.

Thus far, most MoS2 FETs have been integrated with ultra-

thin high-j materials as a top-gate dielectric,21–24 or by

transferring MoS2 onto dielectric substrates.8,25 MOCVD

growth of MoS2 on Al2O3 and HfO2 has also been achieved,

but this approach requires a large thermal budget with over

20 h of high temperature processing.13 Recently, Kim et al.demonstrated MoS2/high-j dielectric FETs by transferring

micromechanically exfoliated MoS2 onto 50 nm thick

Al2O3 grown by atomic layer deposition (ALD), resulting

in mobilities >30 cm2/Vs, ION/IOFF ratios >103, and sub-

threshold swings of �70 mV/decade.8 However, microme-

chanical exfoliation of MoS2 is not suited for large-area

processing.

Overall, current methods of depositing high-j materials

as a top-gate dielectric on MoS2 or transferring CVD MoS2

onto dielectric substrates suffer from several limitations

including lack of control over MoS2 doping, loss of MoS2

structural integrity, and contamination from transfer residues.

For example, the growth of high-j dielectrics on top of MoS2

strongly increases electron doping and induces large negative

shifts in VTH, which significantly increase CMOS power con-

sumption.22,26,27 Meanwhile, transfer processes lead to not

only structural defects and wrinkles in MoS2 but also uncon-

trolled doping from processing residues.9,28,29 Thus, while the

integration of MoS2 with high-j dielectrics has been under-

taken in previous work,30,31 a scalable transfer-free pathway

a)Author to whom correspondence should be addressed. Electronic mail:

[email protected]

0003-6951/2017/110(5)/053101/5/$30.00 Published by AIP Publishing.110, 053101-1

APPLIED PHYSICS LETTERS 110, 053101 (2017)

for doping-controlled enhancement-mode devices remains chal-

lenging for CVD-grown MoS2/high-j dielectric heterostructures.

In this letter, we overcome these issues and report the

direct CVD growth of monolayer MoS2 on 20 nm thick

ALD-derived Al2O3. The resulting MoS2/Al2O3 heterostruc-

tures are characterized with a suite of microscopy and spec-

troscopy techniques including scanning electron microscopy

(SEM), atomic force microscopy (AFM), X-ray photoelec-

tron spectroscopy (XPS), photoluminescence (PL) spectros-

copy, and Raman spectroscopy. Furthermore, the integrity of

the dielectric following CVD growth is verified with X-ray

reflectivity (XRR) and capacitance-voltage (C-V) measure-

ments. The high-quality interface between the MoS2 and

Al2O3 results in FETs with a CMOS ION/IOFF ratio up to

104, sub-threshold swing as low as 220 mV/decade, and

enhancement-mode threshold voltage of �2 V. This overall

set of device metrics for transfer-free FETs represents a sig-

nificant improvement over the literature precedent with

direct implications for low-power electronics.

The CVD growth of monolayer MoS2 on ALD Al2O3

was achieved by adapting a procedure previously used for

CVD growth on SiO2/Si substrates.32 Specifically, 20 nm of

Al2O3 was deposited by ALD at 200 �C on Piranha-cleaned

Si, after which the Al2O3/Si substrate was placed down-

stream of the MoO3 and sulfur source boats under an argon

gas flow rate of 25 sccm and a pressure of 150 Torr (see sup-

plementary material for details). Figures 1(a) and 1(b) pre-

sent SEM and optical images, respectively, of the resulting

CVD-grown MoS2 domains. Most of the MoS2 domains pos-

sess lateral edge lengths of �1 to 2 lm with some domains

showing edge lengths up to 20 lm. An AFM topography

image of a single domain (Figure 1(c)) reveals a step height

of 0.72 nm, which is consistent with monolayer MoS2.33 A

Raman spectrum of the CVD-grown MoS2 (Figure 1(d)) fur-

ther corroborates the single-layer thickness of the MoS2. The

MoS2 in-plane (E12g) and out-of-plane (A1g) vibrational

modes were each fit with a Lorentzian function to determine

their spectral locations at 384.7 cm�1 and 404.9 cm�1,

respectively. A difference of 20.2 cm�1 between these modes

is consistent with monolayer CVD MoS2.17,34 The room-

temperature PL spectrum of the MoS2 (Figure 1(e)) exhibits

a pronounced peak at �669 nm and a minor peak at

�620 nm corresponding to the excitonic A and B direct-gap

optical transitions in monolayer MoS2, respectively.33,35,36

Lastly, the chemical composition of the MoS2 is probed

using XPS. The molybdenum core level spectrum is pre-

sented in Figure 1(f). The position of the Mo 3d5/2 peak at

�230 eV is consistent with the Mo4þ formal oxidation state

of MoS2, whereas the minor doublet at higher binding energy

corresponds to MoOx.37,38 The relatively weak intensity of

the MoOx peaks suggests minor MoOx content, as observed

in other MoS2 CVD studies.32,39,40 More characterization

details are provided in the supplementary material.

The effects of the MoS2 growth conditions on the elec-

tronic quality of the 20 nm Al2O3 dielectric were investigated

via metal-insulator-semiconductor (MIS) capacitance-voltage

(C-V) measurements on an Al2O3/Si substrate annealed in a

temperature cycle identical to that of the MoS2 growth process

(Figure S1(a) of the supplementary material). For these meas-

urements, 200 lm� 200 lm metal contact pads (5 nm Ti/

75 nm Au) were patterned over a �1 cm2 area of the annealed

Al2O3/Si substrates via shadow masking. In Figure 2(a), a

histogram of the capacitance values at V¼ 4 V (i.e., accumu-

lation regime for the grounded n-type Si substrate) for

121 devices shows a narrow distribution with an average

value of 328 nF/cm2. The corresponding effective dielectric

constant (jeff) is calculated to be 8.45 (effective silicon oxide

thickness �10.5 nm), which is comparable to as-deposited

ALD Al2O3.41 jeff was calculated using the Al2O3 thickness

measured by XRR (21 nm) (see supplementary material)

and a 1.8 nm thick native silicon oxide.42 Capacitance meas-

urements on an unannealed control substrate of Al2O3/Si

(Figure S3 of the supplementary material) showed an aver-

age capacitance of 332 nF/cm2, indicating that the thermal

cycling did not significantly affect the dielectric quality

(<2% reduction in capacitance). The maximum leakage cur-

rent density between V¼�4 and 4 V was less than 10�6 A/

cm2 for >55% of the MIS capacitors on the annealed sub-

strate (Figure S4 of the supplementary material).

The integrity of the Al2O3 and Al2O3/Si interface was fur-

ther characterized using XRR (see supplementary material).

Previously, XRR has been employed to probe the robustness

and thickness of heterogeneous ultrathin dielectric stacks fol-

lowing chemical treatments.42,43 The depth-dependent

FIG. 1. (a) SEM image of CVD MoS2 grown on ALD Al2O3. (b) Optical

image of CVD MoS2 on ALD Al2O3 (image contrast was digitally enhanced

since interference effects decrease the contrast of the MoS2 domains on the

20 nm Al2O3 substrate in comparison to 300 nm SiO2). (c) AFM topography

image of a single crystal of MoS2. The height of the red line profile across

the flake edge is shown below, where a step edge fit indicates a height of

�0.7 nm, which is consistent with monolayer MoS2.33 (d) Raman spectrum

of the MoS2 with a separation of 20.2 cm�1 between the A1g and E12g

modes, which is consistent with monolayer MoS2.17,34 (e)

Photoluminescence spectrum of the MoS2 shows direct-gap A and B exciton

peaks from monolayer MoS2.33,35,36 (f) XPS spectrum of the Mo 3d core

level of the MoS2.

053101-2 Bergeron et al. Appl. Phys. Lett. 110, 053101 (2017)

electron density profile was extracted by fitting the XRR data

with the parameters in Table S1 (supplementary material).

Figure 2(b) shows the XRR data collected from a sample of

MoS2 directly grown on Al2O3/Si and the corresponding

model fit, while the inset shows the depth-dependent electron

density profile normalized to the electron density of the Si

substrate. From this analysis, the thickness of the Al2O3 layer

after MoS2 deposition is found to be 20.0 6 0.3 nm with the

addition of a 1.83 6 0.08 nm Al2O3/Si interfacial layer

included to achieve the best fit. The presence of similar inter-

facial layers has previously been reported in annealed Al2O3

systems.44,45 A control sample of as-deposited ALD Al2O3/Si

without MoS2 showed a dielectric thickness of 20.7 6 0.1 nm

(Figure S2(b) of the supplementary material), which agrees

well with the sample that underwent MoS2 growth.

To investigate electronic transport properties, field-effect

transistors (FETs) were fabricated on CVD MoS2 grown on

20 nm ALD Al2O3, with the Al2O3 serving as the back-gate

dielectric (schematic shown in Figure 3(a)). Both two-probe

FETs and four-probe van der Pauw devices were studied to

determine the effect of contacts on the transport characteris-

tics. The devices were patterned with electron-beam lithogra-

phy, contact metallization (2.5 nm Ti/ 100 nm Au), and liftoff

processes outlined previously.39 All devices were measured at

25 �C and <5� 10�5 Torr. The output characteristics of a typ-

ical two-probe MoS2-FET (Figure 3(b)) are linear in the low

bias range, which is consistent with previous studies of MoS2

contacted with Ti/Au.14,46 The transfer characteristics of

the same device exhibit a CMOS ION/IOFF ratio >104,

sub-threshold swing � 220 mV/decade, and VTH¼ 2.1 V

(Figure 3(c)). The threshold voltage is defined here as the VG

axis intercept of the extrapolation of the linear region of the

transfer curve. The transfer curve of a four-probe device is

shown in Figure 3(d). The linear field-effect mobility from the

devices was calculated according to the following equation:

l ¼ L

CoxW

dGD

dVG

� �;

where VG and GD are the gate voltage and channel conduc-

tance, respectively. L and W are the channel length and width,

respectively, where the dimensions are defined by the area

enclosed by the inner electrodes 2 and 3 for the four-probe

devices (inset of Figure (3(d)). Cox is the area-normalized

capacitance of the gate-dielectric (328 nF/cm2). Measurements

on two-probe and four-probe devices revealed comparable

field-effect mobilities, indicating that the contact resistance

does not dominate the overall transistor characteristics. The

field-effect mobility of all six measured devices is found to

vary from 0.4 to 4.1 cm2/Vs (extracted at VD� 1 V), in agree-

ment with previous reports for CVD MoS2 mobility.39,47,48

The devices also show low hysteresis in comparison to other

reports on 2D MoS239,49–51 (see Figure 3(c)) where the sweep

direction dependent shift in VTH is �10 mV.

We now consider the specific transistor metrics relevant to

low-power digital electronics applications. Figure 4 shows the

simultaneous improvement in the CMOS ION/IOFF ratio, sub-

threshold swing, and VTH of the FETs in this work in compari-

son with the previous literature for directly grown CVD MoS2

FETs.13,15,16,22,28,36,39,47,50,52–68 Unless explicitly reported in the

FIG. 3. (a) Schematic of a two-probe FET fabricated from monolayer MoS2 on

20 nm ALD Al2O3. (b) Output plots of an FET at different gate voltages, nor-

malized by the device channel width (L¼ 3lm, W¼ 5.2lm). (c) Linear and

semi-log transfer characteristics of the same device at different drain biases,

including forward and backward sweeps (normalized by the device channel

width). (d) Conductance versus gate bias of a four-probe device (normalized by

the device channel width W¼ 7.5lm). The inset shows an AFM phase image

of the four-probe device, with the MoS2 highlighted by the white dashed lines.

The scale bar is 2lm. The conductance G23 was measured between electrodes

2 and 3 while applying a constant current of 10 nA between electrodes 1 and 4.

The conductance did not significantly change for applied currents of 2 nA,

5 nA, and 10 nA.

FIG. 2. (a) Histogram of the capacitance at V¼ 4 V (accumulation regime)

of 121 Au/Al2O3/Si MIS capacitors where the ALD Al2O3/Si substrate

was annealed at CVD growth temperatures (Figure S1(a) supplementary

material). The average capacitance is 328 nF/cm2. (b) XRR data of the CVD

MoS2 on Al2O3/Si, as shown by the red circles. The uncertainty in the XRR

data is less than that encompassed by the data points. The momentum trans-

fer vector is given by Q¼ 4psin(2h/2)/k, with an angle of scattered X-rays

2h and X-ray wavelength k¼ 0.154 nm. The model fit is shown in the blue

line, with the electron density q as a function of depth along the heterostruc-

ture in the inset (normalized to the silicon electron density). The thickness

of the ALD Al2O3 layer is modeled to be 20.0 6 0.3 nm.

053101-3 Bergeron et al. Appl. Phys. Lett. 110, 053101 (2017)

literature, the metrics were extracted from published data using

a figure digitizer. The majority of the recent reports of transfer-

free CVD MoS2 FETs were included in this analysis, excluding

electrochemically gated devices. In particular, we highlight the

CMOS ION/IOFF ratio, where ION is the device current at the

maximum positive gate voltage reported and IOFF is the device

current at VG¼ 0 V. For our devices, the maximum positive

gate voltage ranges from 3 V to 4 V (n¼ 6.2–8.2� 1012cm�2),

and the resulting CMOS ION/IOFF ratio ranges from 102 to 104,

which is a significant improvement over previous work on

CVD MoS2. Furthermore, the low sub-threshold swing of our

devices from 220 to 530 mV/decade and the low VTH from 1.3

to 2.7 V also compare favorably with the literature on CVD

MoS2 FETs.

We attribute the favorable low-power performance of the

present devices to the direct growth of the MoS2 on ALD

Al2O3. The pristine interface between the two materials mini-

mizes the doping variability of transfer methods while main-

taining the low-power advantages of ultrathin high-jdielectrics. The as-grown doping of monolayer MoS2 on

Al2O3 results in enhancement-mode FETs with low-operating

voltages. As shown in Figure 4(b), the ALD growth of ultra-

thin metal oxides on CVD MoS2 has been reported to achieve

low operating voltages in top-gated FET geometries. However,

this approach increases n-type MoS2 doping, often resulting in

depletion-mode transistors (VTH< 0 V) unsuitable for low-

power CMOS applications. Thus, optimization of power con-

sumption metrics (i.e., CMOS ION/IOFF ratio, threshold volt-

age, and sub-threshold swing) in this work is highly relevant to

logic applications for circuits based on 2D semiconductors.

In conclusion, we have demonstrated the direct growth of

monolayer MoS2 on 20 nm ALD Al2O3 using solid precursor

CVD. Both AFM and Raman spectroscopy confirm the

growth of monolayer MoS2. Annealing of the 20 nm ALD

Al2O3 deposited at 200 �C through a CVD temperature cycle

of 800 �C decreases capacitance by <2% in comparison to a

control sample of as-deposited Al2O3/Si. XRR also confirms

that the thickness of the dielectric does not significantly

change after MoS2 deposition. The resulting MoS2 FETs

exhibit high performance in low-power CMOS metrics such

as a CMOS ION/IOFF ratio of 102–104, sub-threshold swing

¼ 220–530 mV/decade, and VTH¼ 1.3–2.7 V with negligible

hysteresis. The low operating voltage enhancement-mode

FETs fabricated from the MoS2 grown on ALD Al2O3 demon-

strate promise for the low-power n-type branch of CMOS in

integrated circuits. The work presented here thus substantiates

the prospect of scalable MoS2/high-j structures for low-

power electronics.

See supplementary material for details on the deposition

of the Al2O3 dielectric and MoS2, additional characterization

of the Al2O3 dielectric, and experimental methods.

This work was performed under financial assistance award

70NANB14H012 from the U.S. Department of Commerce,

National Institute of Standards and Technology, as part of the

Center for Hierarchical Materials Design (CHiMaD). H.B.

acknowledges support from the NSERC Postgraduate

Scholarship-Doctoral Program. V.K.S. acknowledges support

from the 2-DARE program (NSF EFRI-1433510). J.J.M.

acknowledges support from the National Aeronautics and

Space Administration (NASA NSTRF grant NNX12AM44H).

G.P.C. acknowledges support from the Materials Research

Science and Engineering Center (MRSEC) of Northwestern

University (NSF DMR-1121262). I.B. and X.L. acknowledge

support from the Office of Naval Research (ONR N00014-14-

1-0669). The Raman instrumentation was funded by the

Argonne�Northwestern Solar Energy Research (ANSER)

Energy Frontier Research Center (DOE DE-SC0001059). This

work made use of the EPIC and Keck-II facilities of the

NUANCE Center at Northwestern University, which has

received support from the Soft and Hybrid Nanotechnology

Experimental (SHyNE) Resource (NSF NNCI-1542205); the

MRSEC program (NSF DMR-1121262) at the Materials

Research Center; the International Institute for Nanotechnology

(IIN); the Keck Foundation; and the State of Illinois. The XRR

measurements were performed at the Northwestern X-ray

Diffraction Facility, which is supported by the MRSEC and

SHyNE. The authors thank Dr. K.-S. Chen, Dr. J. Wood, Dr. J.

Emery, M. Beck, and S. Wells for valuable discussions.

FIG. 4. (a) A plot of CMOS ION/IOFF ratio versus sub-threshold swing for

the devices from this work in comparison to other directly grown CVD

MoS2 FETs reported in the literature. Reports in which the sub-threshold

swing could not be extracted or exceeded 20,000 mV/decade are not

included. A red star denotes the best device in this work while the red

dashed oval depicts the range in the metrics for the six devices measured.

The black and blue points depict previously reported top-gated and back-

gated devices, respectively. The numbered reference for each point is indi-

cated. (b) A plot of CMOS ION/IOFF ratio versus threshold voltage of the

devices from this work in comparison to other directly grown CVD MoS2

FETs reported in the literature. Reports in which the threshold voltage could

not be extracted or exceeded 45 V are not included. The CMOS ION/IOFF

was calculated with ION as the current at the maximum positive gate voltage

reported for each device and IOFF at VG¼ 0 V.

053101-4 Bergeron et al. Appl. Phys. Lett. 110, 053101 (2017)

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