H8/3664 Series Hardware ManualHardware Manual ADE-602-202B Rev. 3.0 03/22/01 Hitachi, Ltd. Rev. 3.0, 03/01, page ii of xxvi Rev. 3.0, 03/01, Page iii of xxvi Cautions 1. Hitachi neither

Hitachi Single-Chip Microcomputer

H8/3664 Series

H8/3664HD6433664

H8/3663HD6433663

H8/3662HD6433662

H8/3661HD6433661

H8/3660HD6433660

H8/3664F-ZTATTM

HD64F3664H8/3664N

HD64N3664Hardware Manual

ADE-602-202B

Rev. 3.003/22/01Hitachi, Ltd.

Rev. 3.0, 03/01, page ii of xxvi

Rev. 3.0, 03/01, Page iii of xxvi

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’spatent, copyright, trademark, or other intellectual property rights for information contained inthis document. Hitachi bears no responsibility for problems that may arise with third party’srights, including intellectual property rights, in connection with use of the informationcontained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that youhave received the latest product standards or specifications before final design, purchase oruse.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.However, contact Hitachi’s sales office before using the product in an application thatdemands especially high quality and reliability or where its failure or malfunction may directlythreaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclearpower, combustion control, transportation, traffic, safety equipment or medical equipment forlife support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachiparticularly for maximum rating, operating supply voltage range, heat radiation characteristics,installation conditions and other characteristics. Hitachi bears no responsibility for failure ordamage when used beyond the guaranteed ranges. Even within the guaranteed ranges,consider normally foreseeable failure rates or failure modes in semiconductor devices andemploy systemic measures such as fail-safes, so that the equipment incorporating Hitachiproduct does not cause bodily injury, fire or other consequential damage due to operation ofthe Hitachi product.

5. This product is not designed to be radiation resistant.6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document

without written approval from Hitachi.7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi

semiconductor products.

Rev. 3.0, 03/01, page iv of xxvi

Rev. 3.0, 03/01, Page v of xxvi

Preface

The H8/3664 Series is a single-chip microprocessor made up of the high-speed H8/300H CPU asits core, and the peripheral functions required to configure a system. The H8/300H CPU has aninstruction set that is compatible with the H8/300 CPU.

Target Users: This manual was written for users who will be using the H8/3664 Series in thedesign of application systems. Target users are expected to understand thefundamentals of electrical circuits, logical circuits, and microcomputers.

Objective: This manual was written to explain the hardware functions and electricalcharacteristics of the H8/3664 Series to the target users.Refer to the H8/300H Series Programming Manual for a detailed description of theinstruction set.

Notes on reading this manual:

• In order to understand the overall functions of the chipRead the manual according to the contents. This manual can be roughly categorized into partson the CPU, system control functions, peripheral functions and electrical characteristics.

• In order to understand the details of the CPU's functionsRead the H8/300H Series Programming Manual.

• In order to understand the details of a register when its name is knownRead the index that is the final part of the manual to find the page number of the entry on theregister. The addresses, bits, and initial values of the registers are summarized in Appendix B,Internal I/O Registers.

Example: Bit order: The MSB is on the left and the LSB is on the right.

Related Manuals: The latest versions of all related manuals are available from our web site.Please ensure you have the latest versions of all documents you require.http://www.hitachi.co.jp/Sicd/English/Products/micome.htm

H8/3664 Series manuals:

Manual Title ADE No.

H8/3664 Series Hardware Manual This manual

H8/300H Series Programming Manual ADE-602-053

Rev. 3.0, 03/01, page vi of xxvi

User's manuals for development tools:


C/C++ Compiler, Assembler, Optimized Linkage Editor User's Manual ADE-702-246

Simulator/Debugger User's Manual (Windows) ADE-702-037

Simulator/Debugger User's Manual (UNIX) ADE-702-085

Hitachi Debugging Interface User's Manual ADE-702-212

Hitachi Embedded Workshop User's Manual ADE-702-201

H8S, H8/300 Series Hitachi Embedded Workshop, Hitachi DebuggingInterface Tutorial

ADE-702-231

Application Notes:


H8/300H Series CPU Guide ADE-502-033

H8/300H Series On-Chip I/O Ports Guide ADE-502-036

H8/300H Technical Q & A ADE-502-038

H8S, H8/300 Series C/C++ Compiler Guide ADE-502-044

F-ZTAT Technical Q & A ADE-502-046

Rev. 3.0, 03/01, Page vii of xxvi

Contents

Section 1 Overview........................................................................................... 11.1 Overview...........................................................................................................................11.2 Internal Block Diagram.....................................................................................................21.3 Pin Arrangement ...............................................................................................................41.4 Pin Functions ....................................................................................................................71.5 Comparison between H8/3664N and H8/3664 .................................................................9

Section 2 CPU................................................................................................... 112.1 Address Space and Memory Map .....................................................................................122.2 Register Configuration......................................................................................................15

2.2.1 General Registers .................................................................................................162.2.2 Program Counter (PC) .........................................................................................172.2.3 Condition-Code Register (CCR) ..........................................................................17

2.3 Data Formats.....................................................................................................................192.3.1 General Register Data Formats ............................................................................192.3.2 Memory Data Formats .........................................................................................21

2.4 Instruction Set ...................................................................................................................222.4.1 Table of Instructions Classified by Function .......................................................222.4.2 Basic Instruction Formats ....................................................................................31

2.5 Addressing Modesand Effective Address Calculation ......................................................332.5.1 Addressing Modes ...............................................................................................332.5.2 Effective Address Calculation .............................................................................35

2.6 Basic Bus Cycle ................................................................................................................382.6.1 Access to On-Chip Memory (RAM, ROM).........................................................382.6.2 On-Chip Peripheral Modules ...............................................................................39

2.7 CPU States ........................................................................................................................402.8 Usage Notes ......................................................................................................................41

2.8.1 Notes on Data Access to Empty Areas ................................................................412.8.2 EEPMOV Instruction...........................................................................................412.8.3 Bit Manipulation Instruction................................................................................41

Section 3 Exception Handling .......................................................................... 473.1 Exception Sources and Vector Address ............................................................................473.2 Register Descriptions ........................................................................................................49

3.2.1 Interrupt Edge Select Register 1(IEGR1) ............................................................493.2.2 Interrupt Edge Select Register 2(IEGR2) ............................................................503.2.3 Interrupt Enable Register 1(IENR1) ....................................................................513.2.4 Interrupt Flag Register 1(IRR1) ...........................................................................523.2.5 Wakeup Interrupt Flag Register(IWPR) ..............................................................53

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3.3 Reset..................................................................................................................................543.4 Interrupt Exception Handling............................................................................................54

3.4.1 External Interrupts ...............................................................................................543.4.2 Internal Interrupts ................................................................................................553.4.3 Interrupt Handling Sequence ...............................................................................563.4.4 Interrupt Response Time......................................................................................57

3.5 Usage Notes ......................................................................................................................593.5.1 Interrupts after Reset............................................................................................593.5.2 Notes on Stack Area Use .....................................................................................593.5.3 Notes on Rewriting Port Mode Registers.............................................................59

Section 4 Address Break....................................................................................614.1 Register Descriptions ........................................................................................................61

4.1.1 Address Break Control Register(ABRKCR) .......................................................624.1.2 Address Break Status Register(ABRKSR) ..........................................................634.1.3 Break Address Registers (BARH, BARL)...........................................................634.1.4 Break Data Registers (BDRH, BDRL) ................................................................64

4.2 Operation ..........................................................................................................................64

Section 5 Clock Pulse Generators .....................................................................675.1 System Clock Generator ...................................................................................................67

5.1.1 Connecting a Crystal Oscillator ...........................................................................685.1.2 Connecting a Ceramic Oscillator .........................................................................695.1.3 External Clock Input Method...............................................................................69

5.2 Subclock Generator...........................................................................................................695.2.1 Connecting a 32.768-kHz Crystal Oscillator .......................................................705.2.2 Pin Connection when Not Using Subclock..........................................................70

5.3 Prescalers ..........................................................................................................................715.3.1 Prescaler S............................................................................................................715.3.2 Prescaler W..........................................................................................................71

5.4 Usage Notes ......................................................................................................................715.4.1 Note on Oscillators ..............................................................................................715.4.2 Notes on Board Design ........................................................................................72

Section 6 Power-down Modes...........................................................................736.1 Register Descriptions ........................................................................................................73

6.1.1 System Control Register 1(SYSCR1) ..................................................................736.1.2 System Control Register 2(SYSCR2) ..................................................................756.1.3 Module Standby Control Register 1(MSTCR1) ..................................................76

6.2 Mode Transitions and States of the LSI............................................................................776.2.1 Sleep Mode ..........................................................................................................806.2.2 Standby Mode......................................................................................................816.2.3 Subsleep Mode.....................................................................................................81

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6.2.4 Subactive Mode ...................................................................................................826.3 Operating Frequency in the Active Mode.........................................................................826.4 Direct Transition ...............................................................................................................82

6.4.1 Direct transition from the active mode to the subactive mode.............................826.4.2 Direct transition from the subactive mode to the active mode.............................83

6.5 Module Standby Function.................................................................................................83

Section 7 ROM ................................................................................................. 857.1 Block Configuration..........................................................................................................857.2 Register Descriptions ........................................................................................................86

7.2.1 Flash Memory Control Register 1 (FLMCR1).....................................................877.2.2 Flash Memory Control Register 2 (FLMCR2).....................................................887.2.3 Erase Block Register 1 (EBR1)............................................................................887.2.4 Flash Memory Power Control Register(FLPWCR) .............................................897.2.5 Flash Memory Enable Register(FENR) ...............................................................89

7.3 On-Board Programming Modes........................................................................................907.3.1 Boot Mode ...........................................................................................................907.3.2 Programming/Erasing in User Program Mode.....................................................93

7.4 Flash Memory Programming/Erasing ...............................................................................947.4.1 Program/Program-Verify .....................................................................................947.4.2 Erase/Erase-Verify ...............................................................................................967.4.3 Interrupt Handling when Programming/Erasing Flash Memory..........................97

7.5 Program/Erase Protection .................................................................................................997.5.1 Hardware Protection ............................................................................................997.5.2 Software Protection..............................................................................................997.5.3 Error Protection....................................................................................................99

7.6 Programmer Mode ............................................................................................................1007.6.1 Socket Adapter.....................................................................................................1007.6.2 Programmer Mode Commands ............................................................................1007.6.3 Memory Read Mode ............................................................................................1027.6.4 Auto-Program Mode ............................................................................................1047.6.5 Auto-Erase Mode.................................................................................................1067.6.6 Status Read Mode ................................................................................................1087.6.7 Status Polling .......................................................................................................1097.6.8 Programmer Mode Transition Time.....................................................................1107.6.9 Notes on Memory Programming..........................................................................110

7.7 Power-Down States for Flash Memory.............................................................................111

Section 8 RAM ................................................................................................. 113

Section 9 I/O Ports ............................................................................................ 1159.1 Port 1.................................................................................................................................115

9.1.1 Port Mode Register 1(PMR1) ..............................................................................116

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9.1.2 Port Control Register 1(PCR1) ............................................................................1179.1.3 Port Data Register 1(PDR1).................................................................................1179.1.4 Port Pull-Up Control Register 1(PUCR1)............................................................1189.1.5 Pin Functions .......................................................................................................118

9.2 Port 2.................................................................................................................................1209.2.1 Port Control Register 2(PCR2) ............................................................................1209.2.2 Port Data Register 2(PDR2).................................................................................1219.2.3 Pin Functions .......................................................................................................121

9.3 Port 5.................................................................................................................................1229.3.1 Port Mode Register 5(PMR5) ..............................................................................1249.3.2 Port Control Register 5(PCR5) ............................................................................1259.3.3 Port Data Register 5(PDR5).................................................................................1259.3.4 Port Pull-up Control Register 5(PUCR5).............................................................1269.3.5 Pin Functions .......................................................................................................126



9.6 Port B ................................................................................................................................1349.6.1 Port Data Register B(PDRB) ...............................................................................135

Section 10 Timer A............................................................................................13710.1 Features.............................................................................................................................13710.2 Input/Output Pins ..............................................................................................................13810.3 Register Descriptions ........................................................................................................138

10.3.1 Timer Mode Register A(TMA)............................................................................13910.3.2 Timer Counter A (TCA) ......................................................................................140

10.4 Operation ..........................................................................................................................14010.4.1 Interval Timer Operation .....................................................................................14010.4.2 Clock Time Base Operation.................................................................................14010.4.3 Clock Output........................................................................................................140

10.5 Usage Note........................................................................................................................141

Section 11 Timer V............................................................................................14311.1 Features.............................................................................................................................14311.2 Input/Output Pins ..............................................................................................................14411.3 Register Descriptions ........................................................................................................145

11.3.1 Timer Counter V (TCNTV) .................................................................................14511.3.2 Time Constant Registers A and B (TCORA, TCORB)........................................145

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11.3.3 Timer Control Register V0(TCRV0) ...................................................................14611.3.4 Timer Control/Status Register V(TCSRV) ..........................................................14811.3.5 Timer Control Register V1(TCRV1) ...................................................................149

11.4 Operation...........................................................................................................................15011.4.1 Timer V operation................................................................................................150

11.5 Timer V application examples ..........................................................................................15211.5.1 Pulse Output with Arbitrary Duty Cycle..............................................................15211.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input .............153

11.6 Usage Notes ......................................................................................................................154

Section 12 Timer W.......................................................................................... 15712.1 Features .............................................................................................................................15712.2 Input/Output Pins ..............................................................................................................15912.3 Register Descriptions ........................................................................................................160

12.3.1 Timer Mode Register W(TMRW) .......................................................................16012.3.2 Timer Control Register W(TCRW) .....................................................................16212.3.3 Timer Interrupt Enable Register W(TIERW).......................................................16312.3.4 Timer Status Register W(TSRW) ........................................................................16312.3.5 Timer I/O Control Register 0(TIOR0) .................................................................16512.3.6 Timer I/O Control Register 1(TIOR1) .................................................................16612.3.7 Timer Counter (TCNT)........................................................................................16712.3.8 General Registers A to D (GRA to GRD)............................................................167

12.4 Operation...........................................................................................................................16812.4.1 Normal Operation ................................................................................................16812.4.2 PWM Operation ...................................................................................................172

12.5 Operation Timing..............................................................................................................17612.5.1 TCNT Count Timing............................................................................................17612.5.2 Output Compare Timing ......................................................................................17612.5.3 Input Capture Timing...........................................................................................17712.5.4 Timing of Counter Clearing by Compare Match .................................................17812.5.5 Buffer Operation Timing .....................................................................................17812.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match.................................17912.5.7 Timing of IMFA to IMFD Setting at Input Capture ............................................18012.5.8 Timing of Status Flag Clearing............................................................................180

12.6 Usage Notes ......................................................................................................................181

Section 13 Watchdog Timer ............................................................................. 18313.1 Features .............................................................................................................................18313.2 Register Descriptions ........................................................................................................183

13.2.1 Timer Control/Status Register WD(TCSRWD)...................................................18413.2.2 Timer Counter WD(TCWD)................................................................................18513.2.3 Timer Mode Register WD(TMWD) ....................................................................185

13.3 Operation...........................................................................................................................186

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Section 14 Serial Communication Interface3 (SCI3) ........................................18714.1 Features.............................................................................................................................18714.2 Input/Output Pins ..............................................................................................................18914.3 Register Descriptions ........................................................................................................189

14.3.1 Receive Shift Register (RSR) ..............................................................................19014.3.2 Receive Data Register (RDR) ..............................................................................19014.3.3 Transmit Shift Register (TSR) .............................................................................19014.3.4 Transmit Data Register (TDR).............................................................................19014.3.5 Serial Mode Register (SMR)................................................................................19114.3.6 Serial Control Register 3 (SCR3).........................................................................19214.3.7 Serial Status Register (SSR) ................................................................................19414.3.8 Bit Rate Register (BRR) ......................................................................................196

14.4 Operation in Asynchronous Mode ....................................................................................20114.4.1 Clock....................................................................................................................20114.4.2 SCI3 Initialization................................................................................................20214.4.3 Data Transmission ...............................................................................................20314.4.4 Serial Data Reception ..........................................................................................205

14.5 Operation in Clocked Synchronous Mode ........................................................................20914.5.1 Clock....................................................................................................................20914.5.2 SCI3 Initialization................................................................................................20914.5.3 Serial Data Transmission .....................................................................................21014.5.4 Serial Data Reception (Clocked Synchronous Mode)..........................................21214.5.5 Simultaneous Serial Data Transmission and Reception.......................................214

14.6 Multiprocessor Communication Function.........................................................................21614.6.1 Multiprocessor Serial Data Transmission ............................................................21814.6.2 Multiprocessor Serial Data Reception .................................................................219

14.7 Interrupts...........................................................................................................................22314.8 Usage Notes ......................................................................................................................224

14.8.1 Break Detection and Processing ..........................................................................22414.8.2 Mark State and Break Detection ..........................................................................22414.8.3 Receive Error Flags and Transmit Operations

(Clocked Synchronous Mode Only) ....................................................................22414.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode 225

Section 15 I2C Bus Interface (IIC).....................................................................22715.1 Features.............................................................................................................................22715.2 Input/Output Pins ..............................................................................................................22915.3 Register Descriptions ........................................................................................................229

15.3.1 I2C bus data register(ICDR) .................................................................................23015.3.2 Slave address register(SAR) ................................................................................23215.3.3 Second slave address register(SARX) .................................................................23215.3.4 I2C Bus Mode Register(ICMR)............................................................................23315.3.5 I2C Bus Control Register(ICCR)..........................................................................235

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15.3.6 I2C Bus Status Register(ICSR).............................................................................23815.3.7 Timer Serial Control Register(TSCR)..................................................................240

15.4 Operation...........................................................................................................................24115.4.1 I2C Bus Data Format ............................................................................................24115.4.2 Master Transmit Operation ..................................................................................24315.4.3 Master Receive Operation....................................................................................24415.4.4 Slave Receive Operation......................................................................................24715.4.5 Slave Transmit Operation ....................................................................................24915.4.6 Clock Synchronous Serial Format .......................................................................25115.4.7 IRIC Setting Timing and SCL Control ................................................................25115.4.8 Noise Canceler .....................................................................................................25315.4.9 Sample Flowcharts...............................................................................................253

15.5 Usage Notes ......................................................................................................................258

Section 16 A/D Converter................................................................................. 26316.1 Features .............................................................................................................................26316.2 Input/Output Pins ..............................................................................................................26516.3 Register Description..........................................................................................................266

16.3.1 A/D Data Registers A to D (ADDRA to ADDRD)..............................................26616.3.2 A/D Control/Status Register (ADCSR)................................................................26716.3.3 A/D Control Register (ADCR).............................................................................268

16.4 Operation...........................................................................................................................26916.4.1 Single Mode.........................................................................................................26916.4.2 Scan Mode ...........................................................................................................26916.4.3 Input Sampling and A/D Conversion Time .........................................................27016.4.4 External Trigger Input Timing.............................................................................271

16.5 A/D Conversion Precision Definitions..............................................................................27216.6 Usage Notes ......................................................................................................................273

16.6.1 Permissible Signal Source Impedance .................................................................27316.6.2 Influences on Absolute Precision.........................................................................273

Section 17 EEPROM ........................................................................................ 27517.1 Features..............................................................................................................................27517.2 Input/Output Pin ................................................................................................................27617.3 Registers ............................................................................................................................277

17.3.1 EEPROM Key Register (EKR) ............................................................................27717.4 Operation ...........................................................................................................................277

17.4.1 EEPROM Interface ..............................................................................................27717.4.2 Bus Format and Timing .......................................................................................27817.4.3 Start Condition .....................................................................................................27817.4.4 Stop Condition .....................................................................................................27817.4.5 Acknowledge .......................................................................................................27917.4.6 Slave Addressing..................................................................................................279

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17.4.7 Write Operations..................................................................................................28017.4.8 Acknowledge Polling...........................................................................................28117.4.9 Read Operation ....................................................................................................282

17.5 Notes..................................................................................................................................28417.5.1 Data Protection at VCC On/Off..............................................................................28417.5.2 Write/Erase Endurance ........................................................................................28417.5.3 Noise Suppression Time ......................................................................................284

Section 18 Power Supply Circuit ......................................................................28518.1 When Using the Internal Power Supply Step-Down Circuit.............................................28518.2 When Not Using the Internal Power Supply Step-Down Circuit......................................286

Section 19 Electrical Characteristics .................................................................28719.1 Absolute Maximum Ratings .............................................................................................28719.2 Electrical Characteristics (F-ZTAT™ Version, F-ZTAT™ Version with EEPROM)......287

19.2.1 Power Supply Voltage and Operating Ranges.....................................................28719.2.2 DC Characteristics ...............................................................................................28919.2.3 AC Characteristics ...............................................................................................29519.2.4 A/D Converter Characteristics .............................................................................29919.2.5 Watchdog Timer ..................................................................................................30019.2.6 Flash Memory Characteristics .............................................................................30119.2.7 EEPROM Characteristics (Preliminary) ..............................................................303

19.3 Electrical Characteristics (Mask ROM Version)...............................................................30419.3.1 Power Supply Voltage and Operating Ranges.....................................................30419.3.2 DC Characteristics ...............................................................................................30519.3.3 AC Characteristics ...............................................................................................31119.3.4 A/D Converter Characteristics .............................................................................31519.3.5 Watchdog Timer ..................................................................................................316

19.4 Operation Timing..............................................................................................................31619.5 Output Load Circuit ..........................................................................................................319

Appendix A Instruction Set ...............................................................................321A.1 Instruction List ..................................................................................................................321A.2 Operation Code Map.........................................................................................................336A.3 Number of Execution States .............................................................................................339A.4 Combinations of Instructions and Addressing Modes ......................................................346

Appendix B Internal I/O Registers ....................................................................347B.1 Register Addresses............................................................................................................347B.2 Register Bits......................................................................................................................350B.3 Registers States in Each Operating Mode.........................................................................353

Appendix C I/O Port Block Diagrams...............................................................356

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C.1 I/O Port Block ...................................................................................................................356C.2 Port States in Each Operating State...................................................................................372

Appendix D Product Code Lineup.................................................................... 373

Appendix E Package Dimensions..................................................................... 374

Appendix F Laminated-Structure Cross Section .............................................. 377

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Figures of Contents

Section 1 OverviewFigure 1-1 Internal Block Diagram of H8/3664 of the F-ZTATTM and Mask-ROM Versions .......2Figure 1-2 Internal Block Diagram of the F-ZTATTM Version H8/3664N with EEPROM............3Figure 1-3 Pin Arrangement of the F-ZTATTM-Version H8/3664N with EEPROM(FP-64E) .......4Figure 1-4 Pin Arrangement of H8/3664 of the F-ZTATTM and Mask-ROM Versions

(FP-64E, FP-64A) .........................................................................................................5Figure 1-5 Pin Arrangement of H8/3664 of the F-ZTATTM and Mask-ROM Versions (DS-42S) .6

Section 2 CPUFigure 2-1 Memory Map(1) ..........................................................................................................12Figure 2-1 Memory Map(2) ..........................................................................................................13Figure 2-1 Memory Map(3) ..........................................................................................................14Figure 2-2 CPU Registers .............................................................................................................15Figure 2-3 Usage of General Registers .........................................................................................16Figure 2-4 Relationship between Stack Pointer and Stack Area...................................................17Figure 2-5 General Register Data Formats (1)..............................................................................19Figure 2-5 General Register Data Formats (2)..............................................................................20Figure 2-6 Memory Data Formats ................................................................................................21Figure 2-7 Instruction Formats .....................................................................................................32Figure 2-8 Branch Address Specification in Memory Indirect Mode...........................................35Figure 2-9 On-Chip Memory Access Cycle..................................................................................38Figure 2-10 On-Chip Peripheral Module Access Cycle (3-State Access) ....................................39Figure 2-11 CPU Operation States................................................................................................40Figure 2-12 State Transitions........................................................................................................41Figure 2-13 Example of Timer Configuration with Two Registers Allocated to Same Address..42

Section 3 Exception HandlingFigure 3-1 Reset Sequence............................................................................................................55Figure 3-2 Stack Status after Exception Handling........................................................................57Figure 3-3 Interrupt Sequence ......................................................................................................58Figure 3-4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure ..............59

Section 4 Address BreakFigure 4-1 Block Diagram of an Address Break...........................................................................61Figure 4-2 Address Break Interrupt Operation Example (1).........................................................64Figure 4-2 Address Break Interrupt Operation Example (2).........................................................65Figure 4-2 Address Break Interrupt Operation Example (3).........................................................66

Section 5 Clock Pulse GeneratorsFigure 5-1 Block Diagram of Clock Pulse Generators .................................................................67Figure 5-2 Block Diagram of the System Clock Generator ..........................................................68

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Figure 5-3 Typical Connection to Crystal Oscillator....................................................................68Figure 5-4 Equivalent Circuit of Crystal Oscillator......................................................................68Figure 5-5 Typical Connection to Ceramic Oscillator ..................................................................69Figure 5-6 Example of External Clock Input................................................................................69Figure 5-7 Block Diagram of the Subclock Generator .................................................................69Figure 5-8 Typical Connection to 32.768-kHz Crystal Oscillator ................................................70Figure 5-9 Equivalent Circuit of 32.768-kHz Crystal Oscillator ..................................................70Figure 5-10 Pin Connection when not Using Subclock ................................................................70Figure 5-11 Example of Incorrect Board Design...........................................................................72Figure 6-1 Mode Transition Diagram...........................................................................................78Figure 7-1 Flash Memory Block Configuration ...........................................................................86Figure 7-2 Programming/Erasing Flowchart Example in User Program Mode............................93Figure 7-3 Program/Program-Verify Flowchart ...........................................................................95Figure 7-4 Erase/Erase-Verify Flowchart .....................................................................................98Figure 7-5 Socket Adapter Pin Correspondence Diagram..........................................................101Figure 7-6 Timing Waveforms for Memory Read after Memory Write.....................................102Figure 7-7 Timing Waveforms in Transition from Memory Read Mode to Another Mode.......103Figure 7-8 CE and OE Enable State Read Timing Waveforms ..................................................104Figure 7-9 CE and OE Clock System Read Timing Waveforms................................................104Figure 7-10 Auto-Program Mode Timing Waveforms ...............................................................106Figure 7-11 Auto-Erase Mode Timing Waveforms....................................................................107Figure 7-12 Status Read Mode Timing Waveforms ...................................................................108Figure 7-13 Oscillation Stabilization Time, Boot Program Transfer Time, and

Power-Down Sequence...........................................................................................110

Section 9 I/O PortsFigure 9-1 Port 1 Pin Configuration ...........................................................................................115Figure 9-2 Port 2 Pin Configuration ...........................................................................................120Figure 9-3 Port 5 Pin Configuration ...........................................................................................123Figure 9-4 Port 7 Pin Configuration ...........................................................................................128Figure 9-5 Port 8 Pin Configuration ...........................................................................................131Figure 9-6 Port B Pin Configuration...........................................................................................134

Section 10 Timer AFigure 10-1 Block Diagram of Timer A .....................................................................................138

Section 11 Timer VFigure 11-1 Block Diagram of Timer V .....................................................................................144Figure 11-2 Increment Timing with Internal Clock....................................................................150Figure 11-3 Increment Timing with External Clock...................................................................151Figure 11-4 OVF Set Timing......................................................................................................151Figure 11-5 CMFA and CMFB Set Timing................................................................................151Figure 11-6 TMOV Output Timing ............................................................................................152

Rev. 3.0, 03/01, Page xix of xxvi

Figure 11-7 Clear Timing by Compare Match............................................................................152Figure 11-8 Clear Timing by TMRIV Input ...............................................................................152Figure 11-9 Pulse Output Example.............................................................................................153Figure 11-10 Example of Pulse Output Synchronized to TRGV Input.......................................154Figure 11-11 Contention between TCNTV Write and Clear ......................................................155Figure 11-12 Contention between TCORA Write and Compare Match.....................................155Figure 11-13 Internal Clock Switching and TCNTV Operation.................................................156

Section 12 Timer WFigure 12-1 Timer W Block Diagram.........................................................................................159Figure 12-2 Free-Running Counter Operation............................................................................168Figure 12-3 Periodic Counter Operation.....................................................................................169Figure 12-4 0 and 1 Output Example(TOA = 0, TOB = 1).........................................................169Figure 12-5 Toggle Output Example (TOA = 0, TOB = 1) ........................................................170Figure 12-6 Toggle Output Example (TOA = 0, TOB = 1) ........................................................170Figure 12-7 Input Capture Operating Example...........................................................................171Figure 12-8 Buffer Operation Example (Input Capture).............................................................171Figure 12-9 PWM Mode Example (1) ........................................................................................172Figure 12-10 PWM Mode Example (2) ......................................................................................173Figure 12-11 Buffer Operation Example (Output Compare) ......................................................173Figure 12-12 PWM Mode Example

(TOB=0, TOC=0, TOD=0: initial output values are set to 0) ...............................174Figure 12-13 PWM Mode Example

(TOB=1, TOC=1,and TOD=1: initial output values are set to 1) .........................175Figure 12-14 Count Timing for Internal Clock Source...............................................................176Figure 12-15 Count Timing for External Clock Source..............................................................176Figure 12-16 Output Compare Output Timing ...........................................................................177Figure 12-17 Input Capture Input Signal Timing .......................................................................177Figure 12-18 Timing of Counter Clearing by Compare Match...................................................178Figure 12-19 Buffer Operation Timing (Compare Match) .........................................................178Figure 12-20 Buffer Operation Timing (Input Capture) .............................................................179Figure 12-21 Timing of IMFA to IMFD Flag Setting at Compare Match..................................179Figure 12-22 Timing of IMFA to IMFD Flag Setting at Input Capture......................................180Figure 12-23 Timing of Status Flag Clearing by the CPU..........................................................180Figure 12-24 Contention between TCNT Write and Clear .........................................................181Figure 12-25 Internal Clock Switching and TCNT Operation....................................................182

Section 13 Watchdog TimerFigure 13-1 Block Diagram of WDT..........................................................................................183Figure 13-2 Watchdog Timer Operation Example......................................................................186

Section 14 Serial Communication Interface3 (SCI3)Figure 14-1 Block Diagram of SCI3...........................................................................................188

Rev. 3.0, 03/01, page xx of xxvi

Figure 14-2 Data Format in Asynchronous Communication ......................................................201Figure 14-3 Relationship between Output Clock and Transfer Data Phase

(Asynchronous Mode)(Example with 8-Bit Data, Parity, Two Stop Bits)..............201Figure 14-4 Sample SCI3 Initialization Flowchart .....................................................................202Figure 14-5 Example SCI3 Operation in Transmission in Asynchronous Mode

(8-Bit Data, Parity, One Stop Bit)...........................................................................203Figure 14-6 Sample Serial Transmission Flowchart...................................................................204Figure 14-7 Example SCI3 Operation in Reception in Asynchronous Mode

(8-Bit Data, Parity, One Stop Bit)...........................................................................205Figure 14-8 Sample Serial Reception Data Flowchart (Asynchronous mode)(1).......................207Figure 14-8 Sample Serial Reception Data Flowchart (2) ..........................................................208Figure 14-9 Data Format in Synchronous Communication ........................................................209Figure 14-10 Example of SCI3 Operation in Transmission in Clocked Synchronous Mode .....210Figure 14-11 Sample Serial Transmission Flowchart(Clocked Synchronous Mode) .................211Figure 14-12 Example of SCI3 Reception Operation in Clocked Synchronous Mode...............212Figure 14-13 Sample Serial Reception Flowchart(Clocked Synchronous Mode) ......................213Figure 14-14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations

(Clocked Synchronous Mode) ..............................................................................215Figure 14-15 Example of Communication Using Multiprocessor Format

(Transmission of Data H'AA to Receiving Station A)..........................................217Figure 14-16 Sample Multiprocessor Serial Transmission Flowchart........................................218Figure 14-17 Sample Multiprocessor Serial Reception Flowchart (1) .......................................220Figure 14-17 Sample Multiprocessor Serial Reception Flowchart (2) .......................................221Figure 14-18 Example of SCI3 Operation in Reception Using Multiprocessor Format

(Example with 8-Bit Data, MultiprocessorBit, One Stop Bit) ..............................222Figure 14-19 Receive Data Sampling Timing in Asynchronous Mode ......................................225Figure 15-1 Block Diagram of I2C Bus Interface .......................................................................228Figure 15-2 I2C Bus Interface Connections (Example: This LSI as Master) ..............................229Figure 15-3 I2C Bus Data Formats (I2C Bus Formats)................................................................242Figure 15-4 I2C Bus Timing .......................................................................................................242Figure 15-5 Master Transmit Mode Operation Timing Example (MLS = WAIT = 0).................244Figure 15-6 Master Receive Mode Operation Timing Example (1)

(MLS = ACKB = 0, WAIT = 1) .............................................................................246Figure 15-6 Master Receive Mode Operation Timing Example (2)

(MLS = ACKB = 0, WAIT = 1) .............................................................................246Figure 15-7 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0)........248Figure 15-8 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0)........249Figure 15-9 Example of Slave Transmit Mode Operation Timing (MLS = 0) ...........................250Figure 15-10 I2C Bus Data Format (Serial Format)....................................................................251Figure 15-11 IRIC Setting Timing and SCL Control..................................................................252Figure 15-12 Block Diagram of Noise Canceler ........................................................................253Figure 15-13 Sample Flowchart for Master Transmit Mode ......................................................254Figure 15-14 Sample Flowchart for Master Receive Mode........................................................255

Rev. 3.0, 03/01, Page xxi of xxvi

Figure 15-15 Sample Flowchart for Slave Receive Mode ..........................................................256Figure 15-16 Sample Flowchart for Slave Transmit Mode.........................................................257Figure 15-17 Flowchart and Timing of Start Condition Instruction Issuance

for Retransmission ................................................................................................262

Section 16 A/D ConverterFigure 16-1 Block Diagram of A/D Converter ...........................................................................264Figure 16-2 A/D Conversion Timing..........................................................................................270Figure 16-3 External Trigger Input Timing ................................................................................271Figure 16-4 A/D Conversion Precision Definitions (1) ..............................................................272Figure 16-5 A/D Conversion Precision Definitions (2) ..............................................................273Figure 16-6 Analog Input Circuit Example ................................................................................274

Section 17 EEPROMFigure 17-1 Block Diagram of the EEPROM.............................................................................276Figure 17-2 EEPROM Bus Format and Bus Timing ..................................................................278Figure 17-3 Byte Write Operation ..............................................................................................280Figure 17-4 Page Write Operation..............................................................................................281Figure 17-5 Current Address Read Operation ............................................................................282Figure 17-6 Random Address Read Operation ...........................................................................283Figure 17-7 Sequential Read Operation (when the current address read is used).......................284

Section 18 Power Supply CircuitFigure 18-1 Power Supply Connection when Internal Step-Down Circuit Is Used....................285Figure 18-2 Power Supply Connection when Internal Step-Down Circuit Is Not Used.............286

Section 19 Electrical CharacteristicsFigure 19-1 System Clock Input Timing ....................................................................................316Figure 19-2 RES Low Width Timing .........................................................................................317Figure 19-3 Input Timing............................................................................................................317Figure 19-4 I2C Bus Interface Input/Output Timing...................................................................317Figure 19-5 SCK3 Input Clock Timing ......................................................................................318Figure 19-6 Serial Interface 3 Synchronous Mode Input/Output Timing ...................................318Figure 19-7 EEPROM Bus Timing.............................................................................................319Figure 19-8 Output Load Condition............................................................................................319

AppendixFigure C.1 Port 1 Block Diagram (P17) .....................................................................................356Figure C.2 Port 1 Block Diagram (P16 to P14) ..........................................................................357Figure C.3 Port 1 Block Diagram (P12, P11) .............................................................................358Figure C.4 Port 1 Block Diagram (P10) .....................................................................................359Figure C.5 Port 2 Block Diagram (P22) .....................................................................................360Figure C.6 Port 2 Block Diagram (P21) .....................................................................................361Figure C.7 Port 2 Block Diagram (P20) .....................................................................................362

Rev. 3.0, 03/01, page xxii of xxvi

Figure C.8 Port 5 Block Diagram (P57, P56)* ...........................................................................363Figure C.9 Port 5 Block Diagram (P55) .....................................................................................364Figure C.10 Port 5 Block Diagram (P54 to P50) ........................................................................365Figure C.11 Port 7 Block Diagram (P76) ...................................................................................366Figure C.12 Port 7 Block Diagram (P75) ...................................................................................367Figure C.13 Port 7 Block Diagram (P74) ...................................................................................368Figure C.14 Port 8 Block Diagram (P87 to P85) ........................................................................369Figure C.15 Port 8 Block Diagram (P84 to P81) ........................................................................370Figure C.16 Port 8 Block Diagram (P80) ...................................................................................371Figure C.17 Port B Block Diagram (PB7 to PB0) ......................................................................372Figure E.1 FP-64A Package Dimensions....................................................................................374Figure E.2 FP-64E Package Dimensions ....................................................................................375Figure E.3 DP-42S Package Dimensions....................................................................................376Figure F-1 Laminated-Structure Cross Section of H8/3664N ....................................................377

Rev. 3.0, 03/01, Page xxiii of xxvi

Tables of Contents

Section 1 OverviewTable 1-1 Pin Functions ................................................................................................................7Table 1-2 Comparison between H8/3664N and H8/3664 .............................................................9

Section 2 CPUTable 2-1 Operation Notation......................................................................................................22Table 2-2 Data Transfer Instructions...........................................................................................23Table 2-3 Arithmetic Operations Instructions (1) .......................................................................24Table 2-3 Arithmetic Operations Instructions (2) .......................................................................25Table 2-4 Logic Operations Instructions.....................................................................................26Table 2-5 Shift Instructions.........................................................................................................26Table 2-6 Bit Manipulation Instructions (1)................................................................................27Table 2-6 Bit Manipulation Instructions (2)................................................................................28Table 2-7 Branch Instructions .....................................................................................................29Table 2-8 System Control Instructions........................................................................................30Table 2-9 Block Data Transfer Instructions ................................................................................31Table 2-10 Addressing Modes ..................................................................................................33Table 2-11 Absolute Address Access Ranges ...........................................................................34Table 2-12 Effective Address Calculation (1) ...........................................................................36Table 2-12 Effective Address Calculation (2) ..............................................................................37

Section 3 Exception HandlingTable 3-1 Exception Sources and Vector Address ......................................................................48Table 3-2 Interrupt Wait States ...................................................................................................57

Section 4 Address BreakTable 4-1 Access and Data Bus Used..........................................................................................63

Section 5 Clock Pulse GeneratorsTable 5-1 Crystal Oscillator Parameters......................................................................................68

Section 6 Power-down ModesTable 6-1 Operating Frequency and Waiting Time.....................................................................75Table 6-2 Transition Mode after the SLEEP Instruction Execution and Interrupt Handling ......79Table 6-3 Internal State in Each Operating Mode.......................................................................80

Section 7 ROMTable 7-1 Setting Programming Modes ......................................................................................90Table 7-2 Boot Mode Operation .................................................................................................92Table 7-3 System Clock Frequencies for which Automatic Adjustment of

LSI Bit Rate is Possible ..............................................................................................92

Rev. 3.0, 03/01, page xxiv of xxvi

Table 7-4 Reprogram Data Computation Table ..........................................................................96Table 7-5 Additional-Program Data Computation Table ............................................................96Table 7-6 Programming Time .....................................................................................................96Table 7-7 Command Sequence in Programmer Mode ..............................................................100Table 7-8 AC Characteristics in Transition to Memory Read Mode

(Conditions: VCC = 5.0 V ±0.5 V, VSS = 0 V, Ta = 25°C ±5°C)................................102Table 7-9 AC Characteristics in Transition from Memory Read Mode to Another Mode

(Conditions: VCC = 5.0 V ±0.5 V, VSS = 0 V, Ta = 25°C ±5°C)................................103Table 7-10 AC Characteristics in Memory Read Mode

(Conditions: VCC = 5.0 V ±0.5 V, VSS = 0 V, Ta = 25°C ±5°C)............................103Table 7-11 AC Characteristics in Auto-Program Mode

(Conditions: VCC = 5.0 V ±0.5 V, VSS = 0 V, Ta = 25°C ±5°C)............................105Table 7-12 AC Characteristics in Auto-Erase Mode

(Conditions: VCC = 5.0 V ±0.5 V, VSS = 0 V, Ta = 25°C ±5°C)............................107Table 7-13 AC Characteristics in Status Read Mode

(Conditions: VCC = 5.0 V ±0.5 V, VSS = 0 V, Ta = 25°C ±5°C)............................108Table 7-14 Status Read Mode Return Codes ..........................................................................109Table 7-15 Status Polling Output Truth Table ........................................................................109Table 7-16 Stipulated Transition Times to Command Wait State...........................................110Table 7-17 Flash Memory Operating States............................................................................111

Section 10 Timer ATable 10-1 Pin Configuration..................................................................................................138

Section 11 Timer VTable 11-1 Pin Configuration..................................................................................................144Table 11-2 Clock signals to input to TCNTV and the counting conditions ............................147

Section 12 Timer WTable 12-1 Timer W Functions ...............................................................................................158Table 12-2 Timer W Pins ........................................................................................................159

Section 14 Serial Communication Interface3 (SCI3)Table 14-1 Pin Configuration..................................................................................................189Table 14-2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) ......197Table 14-2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) ......198Table 14-2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3) ......199Table 14-3 Maximum Bit Rate for Each Frequency (Asynchronous Mode) ..........................199Table 14-4 BRR Settings for Various Bit Rates (Clocked Synchronous Mode).....................200Table 14-5 SSR Status Flags and Receive Data Handling ......................................................206Table 14-6 SCI3 Interrupt Requests........................................................................................223

Section 15 I2C Bus Interface (IIC)Table 15-1 I2C Bus Interface Pins...........................................................................................229

Rev. 3.0, 03/01, Page xxv of xxvi

Table 15-2 Communication Format ........................................................................................233Table 15-3 I2C Transfer Rate ..................................................................................................235Table 15-4 Flags and Transfer States ......................................................................................241Table 15-5 I2C Bus Timing (SCL and SDA Output)...............................................................258Table 15-6 Permissible SCL Rise Time (tsr) Values................................................................259Table 15-7 I2C Bus Timing (with Maximum Influence of tSr/tSf) ............................................260

Section 16 A/D ConverterTable 16-1 Pin Configuration..................................................................................................265Table 16-2 Analog Input Channels and Corresponding ADDR Registers ..............................266Table 16-3 A/D Conversion Time (Single Mode)...................................................................271

Section 17 EEPROMTable 17-1 Pin Configuration..................................................................................................277Table 17-2 Slave Addresses ....................................................................................................280

Section 19 Electrical CharacteristicsTable 19-1 Absolute Maximum Ratings .................................................................................287Table 19-2 DC Characteristics (1)...........................................................................................289Table 19-2 DC Characteristics (2)...........................................................................................293Table 19-2 DC Characteristics (3)...........................................................................................294Table 19-3 AC Characteristics ................................................................................................295Table 19-4 I2C Bus Interface Timing ......................................................................................297Table 19-5 Serial Interface (SCI3) Timing..............................................................................298Table 19-6 A/D Converter Characteristics ..............................................................................299Table 19-7 Watchdog Timer Characteristics...........................................................................300Table 19-8 Flash Memory Characteristics...............................................................................301Table 19-9 EEPROM Characteristics .........................................................................................303Table 19-10 DC Characteristics (1)...........................................................................................305Table 19-10 DC Characteristics (2)...........................................................................................310Table 19-11 AC Characteristics ................................................................................................311Table 19-12 I2C Bus Interface Timing........................................................................................313Table 19-13 Serial Interface (SCI3) Timing..............................................................................314Table 19-14 A/D Converter Characteristics ..............................................................................315Table 19-15 Watchdog Timer Characteristics...........................................................................316

AppendixTable A.1 Instruction Set .......................................................................................................3231. Data transfer instructions ........................................................................................................3232. Arithmetic instructions............................................................................................................3253. Logic instructions ...................................................................................................................3284. Shift instructions .....................................................................................................................3295. Bit manipulation instructions..................................................................................................3306. Branching instructions ............................................................................................................332

Rev. 3.0, 03/01, page xxvi of xxvi

7. System control instructions.....................................................................................................3348. Block transfer instructions ......................................................................................................335Table A.2 Operation Code Map (1) .......................................................................................336Table A.2 Operation Code Map (2) .......................................................................................337Table A.2 Operation Code Map (3) .......................................................................................338Table A.3 Number of Cycles in Each Instruction ..................................................................340Table A.4 Number of Cycles in Each Instruction ..................................................................341Table A.5 Combinations of Instructions and Addressing Modes ..........................................346

Rev. 3.0, 03/01, page 1 of 382

Section 1 Overview

1.1 Overview

• High-speed H8/300H central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 and H8/300H CPUs on an object level Sixteen 16-bit general registers 62 basic instructions

• Various peripheral functions Timer A (can be used as a time base for a clock) Timer V (8-bit timer) Timer W (16-bit timer) Watchdog timer SCI3 (Asynchronous or clocked synchronous serial communication interface) I2C Bus Interface (conforms to the I2C bus interface format that is advocated by Philips

Electronics)

10-bit A/D converter• On-chip memory

ROM Model EEPROM ROM RAM

F-ZTAT Version H8/3664N HD64N3664 512 bytes 32k 2,048 bytes

H8/3664F HD64F3664 32k 2,048 bytes

Mask ROM H8/3664 HD6433664 32k 1,024 bytes

Version H8/3663 HD6433663 24k 1,024 bytes

H8/3662 HD6433662 16k 512 bytes

H8/3661 HD6433661 12k 512 bytes

H8/3660 HD6433660 8k 512 bytes

• General I/O ports• I/O pins: 29 I/O pins (H8/3664N has 27 I/O pins), including 8 large current ports (IOL = 20mA,

@VOL = 1.5V)

• Input-only pins: 8 input pins (also used for analog input)• EEPROM interface (only for H8/3664N)

I2C Bus Interface (conforms to the I2C bus interface method presented by Philips)

• Supports various power-down states• Compact package

Rev. 3.0, 03/01, page 2 of 382

Package (Code) Body Size Pin Pitch

QFP-64 (FP-64E) 10.0 × 10.0 mm 0.5 mmQFP-64 (FP-64A) 14.0 × 14.0 mm 0.8 mmSDIP-42 (DP-42S) 14.0 × 37.3 mm 1.78 mmOnly QFP-64 (FP-64E) for H8/3664N

1.2 Internal Block Diagram

P10/TMOWP11P12

P14/P15/P16/

P17/ /TRGV

P50/P51/P52/P53/P54/P55/ /P56/SDAP57/SCL

PB0/AN0PB1/AN1PB2/AN2PB3/AN3PB4/AN4PB5/AN5PB6/AN6PB7/AN7

VC

C

VS

S

VC

L

TE

ST

AVCC

P20/SCK3P21/RXDP22/TXD

P80/FTCIP81/FTIOAP82/FTIOBP83/FTIOCP84/FTIODP85P86P87

P74/TMRIVP75/TMCIVP76/TMOV

OS

C1

OS

C2

X1

X2

CPUH8/300H

ROM RAM

SCI3

Por

t 1

Timer W

I2C businterface

Timer A Watchdogtimer

Timer VA/D

converter

Subclockgenerator

Systemclock

generator

Por

t 2

Por

t BP

ort 5

Por

t 7P

ort 8

Data bus (upper)

Address bus

Data bus (lower)

Figure 1-1 Internal Block Diagram of H8/3664 of the F-ZTATTM and Mask-ROM Versions

Rev. 3.0, 03/01, page 3 of 382

P10/TMOWP11P12

P14/P15/P16/

P17/ /TRGV

P50/P51/P52/P53/P54/P55/ /

PB0/AN0PB1/AN1PB2/AN2PB3/AN3PB4/AN4PB5/AN5PB6/AN6PB7/AN7

VC

C

VS

S

VC

L

TE

ST

AVCC

P20/SCK3P21/RXDP22/TXD

SDA

SCL

P80/FTCIP81/FTIOAP82/FTIOBP83/FTIOCP84/FTIODP85P86P87

P74/TMRIVP75/TMCIVP76/TMOV

OS

C1

OS

C2

X1

X2

CPUH8/300H

ROM RAM

EEPROM

SCI3Timer W

I2C businterface

I2C

bus

Timer A Watchdogtimer

Timer V A/Dconverter

Por

t 1

Subclockgenerator

Systemclock

generator

Por

t 2

Por

t 5P

ort B

Por

t 7P

ort 8

Data bus (upper)

Address bus

Note : The H8/3664N is a laminated-structure product in which an EEPROM chip is mounted on theH8/3664F-ZTATTM version.

Data bus (lower)

Figure 1-2 Internal Block Diagram of the F-ZTATTM Version H8/3664N with EEPROM

Rev. 3.0, 03/01, page 4 of 382

1.3 Pin Arrangement

NC

NC

AV

CC

X2

X1

VC

L

TE

ST

VS

S

OS

C2

OS

C1

VC

C

P50

/

P51

/

NC

NC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

NC

NC

P22

/TX

D

P21

/RX

D

P20

/SC

K3

P87

P86

P85

P84

/FT

IOD

P83

/FT

IOC

P82

/FT

IOB

P81

/FT

IOA

P80

/FT

CI

NC

NC

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

NC

NC

P14/

P15/

P16/

P17/ /TRGV

PB4/AN4

PB5/AN5

PB6/AN6

PB7/AN7

PB3/AN3

PB2/AN2

PB1/AN1

PB0/AN0

NC

NC

NC

NC

P76/TMOV

P75/TMCIV

P74/TMRIV

SCL

SDA

P12

P11

P10/TMOW

P55/ /

P54/

P53/

P52/

NC

NC

H8/3664N

Top view

Note: Do not connect NC pins.

Figure 1-3 Pin Arrangement of the F-ZTATTM-Version H8/3664N with EEPROM(FP-64E)

Rev. 3.0, 03/01, page 5 of 382

NC

NC

AV

CC

X2

X1

VC

L

TE

ST

VS

S

OS

C2

OS

C1

VC

C

P50

/

P51

/

NC

NC

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

NC

NC

P22

/TX

D

P21

/RX

D

P20

/SC

K3

P87

P86

P85

P84

/FT

IOD

P83

/FT

IOC

P82

/FT

IOB

P81

/FT

IOA

P80

/FT

CI

NC

NC

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

NC

NC

P14/

P15/

P16/

P17/ /TRGV

PB4/AN4

PB5/AN5

PB6/AN6

PB7/AN7

PB3/AN3

PB2/AN2

PB1/AN1

PB0/AN0

NC

NC

NC

NC

P76/TMOV

P75/TMCIV

P74/TMRIV

P57/SCL

P56/SDA

P12

P11

P10/TMOW

P55/ /

P54/

P53/

P52/

NC

NC

H8/3664

Top view

Note: Do not connect NC pins.

Figure 1-4 Pin Arrangement of H8/3664 of the F-ZTATTM and Mask-ROM Versions(FP-64E, FP-64A)

Rev. 3.0, 03/01, page 6 of 382

PB3/AN3

PB2/AN2

PB1/AN1

PB0/AN0

AVCCX2

X1

VCL

TEST

VSSOSC2

OSC1

VCCP50/

P51/

P52/

P53/

P54/

P55/ /

P10/TMOW

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

P17/ /TRGV

P16/

P15/

P14/

P22/TXD

P21/RXD

P20/SCK3

P87

P86

P85

P84/FTI0D

P83/FTI0C

P82/FTI0B

P81/FTI0A

P80/FTCI

P76/TMOV

P75/TMCIV

P

H8/3664 Series Hardware ManualHardware Manual ADE-602-202B Rev. 3.0 03/22/01 Hitachi, Ltd. Rev. 3.0, 03/01, page ii of xxvi Rev. 3.0, 03/01, Page iii of xxvi Cautions 1. Hitachi neither

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