GSM BASED AUTOMATIC TELLAR MACHINE OPERATION There s a lot of requirement to automate the security to ensure the security of the ATM’s, according to this project whenever if a person forget his ATM card can also access the ATM’s by using their security passwords by sending an SMS to the ATM. The security system will use GSM interface to inform the authorized person. The GSM modem which is provided inside the tellar machine is installed with an SIM reader and is given a number. By sending the message to the number we can access our account. The remaining process continues so that in case of ATM card damage or misplace this solution works better. The system can work standalone and can also be integrated to a computer using RS232 port. The complete code for the embedded system is going to be developed using c- language.
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
GSM BASED AUTOMATIC TELLAR MACHINE OPERATION
There s a lot of requirement to automate the security to ensure the security of the
ATM’s, according to this project whenever if a person forget his ATM card can also access
the ATM’s by using their security passwords by sending an SMS to the ATM.
The security system will use GSM interface to inform the authorized person. The
GSM modem which is provided inside the tellar machine is installed with an SIM reader and
is given a number. By sending the message to the number we can access our account. The
remaining process continues so that in case of ATM card damage or misplace this solution
works better.
The system can work standalone and can also be integrated to a computer using RS232
port. The complete code for the embedded system is going to be developed using c-language.
INTRODUCTION
Firstly, let us know about Embedded System—
What is Embedded System?
An embedded system is a special-purpose computer system designed to perform one or a few dedicated functions, sometimes with real-time computing constraints. It is usually embedded as part of a complete device including hardware and mechanical parts. In contrast, a general-purpose computer, such as a personal computer, can do many different tasks depending on programming.
Embedded systems have become very important today as they control many of the common devices we use. Since the embedded system is dedicated to specific tasks, design engineers can optimize it, reducing the size and cost of the product, or increasing the reliability and performance. Some embedded systems are mass-produced, benefiting from economies of scale.
According into performance and functionalities embedded system is classified into 4 types:
Standalone embedded system Networking embedded system Real time embedded system Mobile embedded system
STANDALONE EMBEDDED SYSTEM
The standalone word tells that giving the inputs and getting the results/outputs. Here examples for input are pressing a switch, transducer
Examples for output are LCD, buzzer, monitor and printers
NETWORKING EMBEDDED SYSTEM
A set of nodes which are connected through either wired or wireless are called networking embedded system
Examples for wired n/w are LAN in colleges, internet
Examples for wireless n/w are wifi, zigbee in coming sections
REAL TIME EMBEDDED SYSTEM
The most powerful and popular embedded system is real time embedded system.
They are 2 types:
Soft real time Hard real time
MOBILE EMBEDDED SYSTEM
It is not a pure embedded system. It is a combination of both embedded system and VLSI. In this designing part will comes under VLSI and fabrication and coding part will comes under embedded system
An embedded system is some combination of computer hardware and software, either
fixed in capability or programmable, that is specifically designed for a particular kind of
application device. Industrial machines, automobiles, medical equipment, cameras, household
appliances, airplanes, vending machines, and toys (as well as the more obvious cellular phone
and PDA) are among the myriad possible hosts of an embedded system. Embedded systems
that are programmable are provided with a programming interface, and embedded systems
programming is a specialized occupation.
Certain operating systems or language platforms are tailored for the embedded market, such
as Embedded Java and Windows XP Embedded. However, some low-end consumer products
use very inexpensive microprocessors and limited storage, with the application and operating
system both part of a single program. The program is written permanently into the system's
memory in this case, rather than being loaded into RAM (random access memory), as
Automatic Teller Machines (ATMs) are self service banking machines that allows
customers to access their bank account without the aid of a bank teller or bank clerk They are
use for financial transactions, they operate 24 hour a day helping customers to withdraw cash,
deposit cash, transfer funds, check account balance, and print statement of account . They are
placed in convenient locations such as the retail outlets, banking premises, grocery stores,
shopping malls and gas stations. They make banking transaction easier, by helping banks to
meet the demands of their customers; customers do not need to go to the banking hall or even
in some cases they do not need to queue in banks just to make basic banking transactions.
Some ATM machines allow customers of different banks to perform basic banking
transactions without going to their bank or their banks ATM machine. Despite all these
advantages, it has been reported in that customers and banks are faced with a lot of ATM
fraud and other ATM security related problems. Therefore, there is a need to provide a means
of securing ATM transaction against frauds and crimes. This study presents how Short
Message Service (SMS) encrypted message can help make ATMs more secured. The
proposed technology includes the use of existing Personal Identification Number (PIN) to
provide authentication of the card to card issuer host system and the use of SMS encrypted
message to authenticate customers before any transaction can take place at the ATM
machine.
How does it works
ATMs have a small display and either touch screen or input devices for entering inputs. To access their bank account, customers insert a plastic card into the magnetic stride reader. The plastic cards are issued by the holder’s bank. The magnetic stride card contains an identification code that is transmitted to the banks central computer through a host computer. This identification code identifies the holder of the ATM card. The ATM asks for a PIN which is use to authenticate the user. If the user is authenticated, the ATM permits the transaction with the banking computer.
“So, through the password entry from the mobile phone
the customer can access his account. The details of
account and the customer are verified through the host
computer and the transaction is done through the bank
computer”
AT89S52 MICROCONTROLLER
INTRODUCTION:
Micro controller is a true computer on a chip the design incorporates all of the
features found in a microprocessor CPU: arithmetic and logic unit, stack pointer, program
counter and registers. It has also had added additional features like RAM, ROM, serial
I/O, counters and clock circuit.
Like the microprocessor, a microcontroller is a general purpose device, but one
that is meant to read data, perform limited calculations on that data and control it’s
environment based on those calculations. The prime use of a microcontroller is to control
the operation of a machine using a fixed program that is stored in ROM and that does not
change over the lifetime of the system. The design approach of a microcontroller
uses a more limited set of single byte and double byte instructions that are used to move
code and data from internal memory to ALU. Many instructions are coupled with pins on
the IC package; the pins are capable of having several different functions depending on
the wishes of the programmer. The microcontroller is concerned with getting the data
from and on to its own pins.
DESCRIPTION
The AT89S52 is a low power, high-performance CMOS 8-bit microcontroller with
8K bytes of in system programmable Flash memory. The device is manufactured using
Atmel’s high-density nonvolatile memory technology and is compatible with the
industry- standard 80C51 instruction set and pin out. The on-chip Flash allows the
program memory to be reprogrammed in-system or by a conventional nonvolatile
memory programmer. By combining a versatile 8-bit CPU with in-system programmable
Flash on a monolithic chip, the Atmel AT89S52 is a powerful microcontroller, which
provides a highly flexible and cost-effective solution to many embedded control
applications. The AT89S52 provides the following standard features.
Compatible with MCS-51® Products
8K Bytes of In-System Programmable (ISP) Flash Memory
Endurance: 1000 Write/Erase Cycles
4.0V to 5.5V Operating Range
Fully Static Operation: 0 Hz to 33 MHz
Three-level Program Memory Lock
256 x 8-bit Internal RAM
32 Programmable I/O Lines
Three 16-bit Timer/Counters
Eight Interrupt Sources
Full Duplex UART Serial Channel
Low-power Idle and Power-down Modes
Interrupt Recovery from Power-down Mode
Watchdog Timer
Dual Data Pointer
Power-off Flag
Fast Programming Time
Flexible ISP Programming (Byte and Page Mode)
In addition, the AT89S52 is designed with static logic for operation down to zero frequency
and supports two software selectable power saving modes. The Idle Mode stops the CPU
while allowing the RAM, timer/counters, serial port, and interrupt system to continue
functioning. The Power-down mode saves the RAM contents but freezes the oscillator,
disabling all other chip functions until the next interrupt or hardware reset.
DATA MEMORY
The AT89C52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a
parallel address space to the Special Function Registers. That means the upper 128 bytes have
the same addresses as the SFR space but are physically separate from SFR space. When an
instruction accesses an internal location above address 7FH, the address mode used in the
instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR
space. Instructions that use direct addressing access SFR space.
SPECIAL FUNCTION REGISTERS
A map of the on-chip memory area called the Special Function Register (SFR) space
is present in 89c52. All of the addresses are occupied, and unoccupied addresses may not be
implemented on the chip. Read accesses to these addresses will in general return random
data, and write accesses will have an indeterminate effect. User software should not write 1s
to these unlisted locations, since they may be used in future products to invoke new features.
In that case, the reset or inactive values of the new bits will always be 0F.
PIN DESCRIPTION
VCC : Supply +5v voltage
VSS : Circuit ground potential.
XTAL1 : Input to the inverting oscillator amplifier and input to the internal clock operating
circuit
XTAL 2: : Output from the inverting oscillator amplifier
RST : Reset input. A high on this pin for two machine cycles while the oscillator is running
resets the device. This pin drives high for 98 oscillator periods after the Watchdog timeout.
The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the
default state of bit DISRTO, the RESET HIGH out feature is enabled.
Figure 3.1: pin description of AT89S52.
ALE/PROG :
Address Latch Enable (ALE) is an output pulse for latching the low byte of
the address during accesses to external memory. This pin is also the program
pulse input (PROG) during Flash programming. In normal operation, ALE is
emitted at a constant rate of 1/6 the oscillator frequency and may be used for
external timing or clocking purposes. Note, however, that one ALE pulse is
skipped during each access to external data memory. If desired, ALE operation
A
T
8
9
S
52
can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is
active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly
pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in
external execution mode.
PSEN :
Program Store Enable (PSEN) is the read strobe to external program
memory. When the AT89S52 is executing code from external program memory,
PSEN is activated twice each machine cycle, except that two PSEN activations
are skipped during each access to external data memory.
EA/VPP :
External Access Enable. EA must be strapped to GND in order to enable
the device tram memory locations starting at 0000H up to FFFFH .Note, however,
that if lock bit 1 is programmed, EA will be internally latched on reset .EA should
be strapped to VCC for internal program executions. This pin also receives the
12-volt programming enable voltage (VPP) during Flash programming.
Port 0 :
Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each
pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be
used as high impedance inputs. Port 0 can also be configured to be the
multiplexed low-order address/data bus during accesses to external program and
data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the
code bytes during Flash programming and outputs the code bytes during
program verification. External pull-ups are required during program verification.
Port 0 pins Alternate function
P0.0-P0.7 Port 0 is an 8-bit open drain bidirectional I/O
port.
Table:3.1 Port 0 pin explanation
Port 1 :
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1
output buffers can sink/source four TTL inputs. When 1s are written to Port 1
pins, they are pulled high by the internal pull-ups and can be used as inputs. As
inputs, Port 1 pins that are externally being pulled low will source current (IIL)
because of the internal pull-ups. In addition, P1.0 and P1.1 can be configured to
be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2
trigger input (P1.1/T2EX), respectively, as shown in the following table. Port 1
also receives the low-order address bytes during Flash programming and
Verification
Table 3.2: Port 1 pin explanation
Port 2 :
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can
sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal
pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will
source current (IIL) because of the internal pull-ups .Port 2 emits the high-order address byte during
fetches from external program memory and during accesses to external data memory that use 16-bit
addresses (MOVX @DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s.
During accesses to external data memory that uses 8-bit addresses (MOVX @ RI), Port 2 emits the
contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and
some control signals during Flash programming and verification.
Port 2 pins Alternate functions
P2.0-P2.7 Port 2 is an 8-bit bidirectional I/O port with
internal pull-ups.
Table: 3.3 Port 2 pin explanation
Port 3:
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3
output buffers can sink/source four TTL inputs. When 1s are written to Port 3
pins, they are pulled high by the internal pull-ups and can be used as inputs. As
inputs, Port 3 pins that are externally being pulled low will source current (IIL)
because of the pull-ups. Port 3 receives some control signals for Flash
programming and verification. Port 3 also serves the functions of various special
features of the AT89S52, as shown in the following table.
Table 3.4: Port 3 pin explanation.
SPECIAL FUNCTION REGISTERS:
A map of the on-chip memory area called the Special Function Register
(SFR) space is shown in Table 1.Note that not all of the addresses are occupied,
and unoccupied addresses may not be implemented on the chip. Read accesses
to these addresses will in general return random data, and write accesses will
have an indeterminate effect.User software should not write1s to these unlisted
locations, since they may be used in future products to invoke new features. In
that case, the reset orinactive values of the new bits will always be 0.
TIMER 2 REGISTERS:
Control and status bits are contained in registers T2CON (shown in Table
2) and T2MOD (shown in Table 6) for Timer 2. The register pair (RCAP2H,
RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or
16-bitauto-reload mode.
INTERRUPT REGISTERS:
The individual interrupt enable bits are in the IE register. Two priorities can
be set for each of the six-interrupt sources in the IP register.
Table 3.5: AT89S52 SFR map and reset values
UART
The UART in the AT89S52 operates the same way as the UART in the
AT89C51 andAT89C52. For further information on the UART operation, refer to
the ATMEL Web site. From the home page, select “Products”, then “8051-
ArchitectureFlash Microcontroller”, then “Product Overview”.
TIMER 0 AND 1
Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and
Timer 1 in the AT89C51 and AT89C52. For further information on the timers”
operation, refer to the ATMEL Web site. From the home page, select “Products”,
then“8051-Architecture Flash Microcontroller”, then “Product Overview”.
INTERRUPTS
The AT89S52 has six interrupt vectors: two external interrupts (INT0 and
INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt.
These interrupts are all shown in Figure 6. Each of these interrupt sources can be
individually enabled or disabled by setting or clearing a bit in Special Function
Register IE. IE also contains a global disable bit, EA, which disables all interrupts
at once. Note that Table 5 shows that bit position IE.6 is unimplemented.
User software should not write a 1s to this bit position, since it may be
used in future AT89 products. Timer 2 interrupt is generated by the logical OR of
bits TF2 and EXF2 in registerT2CON. Neither of these flags is cleared by
hardware when the service routine is vectored to. In fact, the service routine
may have to determine whether it was TF2 or EXF2 that generated the interrupt,
and that bit will have to be cleared in software The Timer 0 and Timer 1 flags,
TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The
values are then polled by the circuitry in the next cycle. However, the Timer 2
flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer
overflows.
Figure 3.5: interrupt source
Table 3.9 Interrupt enables register
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an inverting
amplifier that can be configured for use as an on-chip oscillator, as shown in
Figure 7. Either a quartz crystal or ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left unconnected while
XTAL1 is driven, as shown in Figure 8.There are no requirements on the duty
cycle of the external clock signal, since the input to the internal clocking circuitry
is through a divide-by-two flip-flop, but minimum and maximum voltage high and
low time specifications must be observed.
IDLE MODE
In idle mode, the CPU puts itself to sleep while all the on-chip peripherals
remain active. The mode is invoked by software. The content of the on-chip RAM
and all the special functions registers remain unchanged during this mode. The
idle mode can be terminated by any enabled interrupt or by a hardware reset.
Note that when idle mode is terminated by a hardware reset, the device normally
resumes program execution from where it left off, up to two machine cycles
before the internal reset algorithm takes control. On-chip hardware inhibits
access to internal RAM in this event, but access to the port pins is not inhibited.
To eliminate the possibility of an unexpected write to a port pin when idle mode
is terminated by a reset, the instruction following the one that invokes idle mode
should not write to a port pin or to external memory.
Figure 3.6: Oscillator connection
Figure 3.7 External clock drive configuration.
Table 3.10: Status of external pins during idle and power down model
PROGRAM MEMORY LOCK BITS
The AT89S52 has three lock bits that can be left un programmed (U) or
can be programmed(P) to obtain the additional features listed in the following
table.
Table 3.11: lock bit protection modes.
When lock bit 1 is programmed, the logic level at the EA pin is sampled and
latched during reset. If the device is powered up without a reset, the latch
initializes to a random value and holds that value until reset is activated. The
latched value of EA must agree with the current logic level at that pin in order for
the device to function properly.
INTERFACING DEVICES
EEPROM
Description
The AT24C01A/02/04/08/16 provides 1024/2048/4096/8192/16384 bits of
serial electrically erasable and programmable read-only memory (EEPROM) organized as
128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage operation are
essential. The AT24C01A/02/04/08/16 is available in space-saving 8-lead PDIP, 8-lead
JEDEC SOIC, 8-lead MAP, 5-lead SOT23 (AT24C01A/AT24C02/AT24C04), 8- lead
TSSOP and 8-ball dBGA2 packages and is accessed via a 2-wire serial interface.
Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge
clock data into each EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address
inputs that are hard wired for the AT24C01A and the AT24C02. As many as eight 1K/2K
devices may be addressed on a single bus system (device addressing is discussed in detail
under the Device Addressing section).
The AT24C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K
devices may be addressed on a single bus system. The A0 pin is a no connect.
The AT24C08 only uses the A2 input for hardwire addressing and a total of two 8K
devices may be addressed on a single bus system. The A0 and A1 pins are no connects.
The AT24C16 does not use the device address pins, which limits the number of
devices on a single bus to one. The A0, A1 and A2 pins are no connects.
WRITE PROTECT (WP): The AT24C01A/02/04/16 has a Write Protect pin that provides
hardware data protection. The Write Protect pin allows normal read/write operations when
connected to ground (GND). When the Write Protect pin is connected to VCC, the write
protection feature is enabled and operates as shown in the following table.
Memory Organization AT24C01A, 1K SERIAL EEPROM: Internally organized with 16
pages of 8 bytes each, the 1K requires a 7-bit data word address for random word addressing.
AT24C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each, the
2K requires an 8-bit data word address for random word addressing.
AT24C04, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the
4K requires a 9-bit data word address for random word addressing.
AT24C08, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the
8K requires a 10-bit data word address for random word addressing
AT24C16, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each,
the 16K requires an 11-bit data word address for random word addressing.
LIQUID CRYSTAL DISPLAY
LCD (liquid crystal display) projectors usually contain three separate LCD glass
panels, one each for the red, green, and blue components of the video signal being fed into
the projector. As light passes through the LCD panels, individual pixels ("picture elements")
can be opened to allow light to pass or closed to block the light, as if each little pixel were
fitted with a Venetian blind. This activity modulates the light and produces the image that is
projected onto the screen.
DLP ("Digital Light Processing") is a proprietary technology developed by Texas
Instruments. It works quite differently than LCD. Instead of having glass panels through
which light is passed, the DLP chip is a reflective surface made up of thousands of tiny
mirrors. Each mirror represents a single pixel.
In a DLP projector, light from the projector's lamp is directed onto the surface of the
DLP chip. The mirrors wobble back and forth, directing light either into the lens path to turn
the pixel on, or away from the lens path to turn it off.
In very expensive DLP projectors, there are three separate DLP chips, one each for
the red, green, and blue channels. However, in most DLP projectors under $20,000 there is
only one chip. In order to define color, there is a color wheel that consists of red, green, blue,
and sometimes white (clear) filters. This wheel spins in the light path between the lamp and
the DLP chip and alternates the color of the light hitting the chip from red to green to blue.
The mirrors tilt away from or into the lens path based upon how much of each color is
required for each pixel at any given moment in time. This activity modulates the light and
produces the image that is projected onto the screen. (In addition to red, green, blue, and
white segments, some color wheels now use dark green or yellow segments as well.)
PIN DESCRIPTION OF THE LCD
table:8 Pin description of LCD
INTERFACING LCD TO MICROCONTROLLER:
Fig:15 Interfacing LCD to microcontroller
A typical LCD write operation takes place as shown in the following timing
waveform:
8051
ER/WWRS
DB7–DB0
LCD control
communications bus
Microcontroller
8
Fig:16 LCD Data waveform
The interface is either a 4-bit or 8-bit parallel bus that allows fast reading/writing of
data to and from the LCD. This waveform will write an ASCII Byte out to the LCD's screen.
The ASCII code to be displayed is eight bits long and is sent to the LCD either four or eight
bits at a time. If 4-bit mode is used, two nibbles of data (First high four bits and then low four
bits with an E Clock pulse with each nibble) are sent to complete a full eight-bit transfer. The
E Clock is used to initiate the data transfer within the LCD.8-bit mode is best used when
speed is required in an application and at least ten I/O pins are available. 4-bit mode requires
a minimum of six bits. In 4-bit mode, only the top 4 data bits (DB4-7) are used. The R/S pin
is used to select whether data or an instruction is being transferred between the
microcontroller and the LCD. If the pin is high, then the byte at the current LCD Cursor
Position can be read or written. If the pin is low, either an instruction is being sent to the LCD
or the execution status of the last instruction is read back (whether or not it has completed).
Table: 9 LCD commands
keypad
A keypad is a set of buttons arranged in a block which usually bear digits and other
symbols but not a complete set of alphabetical letters. If it mostly contains numbers then it
can also be called a numeric keypad. Keypads are found on many alphanumeric keyboards
and on other devices such as calculators, combination locks and telephones which require
largely numeric input.
A telephone keypad
A computer keyboard usually contains a small numeric keypad with a calculator-style
arrangement of buttons duplicating the numeric and arithmetic keys on the main keyboard to
allow efficient entry of numerical data. This number pad (commonly abbreviated to
"numpad") is usually positioned on the right side of the keyboard because most people are
right-handed.
Many laptop computers have special function keys which turn part of the alphabetical
keyboard into a numerical keypad as there is insufficient space to allow a separate keypad to
be built into the laptop's chassis. Separate plug-in keypads can be purchased.
A calculator
By convention, the keys on calculator-style keypads are arranged such that 123 is on
the bottom row. In contrast, a telephone keypad has the 123 keys at the top. It also has
buttons labelled * (star) and # (octothorpe, number sign, "pound" or "hash") either side of the
zero. Most of the keys also bear letters which have had several auxiliary uses, such as
remembering area codes or whole telephone numbers.
The keypad of a calculator contains the digits 0 through 9, together with the four
arithmetic operations, the decimal point and other more advanced functions.
Keypads are a part of mobile phones that are replaceable and sit on a sensor board.
Some multimedia mobile phones have a small joystick which has a cap to match the keypad.
Keypads are also a feature of some combination locks. This type of lock is often used
on doors, such as that found at the main entrance to some offices.
A telephone keypad
REGULATED POWER SUPPLY
A variable regulated power supply, also called a variable bench power supply, is one
where you can continuously adjust the output voltage to your requirements. Varying the
output of the power supply is the recommended way to test a project after having double
checked parts placement against circuit drawings and the parts placement guide.
This type of regulation is ideal for having a simple variable bench power supply.
Actually this is quite important because one of the first projects a hobbyist should undertake
is the construction of a variable regulated power supply. While a dedicated supply is quite
handy e.g. 5V or 12V, it's much handier to have a variable supply on hand, especially for
testing.
Most digital logic circuits and processors need a 5 volt power supply. To use these
parts we need to build a regulated 5 volt source. Usually you start with an unregulated power
To make a 5 volt power supply, we use a LM7805 voltage regulator IC (Integrated Circuit).
The IC is shown below.
The LM7805 is simple to use. You simply connect the positive lead of your
unregulated DC power supply (anything from 9VDC to 24VDC) to the Input pin, connect the
negative lead to the Common pin and then when you turn on the power, you get a 5 volt
supply from the Output pin.
CIRCUIT FEATURES
Brief description of operation: Gives out well regulated +5V output, output current capability of 100 mA
Circuit protection: Built-in overheating protection shuts down output when regulator IC gets too hot
Circuit complexity: Very simple and easy to build
Circuit performance: Very stable +5V output voltage, reliable operation
Availability of components: Easy to get, uses only very common basic components
Design testing: Based on datasheet example circuit, I have used this circuit succesfully as part of many electronics projects
Applications: Part of electronics devices, small laboratory power supply
Power supply voltage: Unreglated DC 8-18V power supply
Power supply current: Needed output current + 5 mA
Component costs: Few dollars for the electronics components + the input transformer cost
BLOCK DIAGRAM
EXAMPLE CIRCUIT DIAGRAM:
RIDE and ISP 3.0
Ride
Please note that in this page RIDE will reference to RIDE6 software which supports
8051, XA and other derivates. For ARM, ST7 and STM8 family thesoftwareisRIDE7.
RIDE is a fully featured Integrated Development Environment (IDE) that provides
seamless integration and easy access to all the development tools. From editing to compiling,
linking, debugging and back to the start, with a Simulator, ICE, Rom Monitor or other
debugging tools, RIDE conveniently manages all aspects of the Embedded Systems
development with a single user interface.
Multi-file Editor
RIDE is based on a fast multi-document editor designed to meet the specific needs of
programming. The various methods, menus, commands, and shortcuts are all fully compliant
with the Microsoft® specifications for Windows 2000, XP and NT. Classic commands, such
as string search and block action are integrated. Advanced features such as Matching
Delimiter (parenthesis, brackets), Grep (multi-file search) and Indenter are integrated as well.
The customizable color-highlighting feature is very useful to indicate specific syntactic
elements as they appear in the source file: keywords, comments, identifiers, operators, and so
on. The color-highlighting feature is automatically keyed to the intrinsic file type (which
means, it works differently for C and assembler)
This permits the user to identify quickly and easily those parts of the code responsible for