Group Number One GITHU Processor Tom Bozic Ian Nuber Greg Ramsey Henry Romero Matt Unangst.

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Group Number One GITHU Processor Tom Bozic Ian Nuber Greg Ramsey Henry Romero Matt Unangst Slide 2 GITHU Processor General Purpose 32-bit, pipelined computer processor MIPS-like architecture Reduced instruction set 16-bit address space 16 Registers R0 = 0 R15 = return address Slide 3 FPGA RAMROM Ribbon Cable Data/Address Ribbon Cable Level Shift Interrupt Controller / Chip Select Ribbon Cable Level Shift Key Pad LCD Monitor Out Keyboard In I/O UART Interrupt Data Ribbon Cable Slide 4 Instruction Set Architecture First two bits indicate instruction category Load, store, bra/jump, R-type 16 bit immediate built into R-type reduces complexity of design Addressing Modes Direct Indirect with Offset ISA accounts for full address space NO PC-relative addressing Slide 5 Instruction Format 31 30 29 24 23 20 19 16 15 0 Op(2)Addr(6)Rt (4)Rs (4)Address Displacement (16) 31 30 29 25 24 23 20 19 16 15 12 11 0 31 30 29 26 25 24 23 20 19 0 Op(2)Type(4)Addr (2)Rs (4)Address Continued (20) Load / Store R-Type Bra / Jmp Op (2)Funct (5)Imm (1)Rd (4)Rs1 (4)Rs2 (4)Immediate (12) Slide 6 Load/Store Instructions (Op = 00/01) InstructionAssemblyMeaning LdLd 0[r3], r2 R2 Mem(r3) StSt r4, 4[r3] R4 Mem(r3 + 4) Slide 7 R-Type Instructions (OP = 10) InstructionFunctionImmedAssembly ExMeaning (** = bitwise op) Add000000Add r2, r3, r4R2 = R3 + R4 Addi000001Addi r2, r2, 5R2 = R2 + 5 Sub000010Sub r6, r3, r5R6 = R3 R5 Subi000011Subi r3, r4, 3R3 = R4 3 And001000And r3, r2, r8R3 = R2 & R8 ** Andi001001Andi r4, r4, 255R4 = R4 & 0xFF ** Or001100Or r2, r3, r4R2 = R3 | R4 ** Ori001101Ori r2, r8, 10R2 = R8 | 0xA ** Nand001010Nand r3, r5, r9R3 = !(R5 & R9) ** Nor001110Nor r2, r1, r4R2 = !(R1 | R4) ** Xor100100Xor r3, r4, r5R3 = R4 ! R5 Mult110000Mult r2, r3, r4R2 = R3 * R4 Div111000Div r4, r5, r2R4 = R5 / R2 Slide 8 R-Type Instructions (Contd) InstructionFunctionImmedAssembly ExMeaning (** = bitwise op) Sll010000Sll r2, r2, r3R2 = [R2] > R3 Sal010100Sal r4, r4, r3R2 = [R4] > R3 Scl011000Scl r4, r4, 1Circular shift left Scr011010Scr r3, r3, 1Circular shift right Slt100000Slt r2, r3, r4R2 =1 IF R3