Group 1 – Week 9

Group 1 – Week 9

Almost done…

Jumps and Branches• Worked on completeing both the jumps and branches• With jumps had to be concerned with three different types:

– Regular jumps fairly straight forward.– Jump and Links had to make sure that the right values were written to the

right register– Jump Register had to add another control signal

• Branches were more complicated– Created a Branch Unit which did the check for zero and updated the branch

address.– Through testing discovered the several different problems with pushing it to

the ID stage– Still trying to determine if all the timing issues have been worked out

Jump and Link Unit

General Testing

• Ran through a large array of tests trying to find small bugs– Clock signal needed to be inverted– Had the wrong control signal input into data

hazard– Control signal had to be reversed so that the

processor wouldn't crash on restart– Determine how to get stalling to work properly

• Now space is becoming an issue

Forwarding & Hazards

• Finished forwarding unit according to book• Noticed the book doesn’t forward from WB back

to MEM (Load then Store), added that logic too– Prioritized so that we always forward furthest back in

the pipeline • MEM wins over WB, its value is more accurate

– Bug found: don’t forget to take FPR / GPR into account

• Used hazard equation in book, pretty simple

Tests to make sure both Rs & Rd are FPR or both GPR top rightTests for zeros at bottom rightRegister address comparisons at center, outputs at topAdditional Equations:If Wb.GPR Write && MEM.Write && (Wb.Rd != 0) && (Wb.Rd == Ex.Rd)

Hazards & Forwarding for Branches

• Pushing up branch comparison to ID creates problems– Our forwarding unit only forwards back to the EX

input muxes• Had to create new forwarding unit from MEM & WB

back to ID

– Data hazard when branch Rs in ID stage == Rd for any instruction in EX• Added to stall unit

This unit is simpler than the other forwarding unit.- branches only use Rs, not Rt- we never use FPR’s here, no need to test both signals- only one mux to control, not two

-Equations:If (ID.Rs == Mem.Rd) && (Mem.Rd !=0) Mem.GPRWrite && ID.BranchIf (ID.Rs == WB.Rd) && (WB.Rd !=0) && (Wb.Rd != Mem.Rd) && WB.GPRWrite && ID.Branch

Next Steps

• Finish!• Hardware– Everything is done except Trap & RFE units• Have control signals for this already

• Testing– Only complicated hazards, stalls, and forwarding

situations to go

Not catching

exceptions = bad