Greetings from Multi-scale and Multi-physics Modeling Their Role in 3D Integration Multi-scale and Multi-physics Modeling Their Role in 3D Integration IEEE EMC Society & Georgia Tech IEEE EMC Society & Georgia Tech Madhavan Swaminathan Distinguished Lecturer, IEEE EMC Society Joseph M. Pettit Professor in Electronics School of Electrical and Computer Engg. Director, Interconnect and Packaging Center
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Greetings from
Multi-scale and Multi-physics Modeling
Their Role in 3D Integration
Multi-scale and Multi-physics Modeling
Their Role in 3D Integration
IEEE EMC Society & Georgia TechIEEE EMC Society & Georgia Tech
Is Moore’s Law Sufficient for System Miniaturization ?
Is Moore’s Law Sufficient for System Miniaturization ?
Georgia Institute of Technology Feb 2012
Stacking using Wirebond (past)
Stacking using TSV (future)
POP Stacking (present)
Ref: R. Tummala and M. Swaminathan, “Introduction to System on Package”, McGraw Hill, 2008
3D Z-directioninterconnections
3D Integration Technologies3D Integration Technologies
Georgia Institute of Technology Feb 2012
CPU and Memory Integration TrendCPU and Memory Integration Trend
Inte
gra
tion
Den
sity
Time
Multichip Package
DDR3
Stacked POPLPDDR
Stacked PIPLPDDR+Analog
Stacked TSV
Wide I/O
4.8nJ/word
512pJ/word
512pJ/word
2-7pJ/word
� Power Budgeting 10X increase in 10 Years� 30-50% increase in I/O Power (Mobile)� 3D w/ TSV reduces power by 4-10X� Interconnect/Packaging Based Solution
Courtesy: Part Greg Taylor, Intel and Paul Franzon, NC State
Georgia Institute of Technology Feb 2012
� First Killer Product in 2013
� Wide I/O Memory� Mobile product application
� 512 I/Os transmitting at 12.8Gbps (3.2Gbps
in LPDDR2 memory)
� 8X improvement in Bandwidth� 35% decrease in package size
K. J. Han, M. Swaminathan and T. Bandhyopadyay, “Electromagnetic Modeling of Through-Silicon Via (TSV) Interconnections using Cylindrical Modal Basis Functions”, IEEE Trans. on Advanced Packaging, 2010
V. Sridharan, M. Swaminathan, and T. Bandyopadhyay, “Enhancing Signal and Power Integrity Using Double Sided Silicon Interposer,” IEEE
Microwave and Wireless Components Letters, To be Published in Dec. 2011
Microstrip Transition with Power and Ground Planes
Microstrip Transition with Power and Ground Planes
Georgia Institute of Technology Feb 2012
Start with FDTD
222
111
1
zyxc
t
∆+
∆+
∆
<∆
� Yee Grid Limited by the CFL stability condition Can lead to long simulation time for multi-scale dimensions� However, FDTD is memory efficient
Expand the fields
Ez Hy
Marching on Time
� Unconditional Stability
� Reduces simulation time for multi-scale dimensions – time step not limited by CFL condition� Domain decomposition techniques can be applied to reduce memory and increase capacity
Marching on Degree
qEEE ,....,, 10
0 5 10 15 20 25 30-0.5
0
0.5
1
p=0
p=1
p=2
p=3
p=4
Laguerre basis functions
Laguerre Finite Difference Time Domain (FDTD) MethodLaguerre Finite Difference Time Domain (FDTD) Method
Georgia Institute of Technology Feb 2012
22
Laguerre-FDTD
SLeEC
Improvement
Laguerre-domainTime-domain
Maxwell’s equations
in time-domain
Maxwell’s equations
in Laguerre-domain
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 50
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Time (ns)
J (A
/m2)
0 20 40 60 80 100 120 140 160 180 200-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
Coefficient #
Am
plit
ude
0 20 40 60 80 100 120 140 160 180 200-3000
-2000
-1000
0
1000
2000
3000
4000
Coefficient #
Am
plit
ude
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5-800
-600
-400
-200
0
200
400
600
800
1000
1200
Time (ns)
J (A
/m2)
SourceSource
Solution
[5] Y.-S. Chung, T. K. Sarkar, B. H. Jung and M. Salazar-Palma, "An unconditionally stable scheme for the finite-difference time-domain method," IEEE Trans. Microw. Theory Tech., vol. 51, no. 3, pp. 697-704, Mar 2003. [6] K. Srinivasan, Multiscale EM and Circuit Simulation Using the Laguerre-FDTD Scheme for Package-Aware Integrated-Circuit Design. PhD Thesis, Georgia Institute of Technology, 2008
[1] K. S. Yee, "Numerical solution of initial boundary value problems involving Maxwell’s equations in isotropic media," IEEE Trans. Antennas Propag., vol. 14, no. 3, pp. 302-307, Mar 1966. [2] Shumin Wang, “Numerical Examinations of the Stability of FDTD Subgridding Schemes,” ACES Journal, Vol. 22, No. 2, July 2007[3] T. Namiki and K. Ito, "A new FDTD algorithm free from the CFL condition restraint for a 2D-TE wave," in IEEE AP-S Symp. Dig., Orlando, FL, 1999. [4] F. Zheng and Z. Chen, "Numerical Dispersion Analysis of the Unconditionally Stable 3-D ADI–FDTD Method," IEEE Trans. Microwave Theory and Tech., vol. 49, no. 5, pp. 1006-1009, May 2001.
Prior Time Domain Methods
Laguerre-FDTD Methods
SLeEC (Simulation using Laguerre-Equivalent Circuit) [6]
J. Xie, D. Chung, M. Swaminathan, et al, “Electrical-thermal co-analysis for power delivery networks in 3D system integration,” IEEE International Conference on 3D System Integration (3DIC), pp. 1-4, Sept. 2009.
J.Xie, D. Chung, M. Swaminathan, M. Mcallister, et al, “Effect of system components on electrical and thermal characteristics for power delivery networks in 3D system integration,” 18th conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), pp. 113-116, Oct. 2009.
Georgia Institute of Technology Feb 2012
Max temperature v.s. flow velocity
J. Xie, M. Swaminathan, “Electrical-thermal co-simulation with micro-channel water cooling in 3D integration,” accepted
with revision by IEEE Trans. Advanced Packaging, 2010.
Correlation with measurement
3D System with micro-channels
40 50 60 70 80 90 100 11020
25
30
35
Ou
tlet
Tem
pera
ture
(D
eg
ree)
Flow Rate (m l/m in)
Simulation
Measurement
Heat Conduction, Air Convection and Micro-fluidic CoolingHeat Conduction, Air Convection and Micro-fluidic Cooling
S. M. Sri-Jayantha, et al, "Thermomechanical modeling of 3D electronic packages," IBM J. RES. & DEV., Vol. 52, No. 6, Nov. 2008.
� TSV induced stress is very large at the TSV-silicon interface � Relatively small as the distance from the TSV increases� Keep Out Zones (KOZ) around the TSV to maximize
reliability and performance� KOZ ensures that there is no wiring, TSVs or other transistordevices in this region
CTE (Cu) ~ 17ppm/CCTE (Tung) ~ 4.5ppm/C
CTE (Si) ~ 3ppm/C
Linear coefficient @ 20C
Keep Out Zones (KOZ) – Need for Mechanical ModelingKeep Out Zones (KOZ) – Need for Mechanical Modeling
Georgia Institute of Technology Feb 2012
Insertion Loss
NEXT between 1 and others FEXT between 1 and others
1
50µm
100µm
1V Excitation
Keep Out Zones (KOZ) and TSV Electrical ResponseKeep Out Zones (KOZ) and TSV Electrical Response
Spread in IL
Spread in Coupling
Change in
Current Dist.
Georgia Institute of Technology Feb 2012
Concluding Thoughts …..Concluding Thoughts …..
Mechanical Stresses
Joule Heating/Electro-migration
Thermal Management
Signal Integrity
Place & Route
Multi-physics andMulti-scaleEnvironment neededFor the DesignOf 3D Heterogeneous SystemsTier 1
Thickness ~ 50 µmAc tive Face Down
Tier 1Thickness ~ 5 0 µm
Active Face Down
BackSide MetalPitc h ~ 5-25 µm
BackSide MetalPitch ~ 5-2 5 µ m
Package SubstrateThickness ~ 180 µm
Package SubstrateThickness ~ 1 80 µ m
UnderfillGap ~ 80 µ m
UnderfillGap ~ 80 µm
Flip Chip BumpSize ~ <100 umPitch ~ 100-200 um
Flip Chip BumpSize ~ <100 umPitch ~ 100-200 um
TSVSize ~ 5-10 µmPitc h ~ 10-50 µm
TSVSize ~ 5-10 µm
Pitch ~ 10-50 µm
BGA BumpPitch ~ 0.65 mm
Height ~ 300 um
BGA BumpPitch ~ 0.6 5 mmHeight ~ 300 um
µ-BumpPitc h ~ 25-50 µm
µ-BumpPitch ~ 25-50 µm
UnderfillGap ~ 20 µ m
UnderfillGap ~ 20 µm
Tier 2Thickness ~ 260 µm
Ac tive Face Down
Tier 2Thickness ~ 2 60 µ mActive Face Down
Multi-scale
Need for the modelingof the interaction betweenmultiple domains will only
increase for 3D!Time for the IEEE Community to Innovate!