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Kobayashi Lab. Gunma University Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei .Sun, Dan.Yao, R.Takahashi, Y.Ozawa, N.Tsukiji, H.Kobayashi, R.Shiota Gunma University, Socionext Inc., Nov. 9 NA-L2 8:30-9:50
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Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

Aug 31, 2019

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Page 1: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

Kobayashi Lab. Gunma

University

Gray-Code Input DAC Architecture for

Clean Signal Generation

Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao,

R.Takahashi, Y.Ozawa, N.Tsukiji, H.Kobayashi, R.Shiota

Gunma University, Socionext Inc.,

Nov. 9 NA-L2 8:30-9:50

Page 2: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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OUTLINE

Research Background ・ ObjectiveGlitchesGray-codeGray-code Input DAC Architecture and OperationSimulation Verification by SPICEConclusion

Page 3: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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OUTLINE

Research Background ・ ObjectiveWhat are GlitchesGray-codeGray-code Input DAC Architecture and OperationSimulation Verification by SPICEConclusion

Page 4: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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Research Background

Analog Input Analog Input

DigitalSignal

Processing

Page 5: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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Research Background

Basic architecture of DAC

Current Source DAC Capacitive DAC Resistance DAC

The switch is driven with a binary code glitch

Page 6: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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Research Objective

Objective

Design Digital-to-Analog Converter (DAC) architectures for clean signal generation

Approach

By reducing glitches with Gray-Code input topologies

Page 7: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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OUTLINE

Research Background ・ ObjectiveGlitchesGray-codeGray-code Input DAC Architecture and OperationSimulation Verification by SPICEConclusion

Page 8: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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What are Glitches

Voltage spikes

Reasons for glitchesDecimal numbers Natural Binary code

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 1 0 1 0

11 1 0 1 1

12 1 1 0 0

13 1 1 0 1

14 1 1 1 0

15 1 1 1 1

when7→8

0111→0110→0100→0000→1000

when8→7

1000→1001→1011→1111→0111

The most significant bit (MSB) changes (near the middle point)

Page 9: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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Generation of Glitch at Switching time

Input

When the input changes 7 →8

Page 10: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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Generation of Glitch at Switching time

When B3 switches first

A big upward spike arises

Page 11: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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Generation of Glitch at Switching time

When B3 switches last

A big downward spike occur

Page 12: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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Generation of Glitch at Switching time

Input

glitch

glitch

Page 13: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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Glitch Problem and Remedy

Effects of Glitch

Serious deterioration of images, videos, sounds

Remedy

Using high-order reconstruction filterUsing track/hold circuitry at the DAC output

Using Gray-Code input DAC topologies

Extra Space in IC, Expensive

Page 14: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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OUTLINE

Research Background ・ ObjectiveWhat are GlitchesGray-codeGray-code Input DAC Architecture and OperationSimulation Verification by SPICEConclusion

Page 15: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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Gray-Code

Binary to Gray code converterBinary to Gray code conversion diagram

Two adjacent number Only one bit change

Gray-Code Alternative representation of binary code

(Gn=Bn+1⊕Bn)

Page 16: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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Gray Code

Compare with Binary code and Gray code

Binary code Multiple bits change at a time

Trigger more switches

Example. 1 2 --- 0001 0010 2 bits change

7 8--- 0111 1000 all 4 bits change

Gray code Only one bit changes at a time

Triggers one switch

Example. 1 2 --- 0001 0011 one bit change 7 8 --- 01001100 one bit change

Less glitches

Page 17: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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OUTLINE

Research Background ・ ObjectiveWhat are GlitchesGray-codeGray-code Input DAC Architecture and OperationSimulation Verification by SPICEConclusion

Page 18: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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Gray-code Input DAC Architecture and Operation

1.Current-steering Gray-Code DAC

2.Charge-mode Gray-Code DAC

3.Voltage-mode Gray-Code DAC

Page 19: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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Current/Voltage Switch Matrix

Parallel connection Cross connection

When S=0 When S=1

When S=0 When S=1

Switch is DPDT (Double-Pole Double-Throw)

Page 20: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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1.Current-steering Gray-Code DAC

Conventional Binary-Weighted current-steering DAC

Gray-Code input current-steering DAC

Page 21: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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Code Conversion

Binary code Gray code Current switch matrix for Gray code

Binary code domain Gray code domain

Code domain in Gray-code input current-steering DAC

Page 22: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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A Gray-code input current-steering DAC (data=5)

𝐼𝑜𝑢𝑡+ = 𝐼 − 2𝐼 + 4𝐼 − 8𝐼 = −5𝐼

𝐼𝑜𝑢𝑡− = −𝐼 + 2𝐼 − 4𝐼 + 8𝐼 = 5𝐼𝐼𝑜𝑢𝑡 = (𝐼𝑜𝑢𝑡+) − 𝐼𝑜𝑢𝑡− = −10𝐼

Page 23: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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2.Charge-mode Gray-code DAC

A binary-weighted capacitor DAC A Gray-code input charge-mode DAC

Page 24: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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Sample Mode of a Gray-Code Input Charge-Mode DAC (data=5)

Page 25: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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Sample Mode of a Gray-Code Input Charge-Mode DAC (data=5)

Page 26: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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3.Voltage-mode Gray-Code DAC

Page 27: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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A Gray-Code Input Voltage-mode DAC (data=5)

𝑉𝑜𝑢𝑡+ = 𝑉𝑟 + 4𝑉𝑟 = 5𝑉𝑟

Page 28: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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OUTLINE

Research Background ・ ObjectiveWhat are GlitchesGray-codeGray-code Input DAC Architecture and OperationSimulation Verification by SPICEConclusion

Page 29: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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Simulation Verification by SPICE

1.Simulation of current-steering Gray-Code DAC

2.Simulation of charge-mode Gray-Code DAC

3.Simulation of voltage-mode Gray-Code DAC

4.Verification of glitch reduction

Page 30: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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1.SPICE Realization of Current-Steering of Gray-Code Input

SubtractorCircuit

Latch

Gray-Code

Binary-Code

Page 31: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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1.Simulation of current-steering Gray-Code DAC

4bit Current-steering DAC 8bit Current-steering DAC

Page 32: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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2.SPICE Realization of charge-mode of Gray-Code Input

Non-overlapclock Latch

Gray-Code

Binary-Code

Page 33: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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2. Simulation of charge-mode Gray-Code DAC

4bit Charge-mode DAC 8bit Charge-mode DAC

Page 34: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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3.SPICE Realization of Voltage-mode of Gray-Code Input

AdderCircuit

AdderCircuit

AdderCircuit

Latch

Gray-Code

Binary-Code

Page 35: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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3. Simulation of Voltage-mode Gray-Code DAC

4bit Voltage-mode DAC 8bit Voltage-mode DAC

Page 36: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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4.Verification of glitch reduction

Binary code generating circuit

Conventional Current-Steering DAC with switching delay (8bit)

Page 37: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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4.Verification of glitch reduction

SubtractorCircuit

Binary code generating circuit

Current-Steering Gray-code input DAC with switching delay (8bit)

Page 38: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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4.Simulation Result (Up Sweeping)

Conventional Current-Steering DAC

Current-steering DAC of Gray-code

glitch

Conventional Current-Steering DAC VS. Current-steering DAC of Gray-code

Page 39: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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4.Simulation Result (Down Sweeping)

Conventional Current-Steering DAC

Conventional Current-Steering DAC VS. Current-steering DAC of Gray-code

Current-steering DAC of Gray-code

glitch

Page 40: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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4.Simulation Result (Random Switching Delay)

Conventional Current-Steering DAC VS. Current-steering DAC of Gray-code

Page 41: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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OUTLINE

Research Background ・ ObjectiveWhat are GlitchesGray-codeGray-code Input DAC Architecture and OperationSimulation Verification by SPICEConclusion

Page 42: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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Conclusion

Binary codeDAC Converter using Glitch

Gray code

input

DAC Converter using Gray code input

Current-steering Gray-Code DACCharge-mode Gray-Code DACVoltage-mode Gray-Code DAC

Glitch reduction

deterioration

Page 43: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

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Final statement

• Coding method can lead to robust mixed-signal circuit design.

Gray code was invented by Frank Gray at Bell Lab in 1947.

Page 44: Gray-Code Input DAC Architecture for Clean Signal Generation · Gray-Code Input DAC Architecture for Clean Signal Generation Richen.Jiang, G.Adhikari, Yifei.Sun, Dan.Yao, R.Takahashi,

Thank you for listening

谢谢

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