CSIR-NAL MTech Project Review 1 CSIR-NAL By SG Ramanathan MTech Thesis Project Final Submission External Review
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BySG Ramanathan MTech Thesis Project Final Submission External Review
CSIR-NAL
CSIR-NALMTech Project Review#
9/04/2015
Title of Project Thesis Design and Development of Graphics Processing Unit (GPU) Framework on FPGATarget FPGA - Spartan-6 XC6SLX45T-3FGG484Internal GuideMr. JAYAKUMAR EPAsst. ProfessorDepartment of ECENIT, CalicutExternal GuideDr. ANANDA CMSr. Principal ScientistHead, Aerospace Electronics Systems DivisionCSIR-NAL, Bangalore
CSIR-NALMTech Project Review# AgendaScope & Objective of the ProjectSystem OverviewTriple Video BuffersDDR3 Memory Controller IntegrationHost Application DevelopmentResults & ConclusionSummaryRendering AlgorithmVideo DemonstrationDesign Blocks Interface
CSIR-NALMTech Project Review# Scope & Objective Of ProjectDevelop GPU Frame Work FunctionalitiesFPGA VHDLTriple Video Buffer Mechanism Display Graphics Controller DesignDevelop Rendering AlgorithmHost Application C ProgramCommand Generation
LCD DisplayDesign OutputSocket ProgrammingUDP Packet Decoder
CSIR-NALMTech Project Review#
UDP DecoderPixel Color/Command HandlerDDR3 MemoryTriple Buffer HandlerDisplay Controller
Typical GPU InterfacesTop-Level FPGA BlocksHost MachineDisplay System
Frame Rendering: Converting Numeric Coordinates into bitmapsGraphics Controller: Converting Bitmaps into signals for screen with control signals based on the chosen resolution
Buffer Management: Frame Buffering using Triple Display Buffers
CSIR-NALMTech Project Review# System OverviewTEMAC CoreFIFO[FWFT]
UDP Decoder
ARP Packet Transmitter
Colour Data/ CommandHandler [MIG Wrapper]
MIG Core
Flush Buffer Logic
FIFO[FWFT]
Display Buffer Logic
FIFO[STD]XGA Display Controller
DDR3 Memory
Rasterization Programming in Host MachineTEMAC InterfaceCommand MemoryInterfaceMIG Interface & Triple Buffer ImplementationDisplay ControllerReview#1Review#2Review#3
Xilinxs TEMAC - Tri-Mode Ethernet Media Access Controller
CSIR-NALMTech Project Review# Display Controller Design & its Simulation Results
CSIR-NALMTech Project Review# XGA_GeneratorClk_65RGB
HSyncVSync
DDR3 Memory
RGB with control signals generated for fixed pattern/colorDisplay pixels has been feed from DDR3 memory
Graphics Controller: Converting Bitmaps into signals for screen with control signals for chosen resolutionPixel Mapping: Each Pixel of the screen mapped to a DDR3 memory locationActive Data
CSIR-NALMTech Project Review# Simulation Result#1: Display Controller Design
RGB Data in Active Region
CSIR-NALMTech Project Review# DDR3 Memory Controller Integration & its Simulation Results
CSIR-NALMTech Project Review# DDR3 Memory Read & Write BlocksInput WrapperOutput Wrapper
Spartan6 FPGA MIG WrapperMemory Controller CORECmd_FIFODATAFIFO
DDR3 Memory
Memory Interface is a free software tool used to generate memory controllers and interfaces forXilinxFPGAs
Top Design
Read & Write LogicsXilinxs Memory Interface Controller
Physical Component in BoardCommand FIFO holds Starting Address & Length of DataData FIFO holds Pixel color (RGB)
CSIR-NALMTech Project Review# FSM for DDR3 Memory AccessSTARTInitialize all Counters/RegisterMemory Calibration StatusSend Command to Controller for Writing to DDR3Controllers Data FIFO EmptyWrite into Data FIFOIncrement Address to Next LocationWrite Finish StatusSTOPCompletedNot CompletedEmptyNot EmptyFinishedNot FinishedSTARTInitialize all Counters/RegisterMemory Calibration StatusSend Command to Controller for Reading DDR3Controllers Data FIFO FullRead Data FIFO ContentIncrement Address to Next LocationRead Finish StatusSTOPCompletedNot CompletedFULLNot FULLFinishedNot FinishedWRITEREAD
CSIR-NALMTech Project Review#
Simulation Result#2: DDR3 Memory Write Sequence
64 colorsCommand64 colorsCommand64 colorsCommand
CSIR-NALMTech Project Review# Simulation Result#3: DDR3 Memory Read Sequence
Command
64 colors
Command
64 colors
CSIR-NALMTech Project Review# Triple Video Display Frame Buffer Design
CSIR-NALMTech Project Review# DDR3 Memory
GPU Engine
1 Operational BufferWhat is Triple Display Frame Buffer?
Frame BufferDisplay
3 Display Buffers
Operational Buffer: Dedicated Buffer for drawing the frame contentDisplay Buffers: Buffer the frame for display
CSIR-NALMTech Project Review# Triple Display Buffer Design How It Works?
Operational Buffer Memory RegionDisplay Buffer1Display Buffer2Display Buffer3
Port 2Colour Data/ Command Handler
Port 5Tri-Buffer Display Wrapper
Port 3Port 4Flush Logic WrapperOn Vsync_TriggerOn Flush TriggerXGA VideoGenerator
Operational Buffer: Dedicated Buffer for drawing the frame contentDisplay Buffers: Buffer the frame for display
CSIR-NALMTech Project Review# Generally, GPU generates 24 FPS, its very hard to witness the function of triple buffer operation.9/04/2015
Top DesignPORT_2
PORT_3
PORT_4
PORT_5
RGB
Input WrapperTri_Buffer_DisplayOutput FIFOFlush LogicClock Infrastructure
Spartan 6FPGA WrapperMemory Controller CORECmd_FIFODATAFIFO
Clk_200
All Clock Signals for Memory Controller DesignClock Gen IPClk_125Clk_65Clk_333.33DDR3 MemoryClk_333.33
XGA_Generator
FLUSH
Latest Buffers Base AddressVsync_Pulse
Integrated Design with Triple Buffer - FPGA
CSIR-NALMTech Project Review# Once Vertical Sync. Triggered from controller, display buffers gets read by tri_buffer_display logic. Triple Buffering to prevent FPS drops related to enabling Vsync; help to both remove tearing while also preventing the significant FPS drop encountered when VSync is enabled9/04/2015
Host Machine Interface & Application Development
CSIR-NALMTech Project Review# Host Software Application Design FunctionsUser Inputs/Commands Rendering AlgorithmSlice PacketsChop-OffSocket ProgramCoordinates, ColourDot, Line, Arc Primitives64 Word CountIgnore Over shoot pixelsEthernet Protocol
UDP DecoderPixel Color/Command HandlerDDR3 Memory
CSIR-NALMTech Project Review# Host FPGA Ethernet InterfaceHost Machine
UDP Packet
ARP PacketFPGAHost Machine & FPGA are bonded with IP & MAC IDs
Ethernet Data Payload Structure
CSIR-NALMTech Project Review# Drawing Pixel Dots
On Screen
CSIR-NALMTech Project Review# Line is a Stair-Case
CSIR-NALMTech Project Review# Bresenhams Line Algorithm
23452435(xk, yk)(xk+1, yk)(xk+1, yk+1)
yykyk+1xk+1
dlowerdupper
Algorithm finds pixel closer to original line0
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