GPRS Based Home Security System

8/13/2019 GPRS Based Home Security System

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A LOW COST GSM/GPRS BASED WIRELESS

HOME SECURITY SYSTEM


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(ABSTRACT)

AIM:

The main aim of the project is to designA LOW COST GSM/GPRS BASED

WIRELESS HOME SECURITY SYSTEM.

COMPONENTS:

S3C2440 Micro Controller, LCD, GPS Modem, Mo!ile, smo"e sensor,

temperat#re sensor$

ABSTRACT:

Sec#rit% is a prime concern in o#r da%&toda% life$ '(er%one )ants to !e as

m#ch sec#re as possi!le$ *n access control for doors forms a (ital lin" in a sec#rit%

chain$

The microcontroller !ased )ireless digital loc" for is an access control

s%stem that allo)s onl% a#thori+ed persons to enter a partic#lar room$ t is a lo)

cost so that the concept is implemented !% #sing micro controller$

n this project )e are #sing *M !ased microcontroller for controlling the

e-#ipments in the home$ GSM modem is #sed to comm#nicate and respond to the

remote commands and those commands are sent to the processor$

The s%stem has a "e% pad !% )hich the pass)ord can !e entered thro#gh it$

.hen the entered pass)ord e-#als )ith the pass)ord stored in the memor% then

the GSM modem sends a message to the #ser$ Then the #ser sends an SMS to the

em!edded s%stem then the rela% )ill !e on the door )ill !e opened$ 'ntering

pass)ord sho#ld !e displa%ed on the li-#id cr%stal displa% and the GSM$ f the

sending pass)ord thro#gh the GSM is also correct, then the loc" )ill !e opened

other)ise the loc" )ill not !e opened$

This s%stem also contains m#ltiple sensors )hich are #sed as sec#rit%

p#rpose, alert signal is pro(ided to o)ner of home #sing GSM modem and !#++er

to alert s#rro#ndings$


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BLOCK DIAGRAM:

IMPLEMENTATION:

MICRO

CONTROLLER

REGULATED

POWER SUPPLY

TEMPERATURE

SENSOR LCD UNIT

GPRS MODULE

MOBILE

RELAY

SMOKE SENSOR


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OPERATING SYSTEM: Lin#/ Ported into controller$

TARGET DEVICE: S3C2440 1riendl% *M$

APPLICATION LANGUAGE: C 5C66

DRIVERS: 7S8 Dri(ers, Displa% Dri(ers$

APPLICATIONS:7sed for 9ome and office sec#rit% s%stem$ADVANTAGES: Lo) cost, eas% to implement, a#tomated operation, and Lo)Po)er cons#mption$

REFERENCE:

:$ The ;0


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S*MS7=G>s S3C2440* :?32&!it SC microprocessor$ S*MS7=Gs

S3C2440* is designed to pro(ide hand&held de(ices and general applications )ith

lo)&po)er, and high&performance microcontroller sol#tion in small die si+e$ To

red#ce total s%stem cost, the S3C2440* incl#des the follo)ing components$

The S3C2440* is de(eloped )ith *M@20T core, 0$:3#m CMAS standard cells

and a memor% complier$ ts lo) po)er, simple, elegant and f#ll% static design is

partic#larl% s#ita!le for cost& and po)er&sensiti(e applications$ t adopts a ne) !#s

architect#re "no)n as *d(anced Micro controller 8#s *rchitect#re *M8*$ The

S3C2440* offers o#tstanding feat#res )ith its CP7 core, a :?32&!it *M@20T

SC processor designed !% *d(anced SC Machines, Ltd$ The *M@20T

implements MM7, *M8* 87S, and 9ar(ard cache architect#re )ith separate

:?B8 instr#ction and :?B8 data caches, each )ith an ;&)ord line length$ 8%

pro(iding a complete set of common s%stem peripherals, the S3C2440* minimi+es

o(erall s%stem costs and eliminates the need to config#re additional components$

The integrated on&chip f#nctions that are descri!ed in this doc#ment incl#de

*ro#nd :$2 internal, :$;2$


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SD 9ost interface (ersion :$0 F MMC Protocol (ersion 2$:: compati!le

2&ch 7S8 9ost controller :&ch 7S8 De(ice controller (er :$:

4&ch P.M timers :&ch nternal timer .atch Dog Timer

;&ch :0&!it *DC and To#ch screen interface

TC )ith calendar f#nction

Camera interface Ma/$ 40@? / 40@? pi/els inp#t s#pport$ 204; / 204; pi/el

inp#t s#pport for scaling

:30 General P#rpose A ports 24&ch e/ternal interr#pt so#rce

Po)er control =ormal, Slo), dle and Sleep mode

An&chip cloc" generator )ith PLL


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F$%&'. SC!""#A B*+, D$-%'-


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FEATURES:

ARCHITECTURE:

ntegrated s%stem for hand&held de(ices and General em!edded applications$

:?32&8it SC architect#re and po)erf#l

nstr#ction set )ith *M@20T CP7 core$

'nhanced *M architect#re MM7 to s#pport

.inC', 'PAC 32 and Lin#/$

nstr#ction cache, data cache, )rite !#ffer and Ph%sical address T*G *M

to red#ce the effect of main memor% !and)idth and latenc% on Performance$

*M@20T CP7 core s#pports the *M de!#g *rchitect#re$

nternal *d(anced Microcontroller 8#s *rchitect#re *M8* *M8*2$0,

*98*P8$

SYSTEM MANAGER

Little8ig 'ndean s#pport$

S#pport 1ast !#s mode and *s%nchrono#s !#s mode$

*ddress space :2;M !%tes for each !an" total :G !%tes$

S#pports programma!le ;:?32&!it data !#s )idth for each !an"$

1i/ed !an" start address from !an" 0 to !an" ?$

Programma!le !an" start address and !an" si+e for !an" E$ 'ight memor% !an"s Si/ memor% !an"s for AM, S*M, and others$

T)o memor% !an"s for AMS*MS%nchrono#s D*M$

Complete Programma!le access c%cles for all memor% !an"s$


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S#pports e/ternal )ait signals to e/pand the !#s c%cle$

S#pports self&refresh mode in SD*M for po)er do)n$

S#pports (ario#s t%pes of AM for !ooting =A=*=D 1lash, ''PAM,

and others$

NAND F-0 B**1 L*-2'

S#pports !ooting from =*=D flash memor%$

4B8 internal !#ffer for !ooting$

S#pports storage memor% for =*=D flash memor% after !ooting$

S#pports *d(anced =*=D flash

C-+0 M*'3

?4&)a% set&associati(e cache )ith &Cache :?B8 and D&Cache :?B8$

;)ords length per line )ith one (alid !it and t)o dirt% !its per line$

Pse#do random or ro#nd ro!in replacement algorithm$

.rite&thro#gh or )rite&!ac" cache operation to #pdate the main memor%$

The )rite !#ffer can hold :? )ords of data and fo#r addresses$CLOCK 4 POWER MANAGER

An&chip MPLL and 7PLL 7PLL generates the cloc" to operate 7S8

9ostDe(ice$ MPLL generates the cloc" to operate MC7 at ma/im#m

400M9+ :$3$

Cloc" can !e fed selecti(el% to each f#nction !loc" !% soft)are$

P*5' *2 =ormal, Slo), dle, and Sleep mode

o N*'- *2 =ormal operating mode

o S*5 *2 Lo) fre-#enc% cloc" )itho#t PLL

o I2 *2 The cloc" for onl% CP7 is stopped$


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o S6 *2 The Core po)er incl#ding all peripherals is sh#t do)n$

.o"en #p !% '=TH:


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4&ch DM* controller

S#pports memor% to memor%, A to memor%, memor% to A, and A to A

transfers

8#rst transfer mode to enhance the transfer rate

LCD CONTROLLER STN LCD DISPLAYS FEATURE

S#pports 3 t%pes of ST= LCD panels 4&!it d#al scan, 4&!it single scan, ;&!it

single scan displa% t%pe

S#pports monochrome mode, 4 gra% le(els, :? gra% le(els, 2


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o Ma/im#m (irt#al screen si+e in ?4B color

o mode 204;/:024, and others

UART

3&channel 7*T )ith DM*&!ased or interr#pt !ased operation

S#pports


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:2; 8%tes ?4&8%te 6 ?4&8%te 11A for T//

S#pports S format and MS8&j#stified data format

AC89 AUDIO7CODEC INTERFACE

S#pport :?&!it samples

:&ch stereo PCM inp#ts :&ch stereo PCM o#tp#ts :&ch MC inp#t

USB HOST

2&port 7S8 9ost

Complies )ith A9C e($ :$0

Compati!le )ith 7S8 Specification (ersion :$:

USB DEVICE

:&port 7S8 De(ice

< 'ndpoints for 7S8 De(ice

Compati!le )ith 7S8 Specification (ersion :$:

SD HOST INTERFACE

=ormal, nterr#pt and DM* data transfer mode !%te, half )ord, )ordtransfer

DM* !#rst4 access s#pport onl% )ord transfer

Compati!le )ith SD Memor% Card Protocol (ersion :$0

Compati!le )ith SDA Card Protocol (ersion :$0

?4 8%tes 11A for T//

Compati!le )ith M#ltimedia Card Protocol (ersion 2$::

SPI INTERFACE

Compati!le )ith 2&ch Serial Peripheral nterface Protocol (ersion 2$::

2/; !its Shift register for T//


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DM*&!ased or interr#pt&!ased operation

CAMERA INTERFACE

T7& 8T ?0:?


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ARM 4 ITS ARCHITECTURE:

ARM H$1*'3

The ARM A+*' RISC M-+0$ architect#re is de(eloped at

*corn Comp#ter Limited of Cam!ridge, 'ngland !et)een:@;3&:@;


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*M CP7s are fo#nd in most corners of cons#mer electronics, from porta!le

de(ices PD*s, mo!ile phones, iPods and other digital media and m#sic pla%ers,

handheld gaming #nits, and calc#lators to comp#ter peripherals hard dri(es,

des"top ro#ters$

*M does not man#fact#re the CP7 itself, !#t licenses it to other

man#fact#rers to integrate them into their o)n s%stem$

ARM -'+0$1+1&'

RISC:

SC, orReduced Instruction Set Computeris a t%pe of microprocessor

architect#re that #tili+es a small, highl%&optimi+ed set of instr#ctions, rather than a

more speciali+ed set of instr#ctions often fo#nd in other t%pes of architect#res$

H$1*'3:

The first SC projects came from 8M, Stanford, and 7C&8er"ele% in the late E0s

and earl% ;0s$ The 8M ;0:, Stanford MPS, and 8er"ele% SC : and 2 )ere all

designed )ith a similar philosoph% )hich has !ecome "no)n as SC$ Certain

design feat#res ha(e !een characteristic of most SC processors

One cycle execution time: SC processors ha(e a CP cloc" per

instr#ction of one c%cle$ This is d#e to the optimi+ation of each instr#ction

on the CP7 and a techni-#e called Q

Pipelining : a techni-#e that allo)s for sim#ltaneo#s e/ec#tion of parts, or


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stages, of instr#ctions to more efficientl% process instr#ctionsQ

Large number of registers :the SC design philosoph% generall%

incorporates a larger n#m!er of registers to pre(ent in large amo#nts of

interactions )ith memor%

CSC SC

PricePerformance Strategies

Price mo(e comple/it% from soft)are to

hard)are$

Performance ma"e tradeoffs in fa(or of

decreased code si+e, at the e/pense of a

higher CP$

Price mo(e comple/it% from hard)are to

soft)are

Performance ma"e tradeoffs in fa(or of a

lo)er CP, at the e/pense of increased code

si+e$

Design Decisions

'/ec#tion of instr#ctions ta"es man%

c%cles

Design r#les are simple th#s core

operates at higher cloc" fre-#encies

Memor%&to&memor% addressing

modes$

Simple, single&c%cle instr#ctions that

perform onl% !asic f#nctions$

*ssem!ler instr#ctions correspond to

microcode instr#ctions on a CSC

machine$

Design r#les are more comple/ and


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* microcode control #nit$

Spend fe)er transistors on registers$

operates at lo)er cloc" fre-#encies

Simple addressing modes that allo)

onl% LA*D and STA' to access

memor%$ *ll operations are register&

to&register$

Direct e/ec#tion control #nit$

Spend more transistors on m#ltiple

!an"s of registers$

7se pipelined e/ec#tion to lo)er CP$

8ased #pon SC *rchitect#re )ith enhancements to meet re-#irements of

em!edded applications *M is ha(ing

:$ * large #niform register file

2$ Load&store architect#re ,)here data processing operations operate on

register contents onl%

3$ 7niform and fi/ed length instr#ctions

4$ 32 &!it processor


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separat2 -2 & 603$+-3 6-'-1 1'-$$* 6-10 . E-= 10

-+0$ 1* 1'->' $1'&+1$* -2 2-1- $&1-*&3 0-+

6'>*'-+. H-'


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The fig#re sho)s the *M core dataflo) model$ n )hich the *M core as

f#nctional #nits connected !% data !#ses$ *nd the arro)s represent the flo) of

data, the lines represent the !#ses, and !o/es represent either an operation #nit or a

storage area$ The fig#re sho)s not onl% the flo) of data !#t also the a!stract

components that ma"e #p an *M core$

1ig *M core dataflo) model

n the a!o(e fig#re the D-1-enters the processor core thro#gh the Data !#s$

The data ma% !e an instr#ction to e/ec#te or a data item$ This *M core

represents the V* N&- implementation of the *M data items and


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contin#es e/ec#ting instr#ctions #ntil an e/ception or interr#pt changes the normal

e/ec#tion flo)$

ARM B& T+0**%3:

'm!edded s%stems #se different !#s technologies$ Most common PC !#s

technolog% is the Peripheral Component nterconnect PC !#s .hich connects

de(ices s#ch as (ideo card and dis" controllers to the ;? processor !#ses$ This

t%pe of technolog% is called '/ternal or off chip !#s technolog%$

'm!edded de(ices #se an on&chip !#s that is internal to the chip and allo)s

different peripheral de(ices to !e inter connected )ith an *M core$

There are t)o different t%pes of de(ices connected to the !#s

:$ 8#s Master

2$ 8#s Sla(e

:$ B& M-1': * logical de(ice capa!le of initiating a data transfer )ith

another de(ice across the same !#s *M processor core is a !#s Master$

2$ B& S-


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*M8* 8#s )as introd#ced in :@@? and has !een )idel% adopted as the An

Chip !#s architect#re #sed for *M processors$

The first *M8* !#ses )ere

:$ *M S%stem 8#s *S8

2$ *M Peripheral 8#s *P8

Later *M introd#ced another !#s design called the *M 9igh performance 8#s

*98

7sing *M8*

i$ Peripheral designers can re#se the same design on m#ltiple projects

ii$ * Peripheral can simpl% !e !olted on the An Chip !#s )itho#t ha(ing to

redesign an interface for different processor architect#re$

This pl#g&and&pla% interface for hard)are de(elopers impro(es a(aila!ilit% and

time to mar"et$

*98 pro(ides higher data thro#ghp#t than *S8 !eca#se it is !ased on centrali+ed

m#ltiple/ed !#s scheme rather than the *S8 !idirectional !#s design$ This change

allo)s the *98 !#s to r#n at )idths of ?4 !its and :2; !its

*M introd#ced t)o (ariations on the *98 !#s

:$ M#lti&la%er *98

2$ *98&Lite

n contrast to the original *98, )hich allo)s a single !#s master to !e

acti(e on the !#s at an% time, the M#lti&la%er *98 !#s allo)s m#ltiple acti(e !#s

masters$

*98& Lite is a s#!set of the *98 !#s and it is limited to a single !#s master$ This

!#s )as de(eloped for designs that do not re-#ire the f#ll feat#res of the standard

*98 !#s$

*98 and M#ltiple&la%er *98 s#pport the same protocol for master and

sla(e !#t ha(e different interconnects$ The ne) interconnects in M#lti&la%er *98


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are good for s%stems )ith m#ltiple processors$ The% permit operations to occ#r in

parallel and allo) for higher thro#ghp#t rates$

ARCHITECTURE R


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D UT*G de!#g

M fast m#ltiplier

'm!edded C' macro cell

' enhanced instr#ction ass#mes TDM

U Ua+elle

1 (ector floating&point #nit

S s%nthesi+a!le (ersion

*ll *M cores after the *METDM incl#de the TDM feat#res e(en

tho#gh the% ma% not incl#de those letters after the *M K la!el

The processor famil% is a gro#p of processor implementations that share the

same hard)are characteristics$ 1or e/ample, the *METDM, *ME40T,

and *ME20T all share the same famil% characteristics and !elong to the

*ME famil%

JTAG is descri!ed !% ''' ::4@$: standard Test *ccess Port and !o#ndar%

scan architect#re$ t is a serial protocol #sed !% *M to send and recei(e

de!#g information !et)een the processor core and test e-#ipment

Embedded ICE macro cellis the de!#g hard)are !#ilt into the processor that

allo)s !rea"points and )atch points to !e set

Synthesizablemeans that the processor core is s#pplied as so#rce code that

can !e compiled into a form easil% #sed !% 'D* tools

I1'*2&+1$* 1* ARM9TDMI +*'


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The *METDM core is a 32&!it em!edded SC processor deli(ered as a hard

macro cell optimi+ed to pro(ide the !est com!ination of performance, po)er and

area characteristics$ The *METDM core ena!les s%stem designers to !#ild

em!edded de(ices re-#iring small si+e, lo) po)er and high performance$

ARM9TDMI F-1&'

32:?&!it SC architect#re *M (4T

32&!it *M instr#ction set for ma/im#m performance and fle/i!ilit%

:?&!it Th#m! instr#ction set for increased code densit%

7nified !#s interface, 32&!it data !#s carries !oth instr#ctions and data Three&stage pipeline

32&!it *L7

er% small die si+e and lo) po)er cons#mption

1#ll% static operation

Coprocessor interface

'/tensi(e de!#g facilities 'm!edded C' de!#g #nit accessi!le (ia UT*G

interface #nit

B>$1

Generic la%o#t can !e ported to specific process technologies

7nified memor% !#s simplifies SoC integration process

*M and Th#m! instr#ctions sets can !e mi/ed )ith minimal o(erhead to

s#pport application re-#irements for speed and code densit%

Code )ritten for *METDM&S is !inar%&compati!le )ith other mem!ers

of the *ME 1amil% and for)ards compati!le )ith *M@, *M@' and

*M:0 families, th#s it>s -#ite eas% to port %o#r design to higher le(el


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microcontroller or microprocessor

Static design and lo)er po)er cons#mption are essential for !atter%

&po)ered de(ices

nstr#ction set can !e e/tended for specific re-#irements #sing coprocessors

'm!edded C'&T and optional 'TM #nits ena!le e/tensi(e, real&time

de!#g facilities

ARM9TDMI M$+'*+*1'*':

:$ *(aila!le *METDM Microcontrollers

2$ *nalog De(ices *D#C E///

3$ *tmel *T@:S*ME

4$ 1ree scale M*CE:00


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registers are (isi!le to the programmer depend #pon the c#rrent mode of the

processor$

C&''1 6'*%'- 1-1& '%$1':

The *M core #ses the cpsr to monitor and control internal operations$The cpsr is a dedicated 32&!it register and resides in the register file$ Thefollo)ing fig#re sho)s the generic program stat#s register$

1ig Program Stat#s egister1ig Program Stat#s egister

The control !it field contains the processor mode, state, and interr#pt mas" !its,1$ eser(ed !its are allocated for the f#t#re (ersions p#rpose$

The =, , C and are condition code flags )ill !e changed as a res#lt ofarithmetic and logical operations in the processor

= =egati(e$ ero$ C Carr%$ A(erflo)

The and 1 !its are the interr#pt disa!le !its

The M0, M:, M2, M3 and M4 !its are the mode !its


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P'*+*' M*2: Processor modes determine )hich register are acti(e, and

access rights to CPS register itself$ 'ach processor mode is either pri(ileged or

=on&pri(ileged$ *M has se(en modes$ These E modes are di(ided into t)o t%pes$

P'$


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Stat#s egister, or SPS$ This SPS is #sed to sa(e the state of CPS C#rrent

program stat#s egister )hen the pri(ileged mode is entered in order that the #ser

state can !e f#ll% restored )hen the #ser processor is res#med

M*2 C0-%$%:

Mode changes !% )riting directl% to CPS or !% hard)are )hen the processor

responds to e/ception or interr#pt$

To ret#rn to #ser mode a special ret#rn instr#ction is #sed that instr#cts the core to

restore the original CPS and !an"ed registers$

ARM I1'&+1$* S1

n this chapter )e are going to disc#ss a!o#t the most commonl% #sed

nstr#ction Set of *M$ Different *M architect#res re(isions s#pport different

instr#ctions$ 9o)e(er ne) re(isions #s#all% add instr#ctions and remain

!ac")ardl% compati!le$ The follo)ing sho)s the t%pe of instr#ctions that *M

s#pport$$ Data Processing nstr#ctions

$ 8ranch nstr#ctions

$Load&store nstr#ctions

$Soft)are nterr#pt nstr#ction

$ Program Stat#s egister nstr#ctions

I. D-1- P'*+$% I1'&+1$*:7

The data processing instr#ctions manip#late data )ithin registers$ Most data

processing instr#ctions can process one of their operands #sing the !arrel shifter$ f


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)e #se the S s#ffi/ on a data processing instr#ction, then it #pdates the flags in the

cpsr. Mo(e and logical operations #pdate the carr% flag C, negati(e flag =, and

ero flag $ The carr% flag is set from the res#lt of the !arrel shift as the last !it

shifted o#t$ The = flag is set to !it 3: of the res#lt$ The flag is set if the res#lt is

+ero$ The follo)ing instr#ctions are Data processing instr#ctions$

$). M*


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*DC add t)o 32&!it (al#es and carr%

S78 s#!tract t)o 32&!it (al#es

S8C s#!tract )ith carr% of t)o 32&!it (al#es

S8 re(erse s#!tract of t)o 32&!it (al#es

SC re(erse s#!tract )ith carr% of t)o 32&!it (al#es

$


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pair of registers$

M7L m#ltipl%

ML* m#ltipl% and acc#m#late

Long M#ltipl% nstr#ctions Prod#ce ?4 !it (al#es, res#lt )ill !e placed in t)o 32

!it (al#es

SML*L signed m#ltipl% acc#m#late long

SM7LL signed m#ltipl% acc#m#late

7ML*L #nsigned m#ltipl% acc#m#late long

7M7LL #nsigned m#ltipl% long

II. B'-+0 I1'&+1$*: 7 * !ranch instr#ction changes the flo) of e/ec#tion or

is #sed to call a ro#tine$ This t%pe of instr#ction allo)s programs to ha(e

s#!ro#tines, i%-then-else str#ct#res, and loops$ The change of e/ec#tion flo) forces

the program co#nterpc to point to ne) address$ The !elo) sho)n instr#ctions are

8ranch instr#ctions$

8 !ranch

8L !ranch )ith lin"

8 !ranch e/change

8L !ranch e/change )ith lin"

III. L*-271*' I1'&+1$*: 7 Load&store instr#ctions transfer data !et)een

memor% and processor registers$

There are three t%pes of load&store instr#ctions

i$ single register transferring

ii$ M#ltiple register transfer

iii$ S)ap


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S$% '%$1' 1'->''$%: 7These instr#ctions are #sed for mo(ing a single

data item in and o#t of a register$ The data t%pes s#pported are signed and #nsigned

)ords 32&!it, half&)ords :?&!it, and !%tes$ The follo)ing instr#ctions are

(ario#s load&store single&register transfer instr#ctions$

LD load )ord into a register

ST sa(e !%te or )ord from a register

LD8 load !%te into a register

ST8 sa(e !%te from a register

LD9 load half&)ord into a register

ST9 sa(e half&)ord into a register

LDS8 load signed !%te into a register

LDS9 load signed half&)ord into a register

M&1$6 '%$1' 1'->': 7 Load&store m#ltiple instr#ctions can transfer

m#ltiple registers !et)een memor% and the processor in a single instr#ction$ The

transfer occ#rs from a !ase address register Rnpointing into memor%$ M#ltiple&

register transfer instr#ctions are more efficient from single&register transfers for

mo(ing !loc"s of data aro#nd memor% and sa(ing and restoring conte/t and stac"s$

f an interr#pt has !een raised, then it has no effect #ntil the load&store m#ltiple

instr#ction is complete$

LDM load m#ltiple registers

STM sa(e m#ltiple registers

S5-6: 7 The s)ap instr#ction is a special case of a load&store instr#ction$ t s)aps

the contents of memor% )ith the contents of a register$ This instr#ction is an

atomic operation& it reads and )rites a location in the same !#s operation,


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pre(enting an% other instr#ction from reading or )riting to that location #ntil it

completes$

IV. S*>15-' I1''&61 I1'&+1$*: 7 * soft)are interr#pt instr#ction S&I#

ca#ses a soft)are interr#pt e/ception, )hich pro(ides a mechanism for

applications to call operating s%stem ro#tines$ The follo)ing instr#ction comes

#nder soft)are interr#pt instr#ction$

S. soft)are interr#pt

V. P'*%'- S1-1& R%$1' I1'&+1$*: 7 The *M instr#ction set pro(idest)o instr#ctions to directl% control a program stat#s psr#$

MS This instr#ction transfers the contents of either the cpsr or spsr into a

register

MS This instr#ction transfers the content of a register into the cpsrorspsr

Together the a!o(e t)o instr#ctions are #sed to read and )rite the cpsrorspsr

ARM8 -'+0$1(+1&'(

ARM8is an *M architect#re 32&!it SC CP7famil%$ .ith this design

generation, *M mo(ed from a (on =e#mann architect#re Princeton

architect#re to a 9ar(ard architect#re)ith separate instr#ction and data !#sses

and caches, significantl% increasing its potential speed$ Most silicon chips

integrating these cores )ill pac"age them as modified 9ar(ard architect#re chips,

com!ining the t)o address !#sses on the other side of separated CP7 cachesand

tightl% co#pled memories$
http://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/Von_Neumann_architecturehttp://en.wikipedia.org/wiki/Harvard_architecturehttp://en.wikipedia.org/wiki/CPU_cacheshttp://en.wikipedia.org/wiki/Von_Neumann_architecturehttp://en.wikipedia.org/wiki/Harvard_architecturehttp://en.wikipedia.org/wiki/CPU_cacheshttp://en.wikipedia.org/wiki/Central_processing_unit


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There are t)o s#!families, implementing different *M architect#re (ersions$

C*11

: Differences from *ME cores

2 *M@TDM !ased cores

3 *M@' !ased cores

D$>>'+ >'* ARM9 +*'

Be% impro(ements o(er *ME cores, ena!led !% spending more transistors,

incl#de

Decreased heat prod#ction and lo)er o(erheating ris"$

Cloc" fre-#enc% impro(ements$ Shifting from a three stage pipeline to a fi(e

stage one lets the cloc" speed !e appro/imatel% do#!led, on the same silicon

fa!rication process$

C%cle co#nt impro(ements$ Man% #nmodified *ME !inaries )ere

meas#red as ta"ing a!o#t 30 fe)er c%cles to e/ec#te on *M@ cores$ Be%

impro(ements incl#de

o 1aster loads and storesQ man% instr#ctions no) cost j#st one c%cle$

This is helped !% !oth the modified 9ar(ard architect#re red#cing

!#s and cache contention and the ne) pipeline stages$

o '/posing pipeline interloc"s, ena!ling compiler optimi+ations to

red#ce !loc"age !et)een stages$

*dditionall%, some *M@ cores incorporate Y'nhanced DSPY instr#ctions, s#ch as

a m#ltipl%&acc#m#late, to s#pport more efficient implementations of digital signalprocessing algorithms$

S)itching to 9ar(ard architect#re entailed a nonnified cache, so that instr#ction

fetches do not e(ict data and (ice (ersa$ *M@ cores ha(e separate data and

address !#s signals, )hich chip designers #se in (ario#s )a%s$ n most cases the%
http://en.wikipedia.org/wiki/ARM9#Differences_from_ARM7_coreshttp://en.wikipedia.org/wiki/ARM9#ARM9TDMI_based_coreshttp://en.wikipedia.org/wiki/ARM9#ARM9E_based_coreshttp://en.wikipedia.org/wiki/ARM9#Differences_from_ARM7_coreshttp://en.wikipedia.org/wiki/ARM9#ARM9TDMI_based_coreshttp://en.wikipedia.org/wiki/ARM9#ARM9E_based_cores


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connect at least part of the address space in (on =e#mann st%le, #sed for !oth

instr#ctions and data, #s#all% to an *98 interconnect connecting to a D*M

interface and an '/ternal 8#s nterface #sa!le )ith =A flash memor%$ S#ch

h%!rids are no longer p#re 9ar(ard architect#re processors$

ARM8TDMI =-2 +*'

*M@TDM is a s#ccessor to the pop#lar *METDM core, and is also !ased on

the *M(4T architect#re$ Cores !ased on it s#pport !oth 32&!it *M and :?&!it

Th#m! instr#ction sets incl#de

*M@20T )ith :?B8 each of D cache and an MM7

*M@22T )ith ;B8 each of D cache and an MM7

*M@40T )ith cache and a Memor% Protection 7nit MP7

A=*&1 10 ARM8!#T:

The *M@20T processor is a mem!er of the *M@TDM famil% of general&

p#rpose microprocessors, )hich incl#des

*M@TDM core

*M@40T core pl#s cache and protection #nit

*M@20T core pl#s cache and MM7$

The *M@TDM processor core is a 9ar(ard architect#re de(ice implemented

#sing a fi(e&stage pipeline consisting of 1etch, Decode, '/ec#te, Memor%, and

.rite stages$ t can !e pro(ided as a standalone core that can !e em!edded into

more comple/ de(ices$ The standalone core has a simple !#s interface that allo)s

%o# to design %o#r o)n caches and memor% s%stems aro#nd it$

The *M@TDM famil% of microprocessors s#pports !oth the 32&!it *M and

:?&!it Th#m! instr#ction sets, allo)ing %o# to trade off !et)een high performance

and high code densit%$
http://en.wikipedia.org/wiki/Memory_management_unithttp://en.wikipedia.org/wiki/Memory_management_unit


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The *M@20T processor is a 9ar(ard cache architect#re processor that is targeted

at m#ltiprogrammer applications )here f#ll memor% management, high

performance, and lo) po)er are all&important$ The separate instr#ction and data

caches in this design are :?B8 each in si+e, )ith an ;&)ord line length$ The

*M@20T processor implements an enhanced *M architect#re (4 MM7 to

pro(ide translation and access permission chec"s for instr#ction and data

addresses$

The *M@20T processor s#pports the *M de!#g architect#re and incl#des logic

to assist in !oth hard)are and soft)are de!#g$ The *M@20T processor also

incl#des s#pport for coprocessors, e/porting the instr#ction and data !#ses along

)ith simple handsha"ing signals$

The *M@20T interface to the rest of the s%stem is o(er #nified address and data

!#ses$ This interface ena!les implementation of either an Ad'anced

(icrocontroller )us Architecture *M8* Ad'anced System )us *S8 or

Ad'anced *i+h-per%ormance )us*98 !#s scheme either as a f#ll%&compliant

*M8* !#s master, or as a sla(e for prod#ction test$ The *M@20T processor also

has a Trac,in+ ICEmode )hich allo)s an approach similar to a con(entional C'

mode of operation$

The *M@20T processor s#pports the addition of anEmbedded Trace (acrocell

'TM for real&time tracing of instr#ctions and data$

T0 ARM8!#T:

The *M@20T is a high&performance 32&!it SC processor Macro cell

com!ining an *M@TDMZ processor core )ith

:$ :?B8 instr#ction and :?B8 data caches

2$ instr#ction and data(emory (ana+ement nits MM7s

3$ )rite !#ffer


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4$ anA()AZ *d(anced Microprocessor 8#s *rchitect#re !#s interface

*'-+

The *M@20T pro(ides a high&performance processor sol#tion for open s%stems

re-#iring f#ll (irt#al memor% management and sophisticated memor% protection$

*n enhanced *M[ architect#re (4 MM7 implementation pro(ides translation

and access permission chec"s for instr#ction and data addresses$ The *M@20T

high&performance processor sol#tion gi(es considera!le sa(ings in chip comple/it%

and area, chip s%stem design, and po)er cons#mption$

C*6-1$= 5$10 ARM9 -2 S1'*%7-'

The *M@20T processor is :00 #ser code !inar% compati!le )ith *METDM,

and !ac")ards compati!le )ith the *ME Th#m![ 1amil% and the Strong *M

processor families, gi(ing designers soft)are&compati!le processors )ith a range

of priceperformance points from ?0 MPS to 2006MPS$ S#pport for the *M

architect#re toda% incl#des

:$ .indo)s C', S%m!ian AS, Lin#/, and J= operating s%stems

2$ 406 eal Time Aperating S%stems

3$ co&sim#lation tools from leading 'D* (endors

4$ ariet% of soft)are de(elopment tools$

A66$+-1$*:

:$ *pplications r#nning an Apen AS

- S%m!ian AS


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- Lin#/, Palm AS

- .inC'

2$ 9igh performance )ireless applications

-Smart phones

- PD*s

3$ =et)or"ing applications

4$ Digital set top !o/es

$1:

:$ Designed specificall% for S%stem&on&Chip integration

2$ S#pports the Th#m! instr#ction set offering the same e/cellent code densit%

as the *METDM

3$ 9igh performance allo)s s%stem designers to integrate more f#nctionalit%

into price and po)er&sensiti(e applications demanding more performance

4$ Cached processor )ith an eas% to #se lo)er fre-#enc% on&chip s%stem !#s

interface$

ARM8!#T B*+, 2$-%'-:


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ARM8!#T M-+'* +:

The *M@20T macro cell is !ased on the *M@TDM 9ar(ard architect#re

processor core, )ith an efficient


44/108


45/108

The ph%sical address of all the lines held in the data cache is stored !% the

P*T*G memor%, remo(ing the need for address translation )hen e(icting a line

from the cache$

MMU

The standard *M@20T implements an enhanced *M(4 MM7 to pro(ide

translation and access$ Permission chec"s for the instr#ction and data address ports

of the *M@TDM$

T0 MMU >-1&' -':

:$ standard *M(4 MM7 mapping si+es, domains, and access protection

scheme

2$ mapping si+es are :M8 sections,?4B8 large pages, 4B8 small pages, and

ne) :B8 tin% pages

3$ access permissions for sections

4$ access permissions for large pages and small pages can !e specified

separatel% for each -#arter of the page these -#arters are called s#!pages


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The s%stem controller ar!itrates !et)een instr#ction and data access to sched#le

single or sim#ltaneo#s re-#ests to the MM7s and the 8#s nterface 7nit$ The

s%stem controller recei(es ac"no)ledgement from each reso#rce to allo)

e/ec#tion to contin#e$

C*1'* +*6'*+*' (CPJ)

The CP:< allo)s config#ration of the caches, the )rite !#ffer, and other

*M@20T options$ Se(eral registers )ithin CP:< are a(aila!le for program

control, pro(iding access to feat#res s#ch as

:$ in(alidate )hole TL8 #sing CP:s processing time incl#ding in )hat order, 2 a s#per(isor,

)hich grants #se of the comp#ter to each process )hen it is sched#led, 3 an

interr#pt handler, )hich handles all re-#ests from the (ario#s hard)are de(ices

s#ch as dis" dri(es and the "e%!oard that compete for the "ernel>s ser(ices and

4 a memor% manager, )hich allocates the s%stem>s address spacesi$e$, locations

in memor% among all #sers of the "ernel>s ser(ices$

The "ernel sho#ld not !e conf#sed )ith the)IS8asic np#to#tp#t S%stem$ The

8AS is an independent program stored in a chip on the motherboardthe main

circ#it !oard of a comp#ter that is #sed d#ring the !ooting process for s#ch tas"s

as initiali+ing the hard)are and loading the "ernel into memor%$ .hereas the 8AS

al)a%s remains in the comp#ter and is specific to its partic#lar hard)are, the

"ernel can !e easil% replaced or #pgraded !% changing or #pgrading the operating

s%stem or, in the case of Lin#/, !% adding a ne)er "ernel or modif%ing an e/isting

"ernel$

Most "ernels ha(e !een de(eloped for a specific operating s%stem, and there is

#s#all% onl% one (ersion a(aila!le for each operating s%stem$ 1or e/ample, the

Microsoft .indo)s 2000 "ernel is the onl% "ernel for Microsoft .indo)s 2000

and the Microsoft .indo)s @; "ernel is the onl% "ernel for Microsoft .indo)s

@;$ Lin#/ is far more fle/i!le in that there are n#mero#s (ersions of the Lin#/

"ernel, and each of these can !e modified in inn#mera!le )a%s !% an informed

#ser$

* fe) "ernels ha(e !een designed )ith the goal of !eing s#ita!le for #se )ith an%

operating s%stem$ The !est "no)n of these is the Mach "ernel, )hich )as

de(eloped at Carnegie&Mellon 7ni(ersit% and is #sed in the Macintosh AS

operating s%stem$
http://www.linfo.org/linuxdef.htmlhttp://www.linfo.org/linuxdef.html


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t is not necessar% for a comp#ter to ha(e a "ernel in order for it to !e #sa!le, the

reason !eing that it is not necessar% for it to ha(e an operating s%stem$ That is, it is

possi!le to load and r#n programs directl% on bare metal machinesi$e$, comp#ters

)itho#t an% operating s%stem installed, altho#gh this is #s#all% not (er% practical$

n fact, the first generations of comp#ters #sed !are metal operation$ 9o)e(er, it

)as e(ent#all% reali+ed that con(enience and efficienc% co#ld !e increased !%

retaining small #tilit% programs, s#ch as program loaders and de!#ggers, in

memor% !et)een applications$ These programs grad#all% e(ol(ed into operating

s%stem "ernels$

The term ,ernelis fre-#entl% #sed in !oo"s and disc#ssions a!o#t Lin#/, )hereas

it is #sed less often )hen disc#ssing some other operating s%stems, s#ch as the

Microsoft .indo)s s%stems$ The reasons are that the "ernel is highl% config#ra!le

in the case of Lin#/ and #sers are enco#raged to learn a!o#t and modif% it and to

do)nload and install #pdated (ersions$ .ith the Microsoft .indo)s operating

s%stems, in contrast, there is relati(el% little point in disc#ssing "ernels !eca#se

the% cannot !e modified or replaced$

C-1%*'$ *> K'

Bernels can !e classified into fo#r !road categories monolithic ,ernels,

micro,ernels, hybrid ,ernels and e/o,ernels$ 'ach has its o)n ad(ocates and

detractors$

Monolithic "ernels, )hich ha(e traditionall% !een #sed !% 7ni/&li"e operating

s%stems, contain all the operating s%stem core f#nctions and the de'ice dri'ers

small programs that allo) the operating s%stem to interact )ith hard)are de(ices,

s#ch as dis" dri(es, (ideo cards and printers$ Modern monolithic "ernels, s#ch as

those of Lin#/ and 1ree8SD, !oth of )hich fall into the categor% of 7ni/&li"e

operating s%stems, feat#re the a!ilit% to load modulesat r#ntime, there!% allo)ing


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eas% e/tension of the "ernel>s capa!ilities as re-#ired, )hile helping to minimi+e

the amo#nt of code r#nning in "ernel space$

* micro"ernel #s#all% pro(ides onl% minimal ser(ices, s#ch as defining memor%

address spaces, interprocess comm#nication PC and process management$ *ll

other f#nctions, s#ch as hard)are management, are implemented as processes

r#nning independentl% of the "ernel$ '/amples of micro"ernel operating s%stems

are *, 8eAS, 9#rd, Mach, Mac AS , M=and J=$

9%!rid "ernels are similar to micro"ernels, e/cept that the% incl#de additional code

in "ernel space so that s#ch code can r#n more s)iftl% than it )o#ld )ere it in #ser

space$ These "ernels represent a compromise that )as implemented !% some

de(elopers !efore it )as demonstrated that p#re micro"ernels can pro(ide high

performance$ 9%!rid "ernels sho#ld not !e conf#sed )ith monolithic "ernels that

can load mod#les after !ooting s#ch as Lin#/$

Most modern operating s%stems #se h%!rid "ernels, incl#ding Microsoft .indo)s

=T, 2000 and P$ Dragon1l% 8SD, a recent%or,i$e$, (ariant of 1ree8SD, is the

first non&Mach !ased 8SD operating s%stem to emplo% a h%!rid "ernel

architect#re$

'/o"ernels are a still e/perimental approach to operating s%stem design$ The%

differ from the other t%pes of "ernels in that their f#nctionalit% is limited to the

protection and m#ltiple/ing of the ra) hard)are, and the% pro(ide no hard)are

a!stractions on top of )hich applications can !e constr#cted$ This separation of

hard)are protection from hard)are management ena!les application de(elopers to

determine ho) to ma"e the most efficient #se of the a(aila!le hard)are for each

specific program$

'/o"ernels in themsel(es the% are e/tremel% small$ 9o)e(er, the% are

accompanied !% library operatin+ systems, )hich pro(ide application de(elopers

)ith the con(entional f#nctionalities of a complete operating s%stem$ * major
http://www.linfo.org/minix.htmlhttp://www.linfo.org/minix.html


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ad(antage of e/o"ernel&!ased s%stems is that the% can incorporate m#ltiple li!rar%

operating s%stems, each e/porting a different *P application programming

interface, s#ch as one for Lin#/ and one for Microsoft .indo)s, th#s ma"ing it

possi!le to sim#ltaneo#sl% r#n !oth Lin#/ and .indo)s applications$

T0 M**$10$+ V'& M$+'* C*1'*


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alphan#meric characters and !efore it is con(erted !% a compilerinto ob1ect code

that a comp#ter>s processor can directl% read and e/ec#te$

1or e/ample, the so#rce code for the Lin#/ "ernel (ersion 2$4$0 is appro/imatel%

:00M8 and contains nearl% 3$3; million lines, and that for (ersion 2$?$0 is 2:2M8

and contains


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directl% )ith the hard)are, creates a not&insignificant cost in terms of s%stem

efficienc%$

L$&

L$&refers to the famil% of 7ni/&li"e comp#ter operating s%stems#sing

the Lin#/ "ernel$ Lin#/ can !e installed on a )ide (ariet% of comp#ter hard)are,

ranging from mo!ile phones, ta!let comp#ters and (ideo game consoles, to

mainframes and s#percomp#ters$ Lin#/ is the leading ser(erAS, acco#nting for

more than


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F-1&' *> L$&:

Lin#/ has e(ol(ed to ha(e the follo)ing feat#res as an o#tstanding operating

s%stem )hich is strong in sec#rit% and net)or"ing$

] M#ltitas"ing Se(eral programs can r#n at the same time$

]M#lti#ser Se(eral #sers can logon to the same machine at the same time There is

no need to ha(e separate #ser licenses$

] M#ltiplatform Lin#/ r#ns on man% different CP7s, that means it s#pports

m#ltiprocessor machine$

] M#ltithreading Lin#/ has nati(e "ernel s#pport for m#ltiple independent threads

of control )ithin a single process memor% space$

]Crash proof Lin#/ has memor% protection !et)een processes, so that one

program can>t !ring the )hole s%stem do)n$

]Demand loads e/ec#ta!les Lin#/ onl% reads from those parts of a program that

are act#all% #sed on the dis"$

]Shared cop%&on&)rite pages among e/ec#ta!les This means that m#ltiple

processes can #se the same memor% to r#n in$ .hen one tries to )rite to that

memor%, that page )ith 4B8 piece of memor% is copied some)here else$ Cop%&

on&)rite has t)o !enefits increasing speed and decreasing memor% #se$

] irt#al memor% #ses paging not s)apping )hole processes to dis" to a separate

partition or a file in the file s%stem, or !oth, )ith the possi!ilit% of adding more

s)apping areas d#ring r#ntime %es, the%>re still called s)apping areas$ * total of

:? of these :2; M8 2G8 in recent "ernels s)apping areas can !e #sed at the

same time, for a theoretical total of 2 G8 of #sa!le s)ap space$ t is simple to

increase this if necessar%, !% changing a fe) lines of so#rce code$


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]Lin#/ has a #nified memor% pool for #ser programs and dis" cache, so that all free

memor% can !e #sed for caching, and the cache can !e red#ced )hen r#nning large

programs$

] Lin#/ does core d#mps for post&mortem anal%sis, allo)ing the #se of a de!#gger

on a program not onl% )hile it is r#nning !#t also after it has crashed$

] Lin#/ is mostl% compati!le )ith PAS, S%stem , and 8SD at the so#rce le(el$

] Thro#gh an i8CS2&compliant em#lation mod#le, Lin#/ is mostl% compati!le

)ith SCA, S3, and S4 at the !inar% le(el$

] 1ree and Apen so#rce code for all *ll so#rce code of Lin#/ is a(aila!le,

incl#ding the )hole "ernel and all dri(ers, the de(elopment tools and all #ser

programsQ also, all of it is freel% distri!#ta!le$ Plent% of commercial programs are

!eing pro(ided for Lin#/ )itho#t so#rce, !#t e(er%thing that has !een free,

incl#ding the entire !ase operating s%stem, is still free$

] Lin#/ s#pports pse#do terminals pt%>s and m#ltiple (irt#al consoles 8% se(eral

independent login sessions thro#gh the console, %o# can s)itch !et)een !%

pressing a hot&"e% com!ination not dependent on (ideo hard)are$ These are

d%namicall% allocatedQ %o# can #se #p to ?4$

] Lin#/ s#pports se(eral common file s%stems, incl#ding mini/, eni/, and all the

common s%stem file s%stems, and has an ad(anced file s%stem of its o)n, )hich

offers file s%stems of #p to 4 T8, and names #p to 2t need an% special commands to #se the MS&

DAS partition, it loo"s j#st li"e a normal 7ni/ file s%stem e/cept for f#nn%

restrictions on file names, permissions, and so on$ MS&DAS ? compressed

partitions do not )or" at this time )itho#t a patch dmsdosfs$ *lso 1*T .=T,

.indo)s @


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] Lin#/ has CD&AM file s%stem )hich reads all standard formats of CD&AMs$

] Lin#/ performs )ell )ith TCPP net)or"ing, incl#ding ftp, telnet, =1S, etc$

] Lin#/ is #ser&friendl% as =et)are client and ser(er

] Lin#/ also r#ns as Lan Manager.indo)s =ati(e SM8 client and ser(er

] t integrates man% net)or"ing protocols The !ase protocols a(aila!le in the latest

de(elopment "ernels incl#de TCP, P(4, P(?, *$2


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RS!!

RS!! ('$- 6*'1):

S&232 ecommended Standard & 232 is a telecomm#nications standard for

!inar%serial comm#nications !et)een de(ices$ t s#pplies the roadmap for the )a%

de(ices spea" to each other #sing serialports$ The de(ices are commonl% referred

to as a DT' data terminal e-#ipment and DC' data comm#nications

e-#ipmentQ for e/ample, a comp#terand modem, respecti(el%$

S232 is the most "no)n serial port #sed in transmitting the data in

comm#nication and interface$ '(en tho#gh serial port is harder to program than the

parallel port, this is the most effecti(e method in )hich the data transmission

re-#ires less )ires that %ields to the less cost$ The S232 is the comm#nication

line )hich ena!les the data transmission !% onl% #sing three )ire lin"s$ The three

lin"s pro(ides 5transmit, 5recei(e and common gro#nd$$$

The 5transmit and 5recei(e line on this connecter send and recei(e data !et)een

the comp#ters$ *s the name indicates, the data is transmitted seriall%$ The t)o pins

are TD F D$ There are other lines on this port as TS, CTS, DS, DT, and

TS, $ The 5: and 50 are the data )hich defines a (oltage le(el of 3 to 2


59/108

The S&232D has e/isted in t)o t%pes$ i$e$, D&TNP' 2< pin connector and D&

TNP' @ pin connector, )hich are male connectors on the !ac" of the PC$ No# need

a female connector on %o#r comm#nication from 9ost to G#est comp#ter$ The pin

o#ts of !oth D&@ F D&2< are sho) !elo)

D&T%pe&@ pin

no$

D&T%pe&2< pin

no$

Pin o#ts 1#nction

3 2 D ecei(e Data Serial data inp#t

2 3 TD Transmit Data Serial data o#tp#t

E 4 TS e-#est to send ac"no)ledge to modem

that 7*T is read% to e/change data; < CTS Clear to send i$e$Q modem is read% to

e/change data

? ? DS Data read% state 7*T esta!lishes a

lin"

< E SG Signal gro#nd

: ; DCD Data Carrier detect This line is acti(e

)hen modem detects a carrier4 20 DT Data Terminal ead%$

@ 22 ing ndicator 8ecomes acti(e )hen

modem detects ringing signal from PST=

R!!


60/108

.hen comm#nicating )ith (ario#s micro processors one needs to con(ert the

S232 le(els do)n to lo)er le(els, t%picall% 3$3 or


61/108

one (oltage 6-+2 1* $+'*+*1'*'


62/108

M*232 is connected to the microcontroller as sho)n in the fig#re a!o(e ::, :2

pin are connected to the :0 and :: pin ie transmit and recei(e pin of

microcontroller$

TEMPERATURE SENSOR

F-1&'


63/108

] Cali!rated directl% in O Celsi#s Centigrade

] Linear 6 :0$0 mOC scale factor

] 0$


64/108

*n analog temperat#re sensor is prett% eas% to e/plain, its a chip that tells %o#

)hat the am!ient temperat#re is These sensors #se a solid&state techni-#e to

determine the temperat#re$ That is to sa%, the% dont #se merc#r% li"e old

thermometers,!imetalic stripsli"e in some home thermometers or sto(es, nor do

the% #se thermistors temperat#re sensiti(e resistors$ nstead, the% #se the fact as

temperat#re increases, the (otage across a diode increases at a "no)n rate$

Technicall%, this is act#all% the (oltage drop !et)een the !ase and emitter & the

!e & of a transistor$ 8% precisel% amplif%ing the (oltage change, it is eas% to

genereate an analog signal that is directl% proportional to temperat#re$

Meas#ring temperat#re

To con(ert the (oltage to temperat#re, simpl% #se the !asic form#la

Temp in OC V Ho#t in m & in the image a!o(e and the form#la

Temp in OC V o#t in m :0

Testing %o#r temperat#re sensor

Testing these sensors is prett% eas% !#t %o#>ll need a !atter% pac" or po)er s#ppl%$

Connect a 2$E&


65/108

(oltage sho#ld !e a!o#t 0$Ere #sing a LM3


66/108

the gas collecting container and ha(ing at least a pair of electrodes positioned

thro#gh electrol%teQ and a (oltage appl%ing apparat#s for appl%ing (oltage to the

detecting section$ Ane of the electrodes of the detecting section is a detection

electrode ha(ing the capa!ilit% of adsor!ing at least one of h%drogeno#s gas and

CA gas )hen a (oltage is applied and then o/idi+ing it$ 8% introd#cing a meas#red

gas into a gas collecting container of the CA gas sensor and carr%ing o#t

electrol%sis according to a potential s)eep method or a p#lse method )ith the

meas#red gas !eing in contact )ith the detecting section, a CA gas concentration

in the meas#red gas can !e meas#red !ased on an electrical c#rrent (al#e o!tained

at the detecting section and changes of the electrical c#rrent )ith elapse of time$

*ccording to the CA gas sensor of the present in(ention, it is possi!le to acc#ratel%

carr% o#t detection and meas#rement of the concentration of CA gas )hen CA gas

is to !e detected or meas#red e(en in a gaseo#s atmosphere containing a relati(el%

large amo#nt of h%drogen gas and CA2 gas$

D'SCPTA=

1'LD A1 T9' ='=TA=

The present in(ention relates to a CA gas sensor for meas#ring the concentration of

CA gas contained in a gaseo#s phase and to a method of meas#ring the

concentration of CA gas, and in partic#lar relates to a CA gas sensor for meas#ring

the concentration of CA gas in a gaseo#s atmosphere containing relati(el% high

concentrations of h%drogen gas and car!on dio/ide gas, a f#el cell po)er

generating apparat#s e-#ipped )ith s#ch CA gas sensor, and a method of

meas#ring the concentration of CA gas$


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8*CBGA7=D *T

n man% cases, h%drogen gas is #sed as a f#el gas for f#el cells$ *s s#ch h%drogen

gas, a h%drogen gas rich reforming gas )hich is o!tained !% reforming methanol or

the li"e is #sed$ .hen man#fact#ring s#ch a reforming gas, a tin% amo#nt of

car!on mono/ide CA, namel% se(eral tens ppm to se(eral h#ndred ppm, is

present as imp#rities$ 1or this reason, )hen s#ch a reforming gas is #sed as a f#el

gas for a f#el cell, the CA gas is adsor!ed on the s#rface of the platin#m catal%st of

the f#el cell electrodes, th#s hindering ioni+ation of the h%drogen gas and lo)ering

the o#tp#t of the f#el cell$ n order to ta"e appropriate meas#res to co#nter s#ch a

pro!lem ca#sed !% the CA gas, it is necessar% to contin#o#sl% monitor the

concentration of CA gas in the reforming gas #sed in the f#el cell$

Con(entionall%, as for the most commonl% #sed CA gas sensor, there are "no)n a

controlled potential anal%sis t%pe CA gas sensor and a semicond#ctor t%pe CA gas

sensor$ 9o)e(er, for the reasons gi(en !elo), neither of these CA gas sensors is

appropriate for detecting CA gas in a reforming gas$

=amel%, the reforming gas contains h%drogen gas #sed as a f#el in the f#el cell for

the amo#nt of a!o#t E


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in )hich interference !% h%drogen gas occ#rs$

n (ie) of the pro!lem mentioned a!o(e, it is an o!ject of the present in(ention to

pro(ide a CA gas sensor )hich can acc#ratel% carr% o#t detection -#alitati(e

anal%sis and meas#rement -#antitati(e anal%sis of the concentration of CA gas

)hen CA gas is detected or meas#red in a gaseo#s atmosphere containing a

relati(el% large amo#nt of h%drogen gas and car!on dio/ide gas, a f#el cell po)er

generating apparat#s e-#ipped )ith s#ch a CA gas sensor, and a method of

meas#ring the concentration of CA gas$

RELAY

* rela% is an electrical s)itch that opens and closes #nder the control of

another electrical circ#it$ n the original form, the s)itch is operated !% an

electromagnetto open or close one or man% sets of contacts$ 8eca#se a rela% is

a!le to control an o#tp#t circ#it of higher po)er than the inp#t circ#it, it can !e

considered to !e, in a !road sense, a form of an electrical amplifier$
http://en.wikipedia.org/wiki/Switchhttp://en.wikipedia.org/wiki/Electrical_circuithttp://en.wikipedia.org/wiki/Magnethttp://en.wikipedia.org/wiki/Amplifierhttp://en.wikipedia.org/wiki/Switchhttp://en.wikipedia.org/wiki/Electrical_circuithttp://en.wikipedia.org/wiki/Magnethttp://en.wikipedia.org/wiki/Amplifier


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Small rela% as #sed in electronics

* simple electromagnetic rela%, s#ch as the one ta"en from a car in the first

pict#re, is an adaptation of an electromagnet$ t consists of a coil of )ire

s#rro#nding a soft iron core, an iron %o"e, )hich pro(ides a lo) rel#ctancepath

for magnetic fl#/, a mo(ea!le iron armat#re, and a set, or sets, of contactsQ t)o in

the rela% pict#red$ The armat#re is hinged to the %o"e and mechanicall% lin"ed to a

mo(ing contact or contacts$ t is held in place !% a springso that )hen the rela% is

de&energi+ed there is an air gap in the magnetic circ#it$ n this condition, one of the

t)o sets of contacts in the rela% pict#red is closed, and the other set is open$ Ather

rela%s ma% ha(e more or fe)er sets of contacts depending on their f#nction$ The

rela% in the pict#re also has a )ire connecting the armat#re to the %o"e$ This

ens#res contin#it% of the circ#it !et)een the mo(ing contacts on the armat#re, and

the circ#it trac" on the Printed Circ#it 8oard PC8(ia the %o"e, )hich is soldered

to the PC8$

.hen an electric c#rrentis passed thro#gh the coil, the res#lting magnetic field

attracts the armat#re and the conse-#ent mo(ement of the mo(a!le contact or

contacts either ma"es or !rea"s a connection )ith a fi/ed contact$ f the set of

contacts )as closed )hen the rela% )as de&energi+ed, then the mo(ement opens

the contacts and !rea"s the connection, and (ice (ersa if the contacts )ere open$

.hen the c#rrent to the coil is s)itched off, the armat#re is ret#rned !% a force,

appro/imatel% half as strong as the magnetic force, to its rela/ed position$ 7s#all%

this force is pro(ided !% a spring, !#t gra(it% is also #sed commonl% in ind#strial

motor starters$ Most rela%s are man#fact#red to operate -#ic"l%$ n a lo) (oltage

application, this is to red#ce noise$ n a high (oltage or high c#rrent application,

this is to red#ce arcing$

f the coil is energi+ed )ith DC, a diodeis fre-#entl% installed across the coil, to

dissipate the energ% from the collapsing magnetic field at deacti(ation, )hich
http://en.wikipedia.org/wiki/Electromagnethttp://en.wikipedia.org/wiki/Coilhttp://en.wikipedia.org/wiki/Magnetic_corehttp://en.wikipedia.org/wiki/Magnetic_reluctancehttp://en.wikipedia.org/wiki/Armature_(electrical_engineering)http://en.wikipedia.org/wiki/Spring_(device)http://en.wikipedia.org/wiki/Printed_circuit_boardhttp://en.wikipedia.org/wiki/Electric_currenthttp://en.wikipedia.org/wiki/Magnetic_fieldhttp://en.wikipedia.org/wiki/Arcinghttp://en.wikipedia.org/wiki/Flyback_diodehttp://en.wikipedia.org/wiki/Electromagnethttp://en.wikipedia.org/wiki/Coilhttp://en.wikipedia.org/wiki/Magnetic_corehttp://en.wikipedia.org/wiki/Magnetic_reluctancehttp://en.wikipedia.org/wiki/Armature_(electrical_engineering)http://en.wikipedia.org/wiki/Spring_(device)http://en.wikipedia.org/wiki/Printed_circuit_boardhttp://en.wikipedia.org/wiki/Electric_currenthttp://en.wikipedia.org/wiki/Magnetic_fieldhttp://en.wikipedia.org/wiki/Arcinghttp://en.wikipedia.org/wiki/Flyback_diode


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!% a magnetic field generated )hen c#rrent passes thro#gh a coilaro#nd the glass

t#!e$ eed rela%s are capa!le of faster s)itching speeds than larger t%pes of rela%s,

!#t ha(e lo) s)itch c#rrent and (oltage ratings$ See also reed s)itch$

M'+&'375112 '-3

* merc#r%&)etted reed rela% is a form of reed rela% in )hich the contacts are

)etted )ith merc#r%$ S#ch rela%s are #sed to s)itch lo)&(oltage signals one (olt

or less !eca#se of its lo) contact resistance, or for high&speed co#nting and timing

applications )here the merc#r% eliminates contact !o#nce$ Merc#r% )etted rela%s

are position&sensiti(e and m#st !e mo#nted (erticall% to )or" properl%$ 8eca#se of

the to/icit% and e/pense of li-#id merc#r%, these rela%s are rarel% specified for ne)e-#ipment$ See also merc#r% s)itch$

P*-'$?2 '-3

* Polari+ed ela% placed the armat#re !et)een the poles of a permanent magnet to

increase sensiti(it%$ Polari+ed rela%s )ere #sed in middle 20th Cent#r% telephone

e/changesto detect faint p#lses and correct telegraphic distortion$ The poles )ere

on scre)s, so a technician co#ld first adj#st them for ma/im#m sensiti(it% and then

appl% a !ias spring to set the critical c#rrent that )o#ld operate the rela%$

M-+0$ 1** '-3

* machine tool rela% is a t%pe standardi+ed for ind#strial control of machine tools,

transfer machines, and other se-#ential control$ The% are characteri+ed !% a large

n#m!er of contacts sometimes e/tenda!le in the field )hich are easil% con(erted

from normall%&open to normall%&closed stat#s, easil% replacea!le coils, and a form

factorthat allo)s compactl% installing man% rela%s in a control panel$ *ltho#gh

s#ch rela%s once )ere the !ac"!one of a#tomation in s#ch ind#stries as a#tomo!ile

assem!l%, theprogramma!le logic controllerPLC mostl% displaced the machine

tool rela% from se-#ential control applications$
http://en.wikipedia.org/wiki/Coilhttp://en.wikipedia.org/wiki/Reed_switchhttp://en.wikipedia.org/wiki/Mercury_(element)http://en.wikipedia.org/wiki/Mercury_switchhttp://en.wikipedia.org/wiki/Crossbar_switchhttp://en.wikipedia.org/wiki/Crossbar_switchhttp://en.wikipedia.org/wiki/Form_factorhttp://en.wikipedia.org/wiki/Form_factorhttp://en.wikipedia.org/wiki/Programmable_logic_controllerhttp://en.wikipedia.org/wiki/Coilhttp://en.wikipedia.org/wiki/Reed_switchhttp://en.wikipedia.org/wiki/Mercury_(element)http://en.wikipedia.org/wiki/Mercury_switchhttp://en.wikipedia.org/wiki/Crossbar_switchhttp://en.wikipedia.org/wiki/Crossbar_switchhttp://en.wikipedia.org/wiki/Form_factorhttp://en.wikipedia.org/wiki/Form_factorhttp://en.wikipedia.org/wiki/Programmable_logic_controller


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C*1-+1*' '-3

* contactor is a (er% hea(%&d#t% rela% #sed for s)itching electric motors and

lighting loads$ 9igh&c#rrent contacts are made )ith allo%s containing sil(er$ The

#na(oida!le arcing ca#ses the contacts to o/idi+e and sil(er o/ide is still a good

cond#ctor$ S#ch de(ices are often #sed for motor starters$ * motor starter is a

contactor )ith o(erload protection de(ices attached$ The o(erload sensing de(ices

are a form of heat operated rela% )here a coil heats a !i&metal strip, or )here a

solder pot melts, releasing a spring to operate a#/iliar% contacts$ These a#/iliar%

contacts are in series )ith the coil$ f the o(erload senses e/cess c#rrent in the load,

the coil is de&energi+ed$ Contactor rela%s can !e e/tremel% lo#d to operate, ma"ingthem #nfit for #se )here noise is a chief concern$

S*$271-1 '-3

Solid state rela%, )hich has no mo(ing parts 2< amp or 40 amp solid state

contactors

* solid state rela% SS is a solid stateelectronic component that pro(ides a

similar f#nction to an electromechanical rela% !#t does not ha(e an% mo(ing

components, increasing long&term relia!ilit%$ .ith earl% SS>s, the tradeoff came

from the fact that e(er% transistor has a small (oltage drop across it$ This (oltage

drop limited the amo#nt of c#rrent a gi(en SS co#ld handle$ *s transistors

impro(ed, higher c#rrent SS>s, a!le to handle :00 to :,200 amps, ha(e !ecome

commerciall% a(aila!le$ Compared to electromagnetic rela%s, the% ma% !e falsel%

triggered !% transients$

S*$2 1-1 +*1-+1*' '-3

* solid state contactor is a (er% hea(%&d#t% solid state rela%, incl#ding the

necessar% heat sin", #sed for s)itching electric heaters, small electric motorsand

lighting loadsQ )here fre-#ent onoff c%cles are re-#ired$ There are no mo(ing
http://en.wikipedia.org/wiki/Contactorhttp://en.wikipedia.org/wiki/Electric_motorhttp://en.wikipedia.org/wiki/Silverhttp://en.wikipedia.org/wiki/Solid_state_(electronics)http://en.wikipedia.org/wiki/Solid_state_relayhttp://en.wikipedia.org/wiki/Solid_state_(electronics)http://en.wikipedia.org/wiki/Electromechanicalhttp://en.wikipedia.org/wiki/Ampshttp://en.wikipedia.org/wiki/Electric_motorhttp://en.wikipedia.org/wiki/Contactorhttp://en.wikipedia.org/wiki/Electric_motorhttp://en.wikipedia.org/wiki/Silverhttp://en.wikipedia.org/wiki/Solid_state_(electronics)http://en.wikipedia.org/wiki/Solid_state_relayhttp://en.wikipedia.org/wiki/Solid_state_(electronics)http://en.wikipedia.org/wiki/Electromechanicalhttp://en.wikipedia.org/wiki/Ampshttp://en.wikipedia.org/wiki/Electric_motor


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parts to )ear o#t and there is no contact !o#nce d#e to (i!ration$ The% are

acti(ated !% *C control signals or DC control signals from Programma!le logic

controller PLCs, PCs, Transistor&transistor logic TTL so#rces, or other

microprocessor controls$

B&+00*? '-3

* 8#chhol+ rela%is a safet% de(ice sensing the acc#m#lation of gas in large oil&

filled transformers, )hich )ill alarm on slo) acc#m#lation of gas or sh#t do)n the

transformer if gas is prod#ced rapidl% in the transformer oil$

F*'+27%&$22 +*1-+1 '-3

* forced&g#ided contacts rela% has rela% contacts that are mechanicall% lin"ed

together, so that )hen the rela% coil is energi+ed or de&energi+ed, all of the lin"ed

contacts mo(e together$ f one set of contacts in the rela% !ecomes immo!ili+ed, no

other contact of the same rela% )ill !e a!le to mo(e$ The f#nction of forced&g#ided

contacts is to ena!le the safet% circ#it to chec" the stat#s of the rela%$ 1orced&

g#ided contacts are also "no)n as Ypositi(e&g#ided contactsY, Ycapti(e contactsY,

Yloc"ed contactsY, or Ysafet% rela%sY$

O


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G'- P-+,1 R-2$* S'


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and i&modepac"et&s)itched cell#lar technologies$ t is no) maintained !% the 3rd

Generation Partnership Project3GPP$

GPS #sage is t%picall% charged !ased on (ol#me of data$ This contrasts )ith

circ#it s)itchingdata, )hich is t%picall% !illed per min#te of connection time,

regardless of )hether or not the #ser transfers data d#ring that period$

GPS data is t%picall% s#pplied either as part of a !#ndle e$g$, < G8 per month for

a fi/ed fee or on a pa%&as&%o#se !asis$ 7sage a!o(e the !#ndle cap is either

charged per mega!%te or disallo)ed$ The pa%&as&%o#se charging is t%picall% per

mega!%te of traffic$

GPS is a !est&effort ser(ice, impl%ing (aria!le thro#ghp#t and latenc% that

depend on the n#m!er of other #sers sharing the ser(ice conc#rrentl%, as opposed

to circ#it s)itching, )here a certain -#alit% of ser(iceJoS is g#aranteed d#ring

the connection$ n 2G s%stems, GPS pro(ides data rates of


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S'>'2

GPS e/tends the GSM Pac"et circ#it s)itched data capa!ilities and ma"es the

follo)ing ser(ices possi!le

SMS messaging and !roadcasting

Y*l)a%s onY internet access

M#ltimedia messaging ser(iceMMS

P#sh to tal"o(er cell#lar PoC

nstant messagingand presence\)ireless (illage

nternet applications for smart de(ices thro#gh )ireless application protocol.*P

Point&to&pointP2P ser(ice inter&net)or"ing )ith the nternet P

Point&to&M#ltipointP2M ser(ice point&to&m#ltipoint m#lticast and point&

to&m#ltipoint gro#p calls

f SMS o(er GPS is #sed, an SMS transmission speed of a!o#t 30 SMS messages

per min#te ma% !e achie(ed$ This is m#ch faster than #sing the ordinar% SMS o(er

GSM, )hose SMS transmission speed is a!o#t ? to :0 SMS messages per min#te$

P'*1*+* &66*'12

GPS s#pports the follo)ing protocolsHcitation neededI

nternet protocolP$ n practice, !#ilt&in mo!ile !ro)sers #se P(4 since

P(?)as not %et pop#lar$

Point&to&point protocolPPP$ n this mode PPP is often not s#pported !%

the mo!ile phone operator!#t if the mo!ile is #sed as a modem to the
http://en.wikipedia.org/wiki/Multimedia_Messaging_Servicehttp://en.wikipedia.org/wiki/Push_to_talkhttp://en.wikipedia.org/wiki/Instant_messaginghttp://en.wikipedia.org/wiki/Wireless_Villagehttp://en.wikipedia.org/wiki/Wireless_Application_Protocolhttp://en.wikipedia.org/wiki/Point-to-point_(telecommunications)http://en.wikipedia.org/wiki/Point-to-Multipointhttp://en.wikipedia.org/wiki/Wikipedia:Citation_neededhttp://en.wikipedia.org/wiki/Wikipedia:Citation_neededhttp://en.wikipedia.org/wiki/Internet_protocolhttp://en.wikipedia.org/wiki/Mobile_browserhttp://en.wikipedia.org/wiki/IPv4http://en.wikipedia.org/wiki/IPv6http://en.wikipedia.org/wiki/Point-to-point_protocolhttp://en.wikipedia.org/wiki/Mobile_phone_operatorhttp://en.wikipedia.org/wiki/Multimedia_Messaging_Servicehttp://en.wikipedia.org/wiki/Push_to_talkhttp://en.wikipedia.org/wiki/Instant_messaginghttp://en.wikipedia.org/wiki/Wireless_Villagehttp://en.wikipedia.org/wiki/Wireless_Application_Protocolhttp://en.wikipedia.org/wiki/Point-to-point_(telecommunications)http://en.wikipedia.org/wiki/Point-to-Multipointhttp://en.wikipedia.org/wiki/Wikipedia:Citation_neededhttp://en.wikipedia.org/wiki/Internet_protocolhttp://en.wikipedia.org/wiki/Mobile_browserhttp://en.wikipedia.org/wiki/IPv4http://en.wikipedia.org/wiki/IPv6http://en.wikipedia.org/wiki/Point-to-point_protocolhttp://en.wikipedia.org/wiki/Mobile_phone_operator


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connected comp#ter, PPP is #sed to t#nnel P to the phone$ This allo)s an P

address to !e assigned d%namicall% to the mo!ile e-#ipment$

$2


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* tr#e Class * de(ice ma% !e re-#ired to transmit on t)o different fre-#encies at

the same time, and th#s )ill need t)o radios$ To get aro#nd this e/pensi(e

re-#irement, a GPS mo!ile ma% implement the d#al transfer mode DTM

feat#re$ * DTM&capa!le mo!ile ma% #se sim#ltaneo#s (oice and pac"et data, )ith

the net)or" coordinating to ens#re that it is not re-#ired to transmit on t)o

different fre-#encies at the same time$ S#ch mo!iles are considered pse#do&Class

*, sometimes referred to as Ysimple class *Y$ Some net)or"s s#pport DTM since

200E$

A22'$%

* GPS connection is esta!lished !% reference to its access point name*P=$

The *P= defines the ser(ices s#ch as )ireless application protocol.*P access,

short message ser(ice SMS, m#ltimedia messaging ser(ice MMS, and for

nternetcomm#nication ser(ices s#ch as emailand .orld .ide .e!access$

n order to set #p a GPS connection for a )ireless modem, a #ser m#st specif% an

*P=, optionall% a #ser name and pass)ord, and (er% rarel% an P address, all

pro(ided !% the net)or" operator$
http://en.wikipedia.org/wiki/Dual_Transfer_Modehttp://en.wikipedia.org/wiki/Access_Point_Namehttp://en.wikipedia.org/wiki/Wireless_Application_Protocolhttp://en.wikipedia.org/wiki/Short_Message_Servicehttp://en.wikipedia.org/wiki/Multimedia_Messaging_Servicehttp://en.wikipedia.org/wiki/Internethttp://en.wikipedia.org/wiki/Emailhttp://en.wikipedia.org/wiki/World_Wide_Webhttp://en.wikipedia.org/wiki/Wireless_modemhttp://en.wikipedia.org/wiki/IP_addresshttp://en.wikipedia.org/wiki/Dual_Transfer_Modehttp://en.wikipedia.org/wiki/Access_Point_Namehttp://en.wikipedia.org/wiki/Wireless_Application_Protocolhttp://en.wikipedia.org/wiki/Short_Message_Servicehttp://en.wikipedia.org/wiki/Multimedia_Messaging_Servicehttp://en.wikipedia.org/wiki/Internethttp://en.wikipedia.org/wiki/Emailhttp://en.wikipedia.org/wiki/World_Wide_Webhttp://en.wikipedia.org/wiki/Wireless_modemhttp://en.wikipedia.org/wiki/IP_address


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. DESIGN AND DEVEPLOPMENT OF HARDWARE.

M-$ C$'+&$1 D$-%'- -2 $1 *


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!. S31 S1&6 -2 C*>$%&'-1$*

B**1 O61$*:7

.e can select the !ooting mode !% toggling the s)itch S2$

.hen toggling the S2 s)itch to the =or 1lashK side the s%stem )ill !oot

from on !oard =or 1lash$ .hen toggling the S2 s)itch to the =and 1lashKside the s%stem )ill !oot from on !oard =and 1lash$

C*+1$% P'$60'-:7

Connect the M=2440 !oards serial port to a PCs serial port$

Connect the


88/108

Clic" on the CancelK !#tton on the follo)ing )indo)$

Clic" on the NesK !#tton and the ABK !#tton to the ne/t step$

* pop#p )indo) )ill re-#ire %o# to name this connection$ n this e/ample

)e t%ped 113S#. .indo)s does not accept names li"e COMthat ha(ealread% !een #sed !% the s%stem$


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*fter naming this connection another )indo) )ill re-#ire %o# to select a

serial port that )ill !e #sed to connect the M=2440 !oard$ 9ere )eselected CAM:

Lastl%, also the most important step is to set #p the port properties$ =ote

%o# m#st select N*in the data flo) control field other)ise %o# )ill onl%


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!e a!le to see o#tp#ts$ n addition the !its per second sho#ld !e set to::


91/108


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I1-$% B**1 *-2':7

Start the D=. applicationQ connect the M=2440 !oard to a host PC (ia a

7S8 ca!le$ f the D=.s title !ar sho)s USB:OK@it indicates that the7S8 connection is a s#ccess$ Select item


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Ance the do)nload is finished, 8AS )ill a#tomaticall% )rite thiss#per(i(i to =and 1lashs corresponding section and ret#rn to the mainmen#

I1-$% L$& K':7

n the 8AS main men#, select item H"I to do)nload a Lin#/ "ernel+mage


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Go to 7S8 PortK & TransmitestoreK, select a +mage file according toAS that )e )ant to load into the M= 2440


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I1-$% R**1 F$ S31 :7

n the 8AS main men# select item H%I to start do)nloading a %affs rootfile s%stem image$

Go to 7S8 PortK & TransmitestoreK, select a file s%stem image fileand start to do)nload$


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*fter the do)nload is done, 8AS )ill a#tomaticall% )rite it in =and1lashs corresponding section and ret#rn to the main men#

*fter the do)nload is done, please disconnect the 7S8 connection,other)ise it co#ld ca#se s%stem crash on reset or po)er&on$

n the 8AS main men#, select item H!I to re!oot the !oard

f the !oot mode is s)itched to the =and 1lash side, the s%stem )illa#tomaticall% !oot on po)er on$


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M$$!""# D


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M$$!""# D


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& : 2$0mm pitch :0&pin UT*G interface

& 4 7ser L'Ds

& ? 7ser !#ttons )ith lead !loc"s

& : !#++er P.M control

& : adj#sta!le resistor, analog&to&digital con(erter for *D test

& : 2C&!#s *T24C0; chip for 2C&!#s test

& : 2$0 mm pitch 20&pin camera interface

& An&!oard real&time cloc" !atter%

& Po)er interface < , )ith po)er s)itch and indicator light

S31 C*+, S*&'+

& :2 M9+ passi(e cr%stal

R-7T$ C*+,

& nternal real&time cloc" )ith lithi#m !atter% !ac"p

E6-$* I1'>-+

& : 34&pin 2$0 mm GPA interface

& : 40&pin 2$0 mm s%stem !#s interface

D$$*

& :00 mm / :00 mm

O6'-1$% S31 S&66*'1

& Lin#/ 2$?$2@

& .indo)s C' $='T -+ L-3*&1


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Mini2440 interface la%o#t is sho)n !elo) it in a (er% compact area of :00 mm / :00 mm

delicate arrangement of open made from a (ariet% of commonl% #sed interface, and also leads to

the need for de(elopment and testing of the s#rpl#s of the A ports and !#s interfaces$

D


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S2 has !een recei(ing side of =*=D flash, the s%stem !oot from a start#p operation of =*=D

flash s%stem$

E1'- I1'>-+ C*+1*'

& Please #se o#r direct serial line to connect the Mini2440s serial port 0 and PCs$

& 7se o#r crosso(er ca!le to the net)or" interface Mini2440 connected )ith the PC$

& 7se o#r < po)er adapter to connect to the < inp#t soc"et on the !oard$

& Spea"ers or headphones to pl#g access on&!oard a#dio o#tp#t port green$

& f %o# ha(e LCD screen, follo) the direction of head data and the LCD interface

Connected to Mini2440$

& Connect Mini2440 )ith 7S8 ca!le connection and the PC$


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WORKING PRINCIPLE:

The proposed ma"es #se em!edded !oard )hich ma"es #se of less po)er

cons#mpti(e and ad(anced micro controller li"e S3C2440$ S3C2440 is a Sams#ng

compan%s microcontroller, )hich designed !ased on the str#ct#re of *M @20T

famil%$ This microcontroller )or"s for a (oltage of 63$3 DC and at an operating

fre-#enc% of 400 M9+, The ma/im#m fre-#enc% #p to )hich this micro controller

can )or" is


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Ane other feat#re of the !oot loader is lo load operating s%stem related files

!%te !% !%te into the temporar% memor% li"e *M$ n o#r c#rrent project, )e are

#sing !oot loader li"e S#per (i(i, )hich is M= 2440 specific$

K': The core part of an operating s%stem )e can call li"e "ernel$ Aperating

s%stem )ill perform its f#nctionalities li"e 1ile management, Process management,

Memor% management, =et)or" management and nterr#pt management )ith the

help of the "ernel onl%$ Bernel holds the de(ice related dri(ers that are present on

the mother!oard$ 1'=DLN *M !oard s#pports for operating s%stems li"e

SNM8*=, *=DAD, 'M8'DD'D L=7, .=C'$ 9o)e(er, in all theseoperating s%stems 'M8'DD'D L=7 )ill pro(ide high sec#rit% to dri(ers and

files$ Therefore, in o#r c#rrent project )e are ma"ing #se of "ernel of

'M8'DD'D L=7 )ith )hich de(ice related dri(ers that are present on the

mother!oard of 1'=DLN *M !oard )ill a#tomaticall% come )hen )e load

'M8'DD'D L=7 related "ernel$

R**1 F$ S31 1ile s%stem )ill tell ho) files arrangement there inside the

internal standard storage de(ices$ n em!edded Lin#/, "ernel treats e(er%thing as a

file e(en the inp#t and o#tp#t de(ices$ n em!edded Lin#/, oot is the parent

director% it contains other s#! directories li"e de(, li!, home, !in ,s!in ,media

,mnt ,temp ,proc , etc, opt and etc$ *ccording to o#r application, )e )ill interface

some e/ternal de(ices also$ *ll the de(ices means internal de(ices that are present

on the mother!oard of M= 2440 )ill get their corresponding dri(ers )hen )e

load 'm!edded Lin#/ related "ernel$ 9o)e(er, these de(ice dri(ers re-#ire micro

controller related header files and some other header files, )hich )ill !e present in

the li! director%, )hich is present in the root director%$ n addition, the de(ices

related dri(ers )o#ld !e present in the de( director%, )hich is again present in the


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root director%$ Therefore, )hene(er )e )ill load the oot 1ile S%stem then )e )ill

get different directories, )hich )ill !e helpf#l to the "ernel$ So comp#lsoril%, )e

need to load the oot 1ile S%stem$ M= 2440 specific oot 1ile S%stem is oot

Jtopia$

The essential programs that are re-#ired in order to )or" )ith M=

2440 li"e 8oot loader, 'm!edded Lin#/ related Bernel, oot 1ile S%stem )ill !e

loaded into the =A flash )hich is present on the M= 2440 !oard itself$ The

program related )ith the application )ill !e loaded into =*=D flash, )hich is also

present on the M= 2440 !oard itself$ 8% #sing !ootstrap s)itch that is present on

the M= 2440 )ill help the #ser to select either =A or =*=D flash$ *fter that

!% #sing D=. tool )e can load 8oot loader, 'm!edded Lin#/ related "ernel and

oot 1ile S%stem into =A flash !% #sing 7S8 ca!le and the application related

program into =*=D flash$

Ance loading e(er%thing into M= 2440 !oard it starts )or"ing !ased on

the application program that )e ha(e loaded into the =*=D flash$ So controlling

station )aits for the remote data that is coming from the remote location$

To pro(ide the sec#rit% for home appliances )e are #sing *M@ !oard

)hich is interfaced to to#ch screen LCD, sensors li"e temperat#re and P sensor

and GPS$ 1irst of all the *M@ !oard )ill stores 3 persons image and their

information into its memor%$ 3 options are present on to#ch screen LCD li"e train,

capt#re and recogni+e$ f an% person is entered press train !#tton on LCD as )ell

as press capt#re !#tton$ *fter pressing capt#re !#tton t)o options )ill appear li"e

add and delete$ 8% pressing the add !#tton the )e!cam )hich is connected to

*M@ !oard )ill capt#res the person images #p to :< times$ *fter :< images the

train !#tton )ill a#tomaticall% goes lo)$ =e/t press recogni+e !#tton for

comparing capt#red image )ith stored images$ f capt#red image is matched )ith

stored images then the door a#tomaticall% )ill open !% #sing rela%$ f capt#red


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image is not matched )ith stored images then the capt#red image )ill !e sent

thro#gh GPS in the form of MMS$ f room temperat#re is increased or an%

dangero#s gas is present then the temperat#re and smo"e sensor )ill detect it and

displa% it on to#ch screen LCD$

$

$


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J. CONCLUSION


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CONCLUSION

The project A L*5 C*1 GSM/GPRS B-2 W$' H* S+&'$13

S31K has !een s#ccessf#ll% designed and tested$ t has !een de(eloped !%

integrating feat#res of all the hard)are components and soft)are #sed$ Presence of

e(er% mod#le has !een reasoned o#t and placed caref#ll% th#s contri!#ting to the

!est )or"ing of the #nit$ Secondl%, #sing highl% ad(anced *M@ !oard and )ith

the help of gro)ing technolog% the project has !een s#ccessf#ll% implemented$

GPRS Based Home Security System

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