GOSSIPO-2 chip: a prototype of read-out pixel array featuring high resolution TDC-per-pixel architecture. Vladimir Gromov , Ruud Kluit, Harry van der Graaf. NIKHEF, Amsterdam, The Netherlands. April 18, 2008.
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GOSSIPO-2 chip: a prototype of read-out pixel array featuring high resolution TDC-per-pixel architecture. Vladimir Gromov, Ruud Kluit, Harry van der Graaf.
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Slide 1
GOSSIPO-2 chip: a prototype of read-out pixel array featuring
high resolution TDC-per-pixel architecture. Vladimir Gromov, Ruud
Kluit, Harry van der Graaf. NIKHEF, Amsterdam, The Netherlands.
April 18, 2008.
Slide 2
Outline Drift time measurements in the GOSSIP detector.
Time-to-Digital Conversion with local oscillator. GOSSIPO-2 chip:
history, structure and features. Characterization and performance
of the pixel array of the chip. Conclusions and plans. V.GromovRD51
Workshop, 4/18/2008 2
Slide 3
GOSSIP detector: principles of operation. Cluster3 Cathode
(drift) plane Integrated Grid (InGrid) Cluster2 Cluster1 Slimmed
Silicon Readout chip Input pixel 1mm, 400V 50um, 400V 50um 3-D
track reconstruction Clusters drift time measurements - low
capacitance on the pixel ( down to 10 fF). - narrow drift gap (1
mm). - fast charge collection time (20 ns). - low diffusion of the
primary electrons (70 um/1.6 ns) X Y Z Gas On Slimmed Silicon Pixel
(GOSSIP): a detector combining a thin gas layer as signal generator
with a CMOS readout pixel array. High resolution TDC V.Gromov RD51
Workshop, 4/18/2008 3
Slide 4
Time-to-Digital Conversion based on local oscillator. Start
Stop Local oscillator Pixel_1 Hit Pixel_2 Clock Bus Clock signal
source Hit signal Clock signal (period is T slow ) Local
oscillator: output signal (period is T fast ) Drift time Measured
time Start Stop The number of clocks (N fast ) at the output of the
local oscillator gives the value of the drift time as follows:
Tdrift = T slow - N fast T fast -Time resolution is determined by
the frequency (T fast ) and performance of the local oscillator
circuit. -The local oscillator is active only within restricted
space of time. - Only slow Clock signal is being distributed across
the chip. Low power consumption Out V.Gromov RD51 Workshop,
4/18/2008 4
Slide 5
V.Gromov RD51 Workshop, 4/18/2008 5 GOSSIPO-2 chip: history,
structure and main features. History. 2006. GOSSIPO-1 (0.13um
CMOS): analog front-end: fast, low-noise (ENC=70 e - ) threshold
=350 e -, low-power (2 uW per channel). 2007. GOSSIPO-2 (0.13um
CMOS) : read-out pixel array. - sensitive area: 0.88 mm 2 (16
pixels x 16 pixels) - pixel size: 55 um. - high resolution
TDC-per-pixel architecture (bin=1.8 ns). -separate TDC block.
-separate local oscillator circuit. -analog monitor block.
Slide 6
Performance of the local oscillator circuit. NAND EN OUT Delay
= T fast /2 = Function (Temp, Vdd) EN T fast (1.8 ns) OUT Power
supply voltage, Volts Temperature, C T fast,ns - 12% / 100mV 2% /
10 C Channel-to-channel statistical spread is 4% Effect of the
power supply voltage. Effect of the temperature. 0nsT slow (25 ns)
015 (4-bit TDC) -If the power supply changes within 50 mV -If the
temperature changes within 30 C Accumulated error will be kept
within 6% (1.8 ns or 1 bin of the 4bit TDC). Schematic of the local
oscillator. V.Gromov RD51 Workshop, 4/18/2008 6
Slide 7
Performance of the TDC block. Start Stop Local oscillator Hit
Out In 4bitslow clock Counter TDC Control Out In 4bitfast clock
Counter Out Clock Trigger Read Reset Hit signal Signal at the input
of the fast clock counter (period is T fast = 1.8 ns) Start Stop
Signal at the input of the slow clock counter (period is T slow =
25 ns). Trigger signal Stop N slow N fast DATA _FORMAT = 4bit (N
slow ) + 4bit (N fast ) Clock - Time resolution is ( T fast ) is
1.8 ns. - Differential non-linearity is about 0.3 1.8 ns. - Dynamic
range is 4bit (T slow = 25 ns) is 350 ns. Data Output code,
converted as N slow 25 ns + N fast 1.8 ns delay of the Hit signal,
ns Transition region is about 30 ps! Discontinuity occurs when the
Hit signal goes over the leading edge of the slow clock (slow)
signal. Will be solved. Vdd=1.3 V Vdd=1.2 V Vdd=1.1 V TDC
structure. V.Gromov RD51 Workshop, 4/18/2008 7
Slide 8
GOSSIPO-2 chip: charge-sensitive preamplifier. I b =1 nA V b2 V
b1 Vdd=1.2 V Output Input C par 30 fF C fb = 1 fF Features. Low
parasitic capacitance at the input (30fF): - low power consumption
(2 W per channel). - pulse response rise-time is 20 ns - low noise
( n =70 e - ENC) threshold =350 e - - In order to confine time
jitter to the TDC bin size (1.8 ns) the signal must be larger then
4000 e -. -The DC feedback circuit is not tolerant for variation of
the fabrication process. This results in a number of not
operational channels (15 %-30 %). This will be solved in the
future. 0 20 Time, ns 40 60 80 Threshold =350 e - Signal size =
2400 e - Signal size = 800 e - time jitter / internal delay 8 ns
time jitter / internal delay 3 ns Time jitter / internal delay =
Rise_time 5 n / Signal size C in V OPAMP V.Gromov RD51 Workshop,
4/18/2008 8
Slide 9
GOSSIPO-2 chip: voltage comparator. Features. The comparator is
an OPAMP based on current mirrors architecture. the internal delay
is inverse proportional to the size of the input signal (as usual).
the minimum value of the internal delay (t min ) is much larger
than one bin of the TDC (1.8 ns). t min depends on the value of the
tail current (I tail ) and therefore t min is temperature dependent
t min is power supply voltage dependent t min takes different
values due to channel-to- channel mismatch. 1000 t min =15 ns
Threshold =350 e - I tail = 0.2 uA Signal size, electrons
Comparator delay I tail = 0.4 uA I tail = 0.8 uA 2000 30004000 -
Currently we are developing a faster comparator having internal
delay close to 1.8 ns (one bin of the TDC) even at low tail
currents (0.4 A). Instability and spread of the value of t min will
be negligible. V thr Output Input I tail Vdd=1.2 V t min =10 ns t
min =7 ns V.Gromov RD51 Workshop, 4/18/2008 9
Slide 10
GOSSIPO-2 chip: read-out pixel array. Functionality. -Only Slow
clock (40 MHz) is being distributed across the array. -All 256
pixel will be read out serially when the Read (Trigger) signal
arrives. - Clear_ON mode: data on the pixel will be RESET locally
if the Read signal is not available within 350ns after the hit
signal. - Clear_OFF mode: data on the pixel will be KEPT UNCHANGED
even if the Read signal is not available within 350ns after the hit
signal. -4 bit DAC for threshold tuning. - Control registers for
masking and test-pulse enabling. Pixel_1 In TDC block Out Read
(Trigger) Reset Clock Data Preamp Comp 4bit Threshold DAC Common
threshold Data Local threshold Input pad Test pulse Pixel_2Pixel_16
Pixel_256 Front-end V.Gromov RD51 Workshop, 4/18/2008 10
Slide 11
Test set-up for the GOSSIPO-2 read-out pixel array. PCB with
GOSSIPO-2 PCB with FPGA & USB port PC with LabView FPGA &
software: Upload configuration data (threshold DACs and mask
registers). Readout chip data. Read(trigger) signal and test pulse.
GOSSIPO-2 FPGA DC source Pulse generator Common threshold power
supply voltage USB GPIB test pulse Read (trigger) Clock (slow)
generator 40MHz. Clock (slow) generator 40MHz. Clock V.Gromov RD51
Workshop, 4/18/2008 11
Slide 12
Time resolution as a function of threshold value. - Low
threshold operation (350 e - ) in combination with large signal
size (larger than 4000 e - ) will allow for high time resolution
(jitter less than 1bin of the TDC = 1.8 ns). Threshold scan. Read
(Trigger) signal V(Q in ) Test pulse Measured time 160 150 Measured
time (converted output code), ns 140 time jitter 4bin 1.8 ns = 7.2
ns 130120 110 100 90 80 70 300 400 500 600 700 300 400 500 600 300
400 500 Threshold voltage, mV Threshold voltage, mV Threshold
voltage, mV noise time jitter 2bin 1.8 ns = 3.6 ns time jitter 1bin
1.8 ns = 1.8 ns Signal size = 1200 e - Signal size = 3000 e -
Signal size = 12000 e - In TDC block Out Read (Trigger) Reset Clock
Data Front-end Threshold Test pulse Pixel cell structure. V.Gromov
RD51 Workshop, 4/18/2008 12
Slide 13
Time scan. Read (Trigger) signal V(Q in >4000e - ) Test
pulse Measured time In TDC block Out Read (Trigger) Reset Clock
Data Front-end Threshold (350e - ) Test pulse Pixel cell structure.
Delay of the Test pulse, ns transition region 1 ns Measured time
(converted output code) [ns] Measured time (converted output code )
as a function of the delay of the Test pulse. Large signal (>
4000 e - ) and low threshold operation (350 e - ). delay Distortion
occurs when the Hit signal goes over the leading edge of the slow
clock (slow) signal. - The complete read-out chain demonstrates
good time resolution (transition region is 1ns) when the threshold
is low (350e - ) and the input signal is large (>4000e - ).
V.Gromov RD51 Workshop, 4/18/2008 13
Slide 14
Threshold equalization in the pixel array. 4bit Threshold DAC
Common threshold voltage Local threshold voltage Configuration
memory Serial Link Generation of the pixels threshold voltage.
Common threshold Before equalization. After equalization. Common
threshold Preamp output Preamp output Offset Pixel_1 - Threshold
spread after equalization per pixel: 150 e -. Pixel number 0 50 100
150 200250 Threshold offset, mV 200 300 400 500 Offset Pixel_2
Offset Pixel_3 600 Threshold offset, mV 200 300 400 500 Not
operational pixels (15%). These pixels should be masked Precision =
160 mV/16(4bit DAC) = 10 mV (150e - ) 160mV V.Gromov RD51 Workshop,
4/18/2008 14
Slide 15
Channel-to-channel spread of the measured time. Pixel_1 Output
Code_1 Pixel_2 Pixel_256 Read Reset Clock Test pulse Pixel array.
Distribution of the value of the measured time (converted output
code ). Threshold equalization has been done. Large signal (>
4000 e - ) and low threshold operation (350 e - ). Output Code_2
Output Code_256 Measured time (converted output code), ns 115 118
121 124 127 130 Entries 30 60 90 120 0 time interval 4bin 1.8 ns =
7.2 ns -Due to uneven delay inside the read-out circuit the pixels
will give different values for the measured time (converted output
code). These values are spread across 4 bins of the TDC (7.2ns). -
In the future we will solve this problem by means of using a faster
comparator (internal delay close to 1.8 ns). V.Gromov RD51
Workshop, 4/18/2008 15
Slide 16
Conclusions and plans. A small chip sensor array has
successfully been prototyped in the GOSSIP0-2 chip in 0.13 m CMOS
technology. The TDC per pixel with local oscillator satisfies the
design requirements: low power consumption, high time resolution
(1.8 ns bin) and simplicity. The front-end circuit of the pixels
readout will benefit from the low detector parasitic capacitance
and no need to compensate for the leakage current. Low threshold
(350 e - ) and fast peaking time (20 ns) enable for high quality
drift time measurements (jitters 1.8 ns) at large input signals
(>4000 e - ) and after accurate threshold equalization. Plans:
The DC feedback in the preamplifier will be revised (matching). A
faster comparator circuit is required in order to reduce internal
delay, spread and jitter. A small-area detector will be constructed
on top of the GOSSIPO-2 chip. This detector will be tested on the
beam in the end of 2008. V.Gromov RD51 Workshop, 4/18/2008 16
Slide 17
Additional slide. Protection against discharges. Metal layer LM
Metal layer TD Polymide Oxide High Resistive Amorphous Silicon 20um
3um Layout of the input pad R fb C p-sub 10fF Q discharge Output A
C p-grid 0.5fF R prot 1M - protective resistor causes neither
signal distortion nor noise increase as long as R prot C p-grid is
less than 1ns. V.Gromov RD51 Workshop, 4/18/2008 17
RD51 Workshop, 4/18/2008 V.Gromov19 Additional slide. Time
scan. Delay of the Test pulse, ns Measured time (converted output
code) [ns] Measured time (converted output code) [ns] Threshold
equalization has been done. Low threshold operation (350 e - ).
Signal = 3000 e - Signal = 1200 e -