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GNUradio_20061208

Jun 02, 2018

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    GNU Radio

    Chen ZhifengChen Ke-Yu

    Electrical and Computer EngineeringUniversity of Florida

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    OutlineWhy GNU Radio?Extensive knowledge involvedWhat is implemented currently?Library

    Architecture

    Development environmentDevelopment BoardsCurrent Issues

    What is next?

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    Why GNU Radio? Almost free!

    All the software are free (Python and C++ source code/linux environment)In most condition, no need expensive RF test machine!No need to purchase development and emulation toolsOnly a development board needed (Universal Software Radio Peripheral)

    FlexibleSoftware:

    reconfigurable for many other modulation methods for both standardizeradio or self-defined radioit is possible to improve the quality of the received signal by utilizing, insoftware, certain mathematical algorithms

    Hardware:Rx and Tx are selectableIntermediate frequency is controllable

    Best choice for research use and radio amateur

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    Extensive knowledge involved

    Software and environment:

    Python/Numeric python library/wxPython

    C++/boost C++ libraties

    Linux environment and lots of support packages:FFTW/cppunit/SWIG/SDCC/

    GNU Radio architecture

    Communications and RF:

    DSPDigital communications

    Wireless communications theory

    FPGA and Assemble language may be used

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    What is implemented currentlyBase System

    Provides the runtime and various signal processing primitives

    Hardware Support

    Universal Software Radio Peripheral (USRP)

    Audio Device Support ALSA (Advanced Linux Sound Architecture)

    OSS (Open Sound System)

    Graphics Support

    wxPython based GUISDL video library

    General Signal Processing

    Specialty Application Areas

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    Library

    Communication related implementation AM demodulationDifferential BPSK / QPSKGMSK modulation / demodulationNarrow band FM transmitter / receiverWide band FM transmitter & broadcast FMreceiver

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    Library (cont.)

    GNU radio utilitiesCRC generatorSocket setup (TCP / UDP)Compute frequency response of a digital filterControl National IMX2306 & SDR-1000frequency synthesizerSome utilities

    Convert unsigned mask into signed integerGcd, Lcm, Log2Return input x that is reverse order

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    Library (cont.)

    GUI examplesProvide window application for different usageFFT sink testwxPython EditBox, SliderDrawingWaterfall sink testOscilloscope Test Application

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    Library (cont.)

    pagerCreate USRP source object supplyingcomplex floatsFlex pager protocol demodulation block

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    Architecture overall

    Software

    Hardware

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    Architecture Hardware

    User-definedCode

    RFFront end

    Sender

    User-definedCode

    Receiver

    DAC

    ADC RFFront end

    FPGAUSB

    USB FPGA

    USRP (mother board)PC

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    Architecture Hardware

    User-definedCode

    RFFront end

    DACUSB FPGA

    Support USB2.0/At this stage, USB 1.x is not supported at all

    1. Support 32MB/sec across the USB.

    2. All samples sent over the USB interface are in 16-bit signed integers in IQformat,16-bit I and 16-bit Q data (complex), resulting in 8M complex samples/secacross the USB.

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    Architecture Hardware

    User-definedCode

    RFFront end

    DACUSB FPGA

    Includes digital down converters (DDC) implemented with cascadedintegrator-comb (CIC) filters.DDC

    Down converts the signal from the IF band to the base band.Decimates the signal so that the data rate can be adapted by the USB2.0 and is reasonable for the computers' computing capability.

    Digital up converters (DUCs) on the transmit side are actually contained inthe AD9862 CODEC chips, not in the FPGA.

    The only transmit signal processing blocks in the FPGA are theinterpolators.

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    Architecture Hardware

    User-definedCode

    RFFront end

    DACUSB FPGA

    4 high-speed 14-bit DA converters, DAC clock frequency is 128 MS/s(stay below about 50MHz or so to make filtering easier.)

    4 high-speed 12-bit AD converters, sampling rate is 64M samples persecond.

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    Architecture Hardware

    User-definedCode

    RFFront end

    DACUSB FPGA

    One mother board support up to four daughter boards.2. Several kinds of daughter boards available

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    Architecture Software

    GNU radio has provided some useful APIsWhat we are interested in at this time ishow to use the existing modules that hasbeen provided in GNU radio project tocommunicate between two end systems

    User-definedCode

    RFFront end

    Sender

    DACUSB FPGA

    PC

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    Architecture Software

    How these modules co-work?C++

    Performance-critical modules

    PythonGlue to connect modulesNon performance-critical modules

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    Architecture Software

    At python level, what we need to do is always justto draw a diagram showing the signal flowfrom the source to the sink in our mind.

    C++

    C++

    V1

    V2

    V3

    C++

    C++

    C++

    V1

    V2

    V3

    C++

    Source

    Sink

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    SPE (Stanis Python Editor) FreeLack of powerful debug tool (breakpoint)

    Development environment

    Explorer ofProject and

    Class members

    Code editor

    Interpreter & debug window

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    Development environment (cont.)

    WingwareMore powerfulFor personal version, the license fee to twostations are $60

    Code editor

    Interpreter

    Explorer ofProject and

    Class members

    Debuginformation

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    Development BoardsDescription Price

    USRP Motherboard $700.00

    BasicTX -- 2 MHz to 200 MHz Transmitter $75.00

    BasicRX -- 2 MHz to 300+ MHz Receiver $75.00

    LFTX -- DC-30 MHz Transmitter $75.00LFRX -- DC-30 MHz Receiver $75.00

    TVRX -- 50 MHz to 870 MHz Receiver $100.00

    DBSRX -- 800 MHz to 2.4 GHz Receiver $150.00

    RFX400 -- 400-500 MHz Transceiver $275.00

    RFX900 -- 800-1000MHz Transceiver $275.00

    RFX1200 -- 1150 MHz - 1450 MHz Transceiver $275.00

    RFX1800 -- 1.5-2.1 GHz Transceiver $275.00

    RFX2400 -- 2.3-2.9 GHz Transceiver, 20+mW output $275.00

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    USRP Motherboard Four 64 MS/s 12-bit analog to digitalConvertersFour 128 MS/s 14-bit digital to analogConvertersFour digital downconverters withprogrammable decimation rates

    Two digital upconverters withprogrammable interpolation ratesHigh-speed USB 2.0 interface (480 Mb/s)Capable of processing signals up to 16MHz wideModular architecture supports widevariety of RF daughterboards

    Auxiliary analog and digital I/O supportcomplex radio controls such as RSSI and

    AGCFully coherent multi-channel systems(MIMO capable)

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    BasicTX2 MHz to 200 MHz Transmitter

    designed for use withexternal RF frontendsas an intermediate

    frequency (IF) interface.DAC outputs aredirectly transformer-coupled to SMAconnectors (50impedance)direct access to all ofthe signals on thedaughterboard interface

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    BasicRX2 MHz to 300+ MHz Receiver

    designed for use withexternal RF frontendsas an intermediate

    frequency (IF) interface. ADC inputs are directlytransformer-coupled toSMA connectors (50impedance)direct access to all ofthe signals on thedaughterboard interface

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    LFTXDC-30 MHz Transmitter

    very similar to theBasicTX and BasicRX,respectively, with 2main differencesUse differentialamplifiers instead oftransformers, theirfrequency responseextends down to DC.have 30 MHz low passfilters for antialiasing.

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    LFRXDC-30 MHz Receiver

    very similar to theBasicTX and BasicRX,respectively, with 2main differencesUse differentialamplifiers instead oftransformers, theirfrequency responseextends down to DC.have 30 MHz low passfilters for antialiasing.

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    TVRX50 MHz to 870 MHz Receiver

    a complete VHF andUHF receiver systembased on a TV tunermodulecan receive a 6 MHzwide block of spectrumfrom anywhere in the 50-860 MHz range.

    All tuning and AGCfunctions can becontrolled from software.

    Note: The TVRX is the only daughterboard which is NOT MIMO capable. A MIMO

    capable version is expected in Q1 2007.

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    DBSRX800 MHz to 2.4 GHz Receiver

    a complete receiversystem for 800 MHz to 2.4GHz with a 3-5 dB noise

    figure.features a softwarecontrollable channel filteras narrow as 1 MHz, or aswide as 60 MHz.MIMO capable, and canpower an active antennavia the coax.

    Note: The DBSRX is NOT guaranteed to cover the 2.4-2.48 GHz ISM band.

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    RFX400400-500 MHz Transceiver

    100+mW output (20dBm) ideal for UHF TV, public safety

    and land-mobile

    communications, low-powerunlicensed devices (like key-fobs), wireless sensor networks(motes), and amateur radio.

    minor modifications to the boardcan move the frequency rangeto anywhere from 200 MHz to800 MHz

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    RFX900800-1000MHz Transceiver

    200+mW output (23dBm)with a 902-928 MHz ISM-band filter installed forfiltering strong out-of-band signals (like pagers).The filter can easily be bypassed to allow usageover the full frequency range, enabling use with

    cellular, paging, motes, and two-way radio, inaddition to the ISM band.

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    RFX12001150 MHz - 1450 MHz Transceiver

    200+mW output (23dBm) Coverage of navigation,

    satellite, and amateurbands.

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    RFX18001.5-2.1 GHz Transceiver

    100+mW output (20dBm)Coverage of DECT, US-DECT, and PCS(including unlicensed) frequencies.

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    RFX24002.3-2.9 GHz Transceiver

    50mW output(17dBm)with a bandpass filteraround the ISM band(2400-2483 MHz).The filter can beeasily bypassed,allowing for coverageof the full frequencyrange.

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    Demo

    SocketJPEG

    EncoderModulationHard Disk

    SocketHard Disk Demodulation

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    Demo (cont.)Modulation

    Demodulation

    Bit to Byte Gray codeEncoderDifferential

    EncoderReal toComplex

    Byte to Bit Gray codeDecoderDifferentialDecoder

    Real toComplex

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    Current issues

    Need a USRP + Microtune 4937Need a python IDE

    A long way to be commercializedHigh performance CPU requirementThe software is still under development

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    What is next?--possible applications and issues

    The clock recovery block doesnt work in theDBPSK modulation

    Add more functions, such as DQPSK, FSKinto our demoWe may test the transmission by actual wirelessconnection, since receiver doesnt ensurecorrect demodulation, for example, carriertracking, clock recovery, we may need to add:

    cyclic redundancy check (CRC)Retransmission control (ARQ)Based on what we have done, we may deploy aresearch-oriented project next