GMRIT-Nanoelectronics Dr. V. Ramgopal Rao Professor Department of Electrical Engineering Indian Institute of Technology, Bombay Powai, Mumbai-400076 Email: [email protected]Web: http://www.ee.iitb.ac.in/~rrao Nanoelectronics Nanoelectronics- Top Down Scaling Top Down Scaling The Technology trends & research opportunities The Technology trends & research opportunities GMRIT-Nanoelectronics What is expected ? Power 0 0 Design Time Cost 0 Complexity 0 Delay Size 0
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GMRIT-Nanoelectronics
Dr. V. Ramgopal Rao
ProfessorDepartment of Electrical Engineering
Indian Institute of Technology, BombayPowai, Mumbai-400076
NanoelectronicsNanoelectronics-- Top Down ScalingTop Down ScalingThe Technology trends & research opportunitiesThe Technology trends & research opportunities
• ―M etal‖ can be m etal, or more frequently heavily doped poly-Si
• ―O xide‖ is usually silicon dioxide, but can be some other high k dielectric
• ―S em iconductor‖ is usually Si , but can be SiGe, SiC
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Basic MOS Structure
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MOSFET Operation – Linear Region
VDS < VGS-VT
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MOSFET Operation – Saturation Region
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NMOS Transistor Equations
• So This is the linear region of operation
• For VDS > VGS-VT
This is the saturation region of operation
VVVVI
2
DSDSTGS 2
1
L
WCμox
D
2
TGSL
WCμ VVI
2
ox
D
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MOS Transistor Output Characteristics
From S. M. Sze, Physics of Semiconductor Devices, John Wiley (1981)
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MOS Transistor Subthreshold Characteristics
Subthreshold swing ~ 60 - 100 mV/decade
nkT
qKexpID
VV TGS
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ScalingScaling
W=0.7, L=0.7, Tox=0.7=> Lateral and vertical dimensions reduce 30 %Area Cap = C = 0.7 X 0.7 = 0.7
0.7=> Capacitance reduces by 30 %
Die Area = X x Y = 0.7x0.7 = 0.72
=> Die area reduces by 50 %
Vdd=0.7, Vt=0.7, T ox=0.7, I=(W/L) (Cox)(V-Vt)2 = 0.7
T= C x Vdd = 0.7, Power = CV2f = 0.7 x 0.72 = 0.72
I 0.7
=> Delay reduces by 30 % and Power reduces by 50 %
= 0.7
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Technology Technology -- Then and NowThen and Now
1981 2000 RATIO
Technology p-well CM OS
Dual W ell CM OS
Gate Oxide 40 nm 2 nm 20X
Poly Dimension 2.5 m 0.12 m 20X
M etal Layers 1 6
SRAM -Density Cell Area Access Time
4 K 1000 m2 40 nS
16 M 5 m2 1 nS
4000X 200X 40X
November 2000 Pentium 4 released with clock speed: 1.5 GHz Number of transistors: 42 million
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Technology ScalingGATE
SOURCE
BODY
DRAIN
Xj
ToxD
GATE
SOURCE DRAIN
LeffBODY
Dimensions scale down by 30%
Doubles transistor density
Oxide thickness scales down
Faster transistor, higher performance
Vdd & Vt scaling Lower active power
Technology has scaled well, will it in the future?Technology has scaled well, will it in the future?
GMRIT-Nanoelectronics
Transistor Count Trend
From S. E. Thompson, Sub-100 nm CMOS, IEDM 1999 Short Course
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Minimum Feature Size Trend
From S. E. Thompson, Sub-100 nm CMOS, IEDM 1999 Short Course
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Microprocessor Frequency Trend
From S. E. Thompson, Sub-100 nm CMOS, IEDM 1999 Short Course
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ChallengesChallenges--CMOS ScalingCMOS Scaling
Meikei Ieong, IBM
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SIA Roadmap
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Outline• CMOS Power Challenges
• Possible Solutions– Technology approaches– Circuit approaches– System level approaches
GMRIT-Nanoelectronics
Outline• CMOS Power Challenges
• Possible Solutions– Technology approaches– Circuit approaches– System level approaches
GMRIT-Nanoelectronics
Technology ScalingGATE
SOURCE
BODY
DRAIN
Xj
ToxD
GATE
SOURCE DRAIN
LeffBODY
Dimensions scale down by 30%
Doubles transistor density
Oxide thickness scales down
Faster transistor, higher performance
Vdd & Vt scaling Lower active power
Technology has scaled well, will it in the future?Technology has scaled well, will it in the future?
GMRIT-Nanoelectronics
Transistor Integration Capacity
0.001
0.01
0.1
1
10
100
10 5 2 1 0.5 0.25 0.13
Tran
sist
ors
(Mill
ion)
Technology (m)
Million Tr
On track for 1B transistor integration capacityOn track for 1B transistor integration capacity
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Is Transistor a Good Switch?
On
I = ∞
I = 0
Off
I = 0
I = 0
I ≠ 0
I = 1ma/u
I ≠ 0
I ≠ 0Sub-threshold Leakage
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Drain Induced Barrier Lowering (DIBL)
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Channel Length Modulation
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Channel Length Modulation
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Short-Channel Effects
Velocity Saturation
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SCESCE--Gate Oxide ScalingGate Oxide Scaling
L=150 nmL=70 nm
G ate O xide T hickn e ss (n m )
0 1 2 3 4 5 6 7
0
50
100
150
200
250
300
350
DIB
L (m
V/V
)D
IBL
(mV
/V)
• Short-channel effects• Drive Current • Circuit Performance• Manufacturability• Reliability
The success of silicon is because of SiO2
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Hot-Carrier Effects in MOS Devices
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ChallengesChallenges--CMOS ScalingCMOS Scaling
Meikei Ieong, IBM
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Statistical Dopant Fluctuations
25 nm channel MOSFET will have an intrinsic VT uncertainty of about 10/W1/2 mV/m1/2, where W is the width of the FET. May betolerable for logic, which tends to be wider and less dense, but may prove problematic for SRAM, where the width is usually minimized. The maximum variation on a chip for such cases can exceed 6s or 250 mV.
• CVD - more common (Carbon contamination)• Recently, direct oxidation of Ti
In RTP with 100 % O2
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SiGe Gate for reducing the poly-depletion problems
UC Berkeley
Low Temp Activationand lower resistivityfor the P+ poly SiGe filmscompared to Poly-Si
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Advanced Gate Electrode
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Dual Metal Gates for CMOS
F ms values for Ru and Ru-Ta alloyOn SiO2 and HfO2/SiO2
UC Berkeley-Molybdenum implanted with nitrogen can show a large workfunction shift
NCSU, 2003
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Mid-gap Gate Materials (SiGe)
• Excellent gm for p-MOSFETs• Counter doping required to adjust Vt
for n-channel ; buried channel operation
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Source/Drain Engineering
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• Laser thermal activation for 50 nm gate lengths
Ultra Shallow S/D Junction Formation
Heat the sample beyond the melting point of Si for ashort period of time in the order of nanoseconds,which significantly enhances the solubility withoutappreciable diffusion.
Hitachi, Japan, IEDM 2003
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Plasma Immersion Ion Implantation• High throughput (400X for 300 mm wafers)• Low Machine cost• Ultra-shallow doping profiles due to
low implantation energy• Room Temp. operation• Compatibility to CMOS
Particularly suitable for p-MOSFETs
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Plasma Implantation Induced Damage
• Charging Damage– Occurs when there is imbalance
in electron and ion currents– Wafer surface gets charged to
a potential,causing a gate to – substrate potential difference (Vgs)– If Vgs is sufficiently large, FN
current begins to flow through the oxide
– This current creates traps/interfacestates,and degrades oxide quality
– Charging damage is dangerous, because it is cumulative in nature !– Occurs during pattering of interconnects
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Silicides• CVD Cobalt process as against the PVD Cobalt for improved step coverage• Novel CVD-cobalt process with CCTBA (DiCobalt HexaCarbonylt-Butylacetylene)
precursor to avoid the formation of thick interfacial oxide on Si.
ULSI Metallization Schemes• Tungsten (W) is used to for contact hole filling (via plugs or contact studs).
Decomposition of WF6 is used for W deposition. A barrier m etallic ‗glue film ‘ is normally used to inhibit the diffusion of fluorine to silicide or silicon surface, and for good adhesion.
• Deposit blanket W by Sputtering and then planarize the metal by ―C hem ical-M echanical P olishing (C M P )‖.
(W)
Reflow Al plugs is an active research area for some low cost products.
Damascene process isused for interconnects
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Aluminum Interconnect Patterning
Lift-OffSubtractive Etch
Lift-off avoids metal etch, increasing the pattern flexibility, but has limited extendibility for sub 0.5 m feature sizes.
Deposit sequentially aluminum alloy, use the same film to fill contacts and define interconnects.
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Damascene Process
Damascene Conventional
Adv. of Damascene:Eliminates the metal etch process. So alloy metals can be used.
Works well with W, Al alloys, Cu and Ag.
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Multi-Level Metal Interconnects
• Pentium II uses five levels of metal interconnects• Refractory metals are used as first level metal because of their process and thermal
thermal stability, and Al is used for upper-level metals (lower resistivity)
Schematic of a five level interconnect system
Low-k inter-level dielectrics (ILD)an active area of intense research.Currently used ILD: CVD-TEOS based oxides. Fluorine is incorporated to reduce the dielectricconstant.
GMRIT-Nanoelectronics
Planarization-Why?• The demand for increasing metal levels calls for ILD planarity.ILD planarization serves two purposes: (i) to provide a smooth surface for good metal step coverage(ii) to provide a flat-enough surface, within the lithography depth of focus (for
patterning of contact vias and metal wires)
No planarization
Smoothing
Partial planarization
Local planarization
Global planarization
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Chemical-Mechanical Polishing (CMP)
Polishing pad
• Used for ILD planarization, and useful for polishing of metal in W plug formation.
Polishing slurry consistsof colloidal silica suspended in KOH solution
R= Kp p v,R is rate of removal, p is applied pressure, v is relative velocity between the wafer and polishing pad, Kp is the proportionality constant (known as Preston coefficient, units (pressure)-1)=> the process is also chemical, not purely mechanical
Preston Equation
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n 6-8 layers of metaln Vias and wires manufactured at same time (dual damascene)n Top levels are thicker for power distributionn Interlayer dielectrics are not all
Interconnects
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Interconnects Will Limit Performance
M.Bohr, TED 2002
• Copper for interconnects• Low-K for ILD
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Low-K for ILD Applications
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Interconnects
• Copper a fast diffuser• Reluctance to introduce
newer materials• Damascene
Copper by Electroplating
As k reduces the mechanical strength is a problem
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Low-K Porous Silica FilmsK~2, for 45 nm node
Excellent mechanical strength
Japan, IEDM 2003
Porous SiOCH film (k=2.5), NEC, Japan
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Metal Barriers & Cap Films
• Copper interconnects require two types of barrier layers: a liner on the sides and a capon top of the damascene features. The key functions of the barrier layers are to preventcopper and oxygen diffusion and promote adhesion with both the interlayer dielectric(ILD) and the copper. The cap layer must also protect the copper from corrosion duringsubsequent patterning steps and act as an etchstop for partially landed vias.
• The current metal barrier technologies using a PVD Ta(N) liner and a PECVD Si(C)Ndielectric cap will be replaced within the next few years due to difficulties withscaling these technologies to <100nm damascene feature sizes while maintainingsatisfactory performance for wire resistance and current density.
• New liner technologies using ALD metal nitride alloys provide a one-generation delayto the wire resistance problem but add new challenges for wire current densityscaling and integration with porous low-k ILD materials.
1. Maintaining good electrostatic control of channel potential(e.g., double-gate FET, ground-plane FET, and ultrathin-body SOI) by controlling the device physical geometry and providing means to terminate drain electric fields.2. Sharp doping profiles, halo/pocket implants.3. High gate capacitance (thin gate dielectrics, metal gateelectrode) to provide strong gate control of channel potential.
Advantages• Better control of SCE; High ON current,
Low OFF current• S~60mV/dec if Leff > 4Tsi+12Tox• Small DIBL if Leff > 2Tsi+12Tox• Fully depleted channel with possible intrinsic channel• Easy layout
FinFET is a variation of planar Double gate MOSFET that has channels along vertical direction
GMRIT-Nanoelectronics
Existing challenges for FINFET research
Experimental Studies:• V T engineering• S eries resistance reduction• D em onstrate sm all gate length device w ith high perform ance (Low
over drive but high current)• D em onstrate the R F properties of the devices in circuits
Theoretical studies: Device parameter models including quantum effectsCompact model development
Geometrical channel width defined as
W=2*H fin +T fin
Channel width can be increased by Placing Number of fins in parallel
FinFET
Nowak, IBM
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IBM
Finfet
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2-D Modeling
Assumptions• Simple Gaussian S/D profiles & Uniformly doped Channel region• Uniformity in vertical Doping of S/D regions• Quantum Mechanical effects are not effective at 45nm node• Energy balance model considers Quantum effects
(in a potential well close to the surface) at 10nm node
Results• 15% Under estimation in Drive Current• Variation of Gm with fin width because of
parasitic resistance and charge centroid.• Necessary to solve coupled Poisson and Schrodinger
equations to find optimum Gm• At 10nm node
• Mobility degradation (~10%) due to Quantum effects
• Drive current increases (~20%) due to ballistic effects
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Triple Gate Devices
• Triple gate device shows 20% greater drive current than double gatefor same size
• AMD proposed multi gate device and claims 50% greater drive than other finFETs
Double gate FinFET Triple get FinFET
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Corner effects in FinFET
Corner device shows much improved subthreshold swing and DIBL overNon corner device because of proximity effect
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Finfet Design Considerations
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Circuit Perceptive
• Bench mark circuits like FO4, NAND pull stack,and Pass gate mux are simulated using mixed mode simulators
• Larger & com plex circuits can‟t be sim ulatedbecause of lack of good circuit models
• Operational 6-transistor SRAM cell with cell sizeof 4.8um2 in 180nm technology by IBM
• Conversion of existing SOI microprocessor design to enable FinFET technology
(source: 1. E .J.N ow ak, “A F unctional F inF E T -D G C M O S S R A M C ell”, IE D M 20022. T . Ludw ig, “F inF E T T echnology for F uture M icroprocessors”, IE E E T E D
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Multiple gate replacement
• Independent Double-Gate MOSFETs• Front and back (top or bottom) gates can operate independently• Better logic design • Dynamic VT control, and thus adaptive threshold
and leakage tuning.• Mixer Circuits for RF applications
• M1 and M2 can be combined into one DGFET• S w itch level m odel for conduction is controlled using signal „A O R B ‟ • One of the advantages of planar double-gate devices over FinFETs from a circuit designer‟s perspective is the possibility of independent back -gate-bias.
• Given the continued development of planar and quasi-planar double-gate processes, circuit designers could find attractive uses for a hypothetical device such as “G round -plane F inF E T ” w ith independent bottom -gate control.
• Maximization of Device Current Drive (Current drive capability and
switching speed)
• Minimization of device short channel effects
• Maximization of device punch through resistance
GMRIT-Nanoelectronics
Buried Oxide
FieldOxide
FieldOxide
OxideSpacer
Buried Oxide
FieldOxide
FieldOxide
TiSi2
Buried Oxide
FieldOxide
FieldOxide
OxideSpacer
S D
poly
Boron
Ge
S D
Amorphous Si
DS
poly
poly
(A)
(B)
(C)
Starting Material
SOI Wafers Si Film Thinning Down
Ge Implantation, 12, 20, and
40 Kev, 1 1015 cm-2
(35 nm, 50 nm, and 80 nm)
Active Area Definition and LOCOS
Threshold Voltage Adjustment(For Conventional MOSFET)Gate Oxidation (4 nm) and Poly Deposition (200 nm)
E-beam Poly Gate Lithographyand Poly Etch
Source/Drain Extension Implant
Large Angle Tilt Implant for VTHAdjustment (for LAC MOSFET)
RTA Anneal (1020 oC, 15 seconds)
Oxide Spacer
Ti Deposition (20~35 nm)Two Step RTA Silicidation
Contact Hole
Metallization and Forming Gas
A
B
C
LAC MOSFET Fabrication-Both Bulk and SOI ProcessDevelopment
UCLA & IIT Bombay
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Approaching a “R ed B rick W all”
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Technology Challenges
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MOSFET Scaling Scenario
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From H.S.P.Wong, Sub-100 nm CMOS, IEDM 1999 Short Course
GMRIT-Nanoelectronics
Outline• CMOS Power Challenges
• Possible Solutions– Technology approaches– Circuit approaches– System level approaches
GMRIT-Nanoelectronics
The Gigascale Dilemma• 1B T integration capacity will be available• But could be unusable due to power• Logic T growth will slow down• Transistor performance will be limitedSolutions• Low power design techniques• Improve design efficiency• Meet the performance specs by even higher
integration (of slower transistors)
GMRIT-Nanoelectronics
• Active power reduction techniques – Clock gating– Supply voltage reduction
• Leakage power reduction techniques – Body biased transistors– Sleep transistors– Dual threshold voltage CMOS
Higher probability of target frequency with:Higher probability of target frequency with:1.1. Larger transistor sizes Larger transistor sizes 2.2. Higher LowHigher Low--Vt usageVt usage
But with power penaltyBut with power penalty
00.5
11.5
2
Transistor size
small large
powertarget frequency probability
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Outline• CMOS Power Challenges
• Possible Solutions– Technology approaches– Circuit approaches– System level approaches
GMRIT-Nanoelectronics
Shift in Design Paradigm
• From deterministic design to probabilistic and statistical design– A path delay estimate is probabilistic (not
deterministic)• Multi-variable design optimization for
– Yield and bin splits – Parameter variations– Active and leakage power– Performance
GMRIT-Nanoelectronics
Resistor Network
4.5 mm
5.3
mm
Multiplesubsites PD & Counter Resistor
Network
CUT Bias Amplifier
Delay
Die frequency: Min(F1..F21)Die power: Sum(P1..P21)
Technology 150nm CMOSNumber of subsites per die 21
Body bias range 0.5V FBB to 0.5V RBB
Bias resolution 32 mV
1.6 X 0.24 mm, 21 sites per die150nm CMOS
Adaptive Body Bias--Experiment
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Adaptive Body Bias
0%
20%
60%
100%
Acc
epte
d di
e
noBB
100% yield
ABB
Higher Frequency
Num
ber o
f die
s
Frequency
too slow
ftarget
too leaky
ftarget
ABB
FBB RBB
Num
ber o
f die
s
Frequency
too slow
ftarget
too leaky
ftarget
ABB
FBB RBB
97% highest bin
within die ABB
For given Freq and Power densityFor given Freq and Power density•• 100% yield with ABB 100% yield with ABB •• 97% highest freq bin with ABB for 97% highest freq bin with ABB for within die variability within die variability
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Active Power Reduction
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Increase on-die Memory
Large on die memory provides:1. Increased Data Bandwidth & Reduced Latency2. Hence, higher performance for much lower power
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Chip MultiChip Multi--ProcessingProcessing
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Summary— Delaying Forever
• Gigascale transistor integration capacity will be available— Power and Energy are the barriers
• Variations will be even more prominent— shift from Deterministic to Probabilistic design
• Improve design efficiency• Multi— everywhere, & SOC valued performance• Exploit integration capacity to deliver performance in