Cb Upgrade Electronics – 2011.07.21 GLIB, Gigabit Link Interface Board Paschalis VICHOUDIS PH-ESE-BE on behalf of the GLIB team (S. Baron, M. Barros Marin, V. Bobillier, S. Haas, M. Hansen, M. Joos, F. Vasey, P. Vichoudis) LHCb UPGRADE ELECTRONICS 21 JULY 2011 1
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GLIB, Gigabit Link Interface Board Paschalis VICHOUDIS PH-ESE-BE on behalf of the GLIB team
GLIB, Gigabit Link Interface Board Paschalis VICHOUDIS PH-ESE-BE on behalf of the GLIB team (S. Baron, M. Barros Marin, V. Bobillier, S. Haas, M. Hansen, M. Joos, F. Vasey, P. Vichoudis) LHCb UPGRADE ELECTRONICS 21 JULY 2011. Introduction. CONCEPT. - PowerPoint PPT Presentation
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LHCb Upgrade Electronics – 2011.07.21 1
GLIB, Gigabit Link Interface Board
Paschalis VICHOUDISPH-ESE-BE
on behalf of the GLIB team(S. Baron, M. Barros Marin, V. Bobillier, S. Haas, M. Hansen, M. Joos, F. Vasey, P. Vichoudis)
LHCb UPGRADE ELECTRONICS 21 JULY 2011
LHCb Upgrade Electronics – 2011.07.21 2
Introduction
THE GLIB IS: an evaluation platform and an easy entry point for users of high speed optical links
THE GLIB IS TARGETED FOR: optical link evaluation in the laboratory control, triggering and data acquisition from remote modules in beam or irradiation
tests
CONCEPT
GBT
Versatile Link
TIA
LD
PD
LaserGBT13
TRx
FPGA
Payload
GBT GLIB
E-Link
LHCb Upgrade Electronics – 2011.07.21 3
Rapid development (first prototype spring 2011)
“Low” cost (capacity limited to four GBT lanes)
Long lifetime (distribution and support of a small set of variants over several
Double width AdvancedMC (AMC) module for μTCA environment or bench-top use. Based on a high-performance Virtex-6 FPGA with Multi-Gigabit Transceivers (MGTs) up
to 6.5Gbps. Sockets for up to four pluggable 10Gbps optical transceiver modules (SFP+). Sockets for two expansion FPGA Mezzanine Cards (FMCs) for user-specific I/Os and up to four additional MGTs (optional).
On-board memory
IntroductionOVERVIEW
LHCb Upgrade Electronics – 2011.07.21 5
IntroductionTYPICAL USE CASES (1/6)
GLIB
Timing/Trig to FE
FRONT-END
FPGA
GBT payloadGLIB configGbE:
Slow CTRLDAQ
Timing/TrigGBT:
Power Supply
FRONT-ENDFRONT-ENDGBT(s)
SRAM
800Mbps
3.2Gbps/link 144Mb
BENCH-TOP: beam test setup
= SFP+= TTC FMC
LHCb Upgrade Electronics – 2011.07.21 6
IntroductionTYPICAL USE CASES (2/6)
Timing/Trig to FESlow CTRLDAQ
Timing/TrigE-Link:
Power Supply
FRONT-ENDFRONT-END
GLIB
FPGA
SRAM
GBT payloadGLIB configGbE:
80Mbps160Mbps320Mbps }Per E-Link
Up to 22 E-Links
144Mb
800Mbps
BENCH-TOP: front-end module test setup
= SFP+= TTC FMC= E-LINK FMC
LHCb Upgrade Electronics – 2011.07.21 7
GLIB
GBT payload
Timing/Trig to FE
FRONT-END
GLIB configPCIe:
FPGA
PCIe adapter
Slow CTRLDAQ
Timing/TrigGBT:
Power Supply
3.2Gbps/link
14Gbps
GBT(s)
IntroductionTYPICAL USE CASES (3/6)
BENCH-TOP: system test setup
= SFP+= TTC FMC
LHCb Upgrade Electronics – 2011.07.21 8
GLIB
Timing/Trig to FE
FRONT-END
FPGA
GLIB configGbE:
Slow CTRLDAQ
Timing/TrigGBT:
Power Supply
FRONT-ENDFRONT-END
GBT payload10GbE:3.2Gbps/link
GBT(s)
IntroductionTYPICAL USE CASES (4/6)
BENCH-TOP: system test setup [remote control/readout]
= SFP+= TTC FMC= 10GbE FMC
LHCb Upgrade Electronics – 2011.07.21 9
GLIB
HARDDISK
GBT payloadGLIB config
Timing/Trig to FE
FRONT-END
GbE:
FPGA
BackplaneCrate
GLIB
FPGA
GbESlow CTRL
DAQTiming/Trig
GBT:
FRONT-ENDFRONT-END
SRAM SRAM
GbEswitch
ClockDistr.
PCIeswitch
MCHμP
Commercial MCH
Crate Management
GBT(s)
IntroductionTYPICAL USE CASES (5/6)CRATE: beam test setup
= SFP+= TTC FMC
LHCb Upgrade Electronics – 2011.07.21 10
GbEswitch
ClockDistr.
PCIeswitch
MCHμP
Commercial MCH
GLIB
CPU StorageMedium
GLIB config
Storage
Timing/Trig to FE
FRONT-END
CPU
FPGA
BackplaneCrate
GLIB
FPGA
Slow CTRLDAQ
Timing/TrigGBT:
GBT payload
PCIe:
FRONT-ENDCrate Management
GBT(s)
IntroductionTYPICAL USE CASES (6/6)CRATE: system test setup
= SFP+= TTC FMC
LHCb Upgrade Electronics – 2011.07.21
Introduction
Electronics Coordination Board, 13-September-2010
GLIB
Timing/Trig to FE
FRONT-END
FPGA
GBT payloadGLIB configGbE:
Slow CTRLDAQ
Timing/TrigGBT:
Power Supply
FRONT-ENDFRONT-ENDGBT(s)
SRAM
800Mbps
3.2Gbps/link 144Mb
Timing/Trig to FESlow CTRLDAQ
Timing/TrigE-Link:
Power Supply
FRONT-ENDFRONT-END
GLIB
FPGA
SRAM
GBT payloadGLIB configGbE:
80Mbps160Mbps320Mbps }Per E-Link
Up to 22 E-Links
144Mb
800Mbps GbEswitch
ClockDistr.
PCIeswitch
MCHμP
Commercial MCH
GLIB
CPU StorageMedium
GLIB config
Storage
Timing/Trig to FE
FRONT-END
CPU
FPGA
BackplaneCrate
GLIB
FPGA
Slow CTRLDAQ
Timing/TrigGBT:
GBT payload
PCIe:
FRONT-ENDCrate Management
GBT(s)
The GLIB team envisages to deliver and support software, firmware and
hardware for the following 3 setups:- Bench-top beam test setup
- Bench-top front-end module test setup
- Crate system test setup
The required FMCs (TTC & E-Link) will also be delivered and supported.
= SFP+= TTC FMC= E-LINK FMC
Bench-top front-end module test setupBench-top beam test setup Crate system test setup
DELIVERABLES
LHCb Upgrade Electronics – 2011.07.21 12
Hardware
AMC edgeconnector
Port [0:1]
Port [4:7] MGT quad
CLK1/TCLKA
JTAG circuitry(CPLD-based)Module Management
Controller (MMC)IPMI
JTAG
FPGA
GbE
Port [12:15]
4x SFP+
4
SRAM
I/O
CLK
JTAG
FMC#2
FMC#1
I2C
ClockDistribution
Circuitry
GbEPHY
20
I/O
CLK
JTAGI2C
TRx
4
160
160
SRAM
4
4
CLK2/TCLKBCLK3/FCLKA
Port [2:3]
Port [8:11] MGT quad
M-LVDS TRx
Port [17:20]MGT quad
MGT quad
Diff. I/O pairs
ARCHITECTURE (1/2)
LHCb Upgrade Electronics – 2011.07.21 13
HardwareARCHITECTURE (2/2)
LHCb Upgrade Electronics – 2011.07.21 14
HardwareFIRST PROTOTYPE (TOP VIEW)
LHCb Upgrade Electronics – 2011.07.21 15
HardwareFIRST PROTOTYPE (BOTTOM VIEW)
LHCb Upgrade Electronics – 2011.07.21 16
AMC edgeconnector
Port [0:1]
Port [4:7] MGT quad
CLK1/TCLKA
JTAG circuitry(CPLD-based)Module Management
Controller (MMC)IPMI
JTAG
FPGA
GbE
Port [12:15]
4x SFP+
4
SRAM
I/O
CLK
JTAG
FMC#2
FMC#1
I2C
ClockDistribution
Circuitry
GbEPHY
20
I/O
CLK
JTAGI2C
TRx
4
160
160
SRAM
4
4
CLK2/TCLKBCLK3/FCLKA
Port [2:3]
Port [8:11] MGT quad
M-LVDS TRx
Port [17:20] MGT quad
MGT quad
Diff. I/O pairs
FIRST PROTOTYPE TEST RESULTSHardware
P0 TxN only
EEPROM only
The second version of GLIB has been launched, expected end July
LHCb Upgrade Electronics – 2011.07.21 17
Mezzanine cardsTTC FMC ARCHITECTURE
GLIB
Timing/Trig to FE
FRONT-END
FPGA
GBT payloadGLIB configGbE:
Slow CTRLDAQ
Timing/TrigGBT:
Power Supply
FRONT-ENDFRONT-ENDGBT(s)
SRAM
800Mbps
3.2Gbps/link 144Mb
TTC FMC in bench-top beam test setup(Deliverable #1)
TrueLight replacement
LHCb Upgrade Electronics – 2011.07.21 18
Mezzanine cardsTTC FMC IMPLEMENTATION
LHCb Upgrade Electronics – 2011.07.21 19
Two different setups are available.
The setups include:
- Crate
- MCH
- Power supply
- CPU
- Commercial cards
The TCA infrastructure study became a different project “xTCA Evaluation Project” led by M. Joos
Planning to develop a Graphical Users Interface (GUI) for the IPBUS- Based on Java- A draft specification is available- A technical student will work on it starting for July (under the supervision of M. Joos)- Already some progress
IPBUS software reference: Robert Frazier, “IP Bus (Ethernet HAL) Software” http://indico.cern.ch/getFile.py/access?contribId=6&sessionId=1&resId=0&materialId=slides&confId=90024