Gigabit Kits Workshop August 2001 1 Washington WASHINGTON UNIVERSITY IN ST LOUIS IP Processing Wrapper Tutorial Gigabitkits Workshop August 2001 http://www.arl.wustl.edu/arl/projects/fpx/ wrapper/
Gigabit Kits Workshop August 2001 1Washington
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IP Processing WrapperTutorial
Gigabitkits Workshop August 2001http://www.arl.wustl.edu/arl/projects/fpx/wrapper/
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IP Processing Wrapper Library
Collection of protocol components in VHDL Module interface for higher protocol levels Translation from/to cells to/from higher levels Components handle protocol checksums and CRCs
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Stacked Wrapper
Application
Wrapper
Wrapper
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The Cell-Processor
• Checks the HEC and drops erroneous cells• Dispatch cells to application or bypass• Handles control cells• Recomputes HEC for outgoing cells
Cells
Control
DispatchCheck
HEC
HEC
Set
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AAL5 Frame Processor
• Frame Processor detects frame boundaries• FP handles CRC• FP segments data into cells
Frame
Detection
Cell
AAL5CRC AAL5CRCation
Segment
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IP Processor• Verify IP version• Check Header Checksum for application (ev. Drop)• Decrease TTL field (ev. ICMP msg)• Signal start of payload (SOP)• Recompute Header Checksum
IP DetectTTLDec
IPProcessor
TTL
ATM Header
IP Header
Ver HL ToS
Proto
Packet Length
Fragment
Checksum
IPID
Source IP address
Destination IP address
PayloadChecksum+Checksum
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UDP Processor
• Check for protocol ID (17)• Signal start of datagram (SOD)• Handle UDP checksum
UDPProcessor
UDP
Detect Checksum
Set
UDP Header
IP Header
Src Port Dest Port
Length Checksum
Payload
ATM Header
Ver HL
Proto
ToS
TTL Checksum
Fragment
Packet Len
IPID
Source IP address
Destination IP address
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Space & Speed
Space/LUTs Speed/MHz
Cell Processor 781 125
Frame Processor 1251 116
IP Processor 1009 109
UDP Processor 550 114
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Delays
Delay for short packages Delay for long packages
Input output Input output
Cell Processor
4 6 4 6
Frame Processor
21 22 10 31
IP Processor 36 39 24 197
UDP Processor
39 44 27 202
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Throughput
Throughput for short packages
Throughput for long packages
Input output Input output
Cell Processor
4 6 4 6
Frame Processor
21 22 10 31
IP Processor 36 39 24 197
UDP Processor
39 44 27 202
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Downloading the library
Download at http://www.arl.wustl.edu/arl/fpx/wrapper/ VHDL simulation files edif files for synthesis VHDL wrapper files
» Combine several layers for convenience
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Cell Wrapper files
Cellprocessor.edn» Synthesized cell processor» Use during place & route of your design
Cellprocessor.vhdl» Structural simulation file» Use during simulation of design
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Frame Wrapper Files
Frameprocessor.edn» Synthesized frame processor» Use during place & route of your design
Frameprocessor.vhdl» Structural simulation file» Use during simulation of design
Framewrapper.vhdl» Combine the frame processor with the cell processor
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IP Wrapper Files
ipprocessor.edn» Synthesized IP processor» Use during place & route of your design
ipprocessor.vhdl» Structural simulation file» Use during simulation of design
ipwrapper.vhdl» Combine the ip processor with the frame wrapper
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UDP Wrapper Files
udpprocessor.edn» Synthesized UDP processor» Use during place & route of your design
udpprocessor.vhdl» Structural simulation file» Use during simulation of design
udpwrapper.vhdl» Combine the UDP processor with the IP wrapper
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UDP Application
Input signals» D_MOD_IN (data input)» DataEn_MOD_IN (data enable)» SOF_MOD_IN (start of frame)» SOD_MOD_IN (start of datagram)» EOF_MOD_IN (end of frame)» TCA_MOD_IN (congestion
control)
Output signals» D_OUT_MOD (data output)» DataEn_OUT_MOD (data enable)» SOF_OUT_MOD (start of frame)» SOD_OUT_MOD (start of datagram)» EOF_OUT_MOD (end of frame)» TCA_OUT_MOD (congestion control)
General signals CLK (clock signal) Reset_l (synchronous reset, active
low)
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Clock & Reset
CLK» Clock signal for module» 100 MHz
Reset_l» Synchronous reset» Low for 1 clock cycle to reset state machines» Set by reconfiguration logic
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Data
D_MOD_IN + D_OUT_MOD» Data bus» 32 bit wide
DataEn_MOD_IN + DataEn_OUT_MOD» Hi during valid payload data» Hi during trailer words (after EOF)
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Boundary signals
SOF_MOD_IN + SOF_OUT_MOD» Hi for 1 clock cycle during first ATM header word» Signals start of a new AAL5 frame» Note: HEC is not sent after this signal
SOD_MOD_IN + SOD_OUT_MOD» Hi for 1 clock cycle during first word of UDP header» UDP payload starts after two valid payload words (check Data
Enable)» Not enabled if not a UDP packet
EOF_MOD_IN + EOF_OUT_MOD» Hi during 1 clock cycle of last payload word of datagram» Followed by the two trailer words of the AAL5 frame
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Congestion Control
TCA_MOD_IN + TCA_OUT_MOD» TCA signal is hi when data can be accepted, lo if no data
should be sent» Wrappers back-propagate TCA to the NID» Data in pipeline will still be forwarded (~cell time)» IP wrapper has big packet buffer for outgoing data
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Signals
DataEn
SOF
EOF
Data
SOC
Data
SOD
SOP/
A A I I I I I U U D D D D D D D D D D D DA A- - P P P F F - -
A - I I I I I U D D D D D - - - - D D D D D D D F F - - - - -
A
-
I
U
U
FP
DATM Header IP Header
Don't care Frame TrailerPadding
Payload Data
UDP Header
CLK
Cell LevelFram
e Level
IP Level
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Integrate Application
UDP Processor
Application
IP Processor
Cell Processor
Frame Processor
OutputInput
UDP Wrapper
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RAD
Application (with wrappers) Reconfiguration logic (reset
and repramming) Control Cell Processor (if
needed for SRAM/SDRAM access)
SRAM/SDRAM controller (if needed)
Application
ControlReconfig SRAM
Interface
Control
ProcessorCell
RAD
Ingress
Port
Egress
Port
Ingress
Port
SRAM
Egress
Port
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Synthesis
Add VHDL files for application Set part to “Xilinx Virtex 1000E fg680” Synthesize E.g. Synplicity/Synplify
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Place & Route
Copy wrapper-edif files (*.edn) to target directory “ngdbuild –p xcv1000e-7-fg680 design –uc design.ucf” “map –p xcv1000e-7-fg680 –o top.ncd design.ncd
design.pcf” “par –w –ol 2 top.ncd design.ncd design.pcf” “bitgen design.ncd –b –l –w –f bitgen.ut”