Ghép nối Thiết bị ngoại vi-Ch06

8/9/2019 Ghp ni Thit b ngoi vi-Ch06

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Ch6 Analog 5

Hnh 6.02-b. M hnh H o lng - iu khin s

Ch6 Analog 6

Process: L cc qu trnh cng ngh nh: dy chuyn xeo giy;

phi-trn-nghin-nung clinker => sn xut cement; dychuyn luyn-nung-cn thp, sn xut-trn phn bnNPK, cc nh my pht in...

Sensors: L vt liu/thit b dng chuyn i cc i lng

vt l khng in t th gii thc (T, RH, p, L, v, a, F,pH,..) thnh tn hiu in (u, i, R, f)

Vt liu: do c tnh t nhin ca vt cht v d RTDPt100, cp nhit in, piazo (titanate-bary), tenzometric

Thit b: c s gia cng/ch tc v d LM135precision temperature sensor, bn dn

Conditioners: V tn hiu t sensors thng rt nh, c th c nhiu v

phi tuyn => c mch in t analog x l tn hiu:khuch i, lc nhiu, b phi tuyn... cho ph hp.


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Ch6 Analog 7

MUX: analog multiplexer b dn knh Inputs: n bit chn knh, c 2n knh so analog, nh s t

0..2n-1; Output: 1 knh chung thng vi 1 trong s 2n inputs v duy

nht;

Nh vy ch cn 01 h VXL/MT v 01 ADC vn thu thpc nhiu im o cng ngh

Trch mu v gi - Sample & Hold: Dng trch mu ca t/h khi c xung sample (100s ns.. vi

us) v gi nguyn gi tr ca t/h trong khong thi gian luhn ADC chuyn i c n nh;

Ch dng trong cc trng hp tn hiu bin thin nhanhtng i so vi thi gian c/ ca ADC;

Nng cao chnh xc v tn s ca th.

Ch6 Analog 8

ADC: analog to digital convertor: Ri rc ha t/h v thi gian v s ha t/h lng t ha C nhiu phng php/tc /a chng dng ca

chuyn i

Central system: h nhng/MT: CPU, mem, bus, IO port, c th kt ni vi CSDL, net;

thu thp v x l so.

DAC: digital to analog convertor Bin i tn hiu s => lin tc v tg nhng vn ri rc

v gt; Nhiu loi: s bit/1 hay 2 du/tc ...


5/51

Ch6 Analog 9

Mch in t analog: C nhiu kiu chc nng ty thuc ng dng:

Lc ti to, tng hp m thanh; Khuch i n cc ccu chp hnh; Cch ly quang hc ghp ni vi cc thit b cng sut ln

(motor, breaker, ...)

Actuators: cc ccu chp hnh L 1 lp cc thit b tc ng ng trli dy

chuyn cng ngh; Chc: motor (3 phase Sync/Async, single phase, dc,

step) nh robot, printers motor, FDC/HDC motors... iu khin dng nng lng in: SCR (thyristor),

Triac, Power MOSFET, IGBT... iu khin dng cht lng/kh/gas: valves (percentage,

ON/OFF valves)

Ch6 Analog 10

H.6.2c.Mhnhh

DCS


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Ch6 Analog 11H. 5.02d. M hnh h SCADA

Ch6 Analog 12

6.2. analog electronics: chun ha tn hiu

Operational Amplifiers - OpAmps - Khuch ithut ton to cc b conditioners chun hatn hiu

Analog Switches & Analog Multiplexers

Reference Voltage Sourcers - ngun p chun

Sample & Hold - trch mu v gi

Converssion Errors - Sai s chuyn i

...


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Ch6 Analog 13

6.2. analog electronics: 6.2.1. Opamp

L vi mch khuch i, nigalvanic, x l th t 0Hz.

Tn hiu gm:

2 chn tn hiu Inv. Inp vNon Inv. Input

Chn Output

Ngun cp: +Vcc, -Vcc( Gnd)

Chnh Offset.

C th c thm chn ni tb tn s

H603. OperationalAmplifier (OpAmp)

Ch6 Analog 14

6.2.1. opamp: c im opamp

X l tn hiu dc (0 Hz up)

H s khuch i ln, t kilo... Mega... and even more...(GBW - Gain - band width Product, unit @ MHz)

Tr vo ln vi k n 1012, tr ra nh, 10s n100s, tt cho cc mch ghp ni analog, phi hp trkhng.

Hnh 6.04.Thit b 2 ca


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Ch6 Analog 15

6.2.1. opamp: c im opamp

Ngun cp di rng, 1 hoc 2 du: 3Vdc to 18Vdc Khuch Vi sai (Differential Amplifier), loi tr nhiu tt=> CMRR (Common Mode Rejection Ratio - h s khnhiu ng pha ln) up to 120dB Band width/ Slew rate: Bng thng/ Tc tng in pti a pha Output khi ca vo c bc nhy n v UOffset: Khi ca vo =0 m ca ra khc 0. in p tritheo thi gian v nhit => chnh Uoffset/ bias current ICs:

Linear Monolithic: A741 (Fair Child), LMx24s...(NS) Linear FET: TL 081/ 082/ 084 (TI), LF356/357/347..(NS)

Linear Hybrid: LH0024/ 0032 (NS-Hi Slewrate)

Instrumentation OpAmp: LM725/ LH0036/ 0038/ 0084(NS)

Ch6 Analog 16

Hnh 6.05a. Analog Comparator, dng trong ADC


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Ch6 Analog 19

Hnh 6.05d

Ch6 Analog 20

Hnh 6.05e


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Ch6 Analog 21

H 6.05f: Differential apmlifier

Ch6 Analog 22

Hnh 6.05-g. Instrumentation Ampl.


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Ch6 Analog 23

Hnh 6.05-h, dng trong cc ADC tch phn 2 sndc, c thi gian C chm, phn ly, CX cao, r

Ch6 Analog 24

Hnh 6.05-j, Active filter,fc m ti bin tn hiu gim 0.707

2nd order, -40dB/dec, bin th gim 100 ln khitn s tng 10 ln


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Ch6 Analog 25

Hnh 6.05-k, ging nh low pass

Xd cc mch:

Band pass, thng 1 di

Notch, chn 1 di

Ch6 Analog 26

Hnh 6.05-l. Mch lp li tn hiu (Follower),

- Bin i ngun t/h c ni tr ln thnh ngun s cni tr nh,

- Loi tr in tr (in p ri) trn cc mch trunggian v d nh loi b RON ca cc kha analog.


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Ch6 Analog 27

Hnh 6.05-n. i/ U Converter - ghp ni dac out

- Thng dng vi cc DAC Current Output types.

Ch6 Analog 28

Mt s lu khi dng OpAmp H s kc chn ty thuc cc mch:

Mch k thng thng (o du v khng o du: viln n 10 ln), nu cn hs k tng ln th dng nhiutng => n nh v d dng kim sot

Mch khuch i vi sai, H6.05f, t 10 dm chc ln

Mch ko lng (instrument) dm chc- trm ln,H6.05g, tng Vo Vi sai Ra Vi sai: 30 100 ln, tngVo Vi sai Ra n cc: 10 n 30.

Lu : chn HSK cng ln: Bng thng gim by nhiu ln in trvo gim by nhiu ln

n nh ca mch gim: tri zero theo thi gian, nhit


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Ch6 Analog 29

Dng mch cng dch trc. V d: Sensor nhit LM335: Range: -0oC +100oC

Sensitivity: nu cp dng t 0,5-5mA =>10mV/oK, @0oC => 2,73V; 100oC => 3,73V. Nu mun o theo OC=> phi dch trc, tri 2,73V. Ty thuc vo ADCInput Voltage s khuch i my ln.

Nu ADC Input Voltage = 5V => s dng mch K -5ln. Nh vy mi khai thc trit c phn ly ca

ADC

Mt s ch khi s dng OpAmp

Ch6 Analog 30

Case study 1: LM335 conditioning circuit


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Ch6 Analog 31

Case study 2: Loadcell Conditioning Circuit

Ch6 Analog 32

Case study: Pt100 sensor Pt100 l RTD, Resistance Thermo Device,

nhit in trPlatin, c R=100Ohm @ 0OC R/T = 0,39%/OC Xy dng mch chun ha tn hiu

conditioner, c Output = 0..5Vdc, nhit

o t 0..500OC Gi : Wheaston Bridge, Constant currentsourcerc b im zero


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Ch6 Analog 33

6.2.2. analog switches & multiplexers: a. Switches

Hnh 6.06. Symbol ofAnalog SPDT switch

Dng cp transistor FETb knh p v knh n => dndng ac

R(on) t 100 .. 1.5 k Off channel LeakageCurrent: 100 pA .. 1 nA =>Khng dng kha tnhiu p qu thp

Bin tn hiu:Vss


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Ch6 Analog 35

2n switches ni chung 1 cc

n bit chn knh => 2n knh, 1 trong s 2n knh cchn trong 1 thi im.

Chc nng MUX v DeMUX

C tn hiu Inhibit - cm tt c cc knh

Bin tn hiu: Vss thng dng mch follower loi tr Ron

ICs: CD 4051, 74HC4051 (TI), DG508A, 509A (Maxim)

6.2.2. analog switch & multiplexer: b.MUX

Ch6 Analog 36

L cc vi mch (super zener) to ra cc in p c nnh cao theo thi gian v theo nhit mi trng

Gi tr in p theo thp phn (2,5 / 5/ 10,00Vdc) hay nhphn (5,12/ 10,24Vdc)

H s tri: 30..50 ppm/OC

Cng thc chuyn i A/D v D/A n bit:

bn-12n-1 + bn-22n-2 + ... + b121 + b020

Uanalog Uref ()2n

Cc vi mch: LH0070, LM199s, LM136s (NS)

6.2.3. voltage reference - uref


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Ch6 Analog 37

Trch mu ca tn hiu vo thi im cui ca xung

Sample v gi nguyn gi tr trong khong thi gianlu hn.

Dng trong cc h thu thp s liu khi tc binthin tn hiu cao (tng i) vi thi gian ADC chuyni

Thu hp ca s bt nh ca ADC - do thi gianchuyn i di (10s s - ms) thnh ca s bt nh caS&H (10s ns..s) => nng cao chnh xc chuyn iA/D v nng cao tn s tn hiu.

Thi gian trch mu: vi chc ns n vi s T gi (Chold): dng t c dng r rt nh

Tc st p: mV/s, tu thuc t

Guard Ring: k thut ch to mch gim thiu dng r

6.2.4. Sample & Hold (trch mu & gi)

Ch6 Analog 38

Hnh 6.08. Symbolic Sample & Hold

ICs: LF189s (NS); AD585 (Analog Device Inc.)


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Ch6 Analog 39

Ch6 Analog 40

Hnh 6.09. Biu chuyn i tn hiu w/o [w] S&H


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Ch6 Analog 41

C tn hiu u(t). nh: im t1 => mu A1; t2 => mu

A2... khi khi phc li s c ng cong gn ng ving ban u, ty thuc mt ca mu.

Thc t:

t1 => start ADC, t1+ c tn hiu EOC => mu thuc A*1 t2 => start ... mu A*2 ... khi khi phc c ngcong khc.

Tc tn hiu bin thin cng ln => sai s

Dng S&H:

t1=> sample, start ADC, t2 => sample, start ADC...

Ch6 Analog 42

Hnh 6.10. Tnh tn s hnh sin vi DAC 574

Case study: u(t)= 5+5*sin(t+) (V). ADC 12bit, 35sconverssion time, U(ref) = 10,24V. Sai s lng t = 1/2ULSB . Hi tn s tn hiu max - khng sai trong 2 trnghp w - w/o S&H. Sample time=100ns


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Ch6 Analog 43

Ch6 Analog 44

Sai s tuyt i gia gi tro v gi tr thc xx = x x*

Sai s tng i: % = (x/x) x 100

Sai s do sensor: Sai s c tnh h thng:

Do nguyn l ca sensor,

Chun thang, x l kt quo

Sai s ngu nhin: Do tn hiu nhiu ngu nhin, nh hng ca mi trng

6.2.5. Cc sai s chuyn i


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Ch6 Analog 45

Ch6 Analog 46

Sai s lng t: do vic ri rc ha tn hiu => lytrung bnh, loi tr bt

Sai s do mch chun ha (conditioner) analog:

Zero Err, offset, cng => potentiometer/ software,

Full Scale Err, nhn gain, => pot./ software

Ngun chun Uref Ngun cp, ...

Tn hiu bin thin nhanh

Tn s ly mu tha/chm. RefK thut o lng- Prof. Dr. Phm Thng Hn

6.2.5. cc sai s chuyn i


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Ch6 Analog 47

Phng php 3 sigma (3)

loi tr sai s th bo Ti 1 gi tr, vi n ln o, thu

c 1 b s x, k vng tonhc ca b so l:

Phng sai:

Gi tr o x* c coi l tincy, nu ly: 2, chnh xc rt cao

3, chnh xc cao

Ngoi 3 : xc sut t, sai s ln=> b

Ch6 Analog 48

6.3. DAC - Digital to Analog Convertors

6.3.1. Khi nim: Digital to Analog: s => tn hiu dng in/in p,

lin tc v thi gian, ri rc v gi tr. Phn loi:

Cng ngh ch to, s bit (reslution), Thi gian c 10s ns .. 100s ns, Cu trc: Built-in latched ghp ni trc tip vi bus

/unlatched cn c out-port, bus 8 hay 16 bit Signed in p ra 2 du hoc unsnigned in p ra 1

du.


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Ch6 Analog 49

ng dng:

+ Tng hp tn hiu:- n Organ,- Functional Generators, pht tn hiu chun- Voice Chip,

+ VGA/SVGA: RAM-DAC+ Ti to: m thanh s, MP3, CD, KaraOke...+ Ghp ni gia h thng s (PC, PLC...) => biu khin analog, to ra cc SET-POINT+ B nhn tn hiu analog - 4 gc: nhn h s viU(in) thay cho UREF

Ch6 Analog 50


6.3.2. Nguyn l

cu trc vHot ng

(hnh 6.15)

Hnh 6.15. Nguyn l DAC


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Ch6 Analog 51


6.3.3. R-2R Ladder DAC: Xem hnh 6.16.

L phng php dng li in trR-2Rchia cy nh phn dng in.

n gin, chnh xc cao, nhanh

R

Trn th trng dng phng php ny.

Ch6 Analog 52

Hnh 6.16. R-2R ladder DAC with i/u converter

- Khi bi = 0 or 1 => ki R or L, Non Inv. Inp of OpAmp grounded =>Inv. Inp = #0V => ki lun ng xung t bt k bi = x

- Mng R-2R ni kiu cy nh phn.


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Ch6 Analog 53

6.3.4. Ghp ni DAC vi h VXL: Xem DAC loi g: 8/10/12 bit; signed/unsigned,

latched/unlatched, Uref? data bus: 8/16 bit? Tn s tn

hiu? Hnh 6.17. V d v single pole DAC, unltched

Thit b bao gm: port //, DAC v KTT (OpAmp) bin i i=> u, Ngun chun,

DAC0808: 8 bit unlatched input => dng latch bn ngoi, 100ns,n du, 16 pin DIP, r tin v d ghp ni.

Cng // c th l (***) LPT, mode 0, nu ghp ni vi PC hoc ISA bus PPI 8255 (h. 5.3) hoc b cht 8 bit c gii m a ch (h.5.2a) hoc Vi iu khin c latched outport.

Options: built in latched DAC: DAC0832, l DAC0808 +

latch => ghp trc tip vi data bus; DAC1210 12 bit,ghp vi bus 8/16 bit bus interface directly Theo hnh 6.17, nu R1=R2=(R3+RPOT) th tha CT *

Ch6 Analog 54

=========================================bn-12n-1+ bn-22n-2+...+ b121+ b020

UOUT = --------------------------------------- UREF2n

=========================================

UOUT = - iO * RFEETBACK=> UOUT = - iO * RR3+Rpot

Nu mun thay i di gi tr Analog Out (Output

range) th thay i (R3+RPOT). V d: UREF=5,12V, cn UOUT =0...10,20V, th gi tr Rs =?

POT: potentiometer chit p


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Ch6 Analog 55Hnh 6.17. Interfacing to DAC

Ch6 Analog 56

Cc v d to in p analog: /v H 6.17n = 8 bit, UREF = 10,24Volt (gi s) b(i) = 0s, all => UOUT= 0V

b(0) = 1, (!) => UOUT=ULSB= (1/2n)*UREF= 0.04V (TVDN), phn ly ca DAC resolution/threshold, l kh nng toin p nh nht, hoc hiu ca 2 gi tr lin tip nhau

...

b(n-1) = 1 (!) => UOUT= (2n-1/2n) UREF= 5.12V, (TVDN) HalfScale, na thang o.

...

b(i) = 1s (all) => UOUT = ((2n-1)/2n) UREF= (255/256) UREF

(TVDN) = 10.20V, Full Scale

Output Voltage = 0 10.20 Volt.


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Ch6 Analog 57

V d 1: vi UOUT=0...10,20V, to /p 9,23V: V chuyn i l tuyn tnh, in p ny bng bao nhiu

ln /p ULSB,, viAmpll bin kiu byte.Ampl := Round(9.23/0.04); {= 230,75 lm trn = 231}

Port[dac]:=231; {in p bng? 9,24V}

V d 2: to 5,26VPort[dac]:= Round(5.26/0.04); {131,5 => 132}

Ch : v output ports, latches... l 8/10/12 bit => khi Out ra, s

liu phi l snguyn, mc d in p l sthc v ktqu php chia l sthc => phi dng php lm trn

trc Dln gia bin in p sthc v snguyn t/!

Ch6 Analog 58

Th tc to n chu k xung ch nht c bin in p l U0

=2.34V v U1 = 7.45V , thi gian t0 v t1(Hnh 6.18-a). A0 vA1 l 2 bin nguyn kiu byte, t0 =2ms v t1=1ms (bin nguyn).A0:= Round(2.34/0.04); {A0 v A1 l bin kiu byte}A1:= Round(7.45/0.04);

For i:= 1 to n do

Begin

Port[dac]:= A1; delay (t1);

Port[dac]:= A0; delay (t0);

End;

Pht xung vung a mc, sine (vi s mu cho trc), rng ca,tam gic...

Kt hp: ch nht vi sine, rng ca vi ... tn hiu vi bin thay i c (Pht iu ch), tn s thay i c, rng thayi c

Ch :nu cc sliu lp li nhiu ln => lm trn ngoi vnglp khinh hngn thi gian tr.


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Ch6 Analog 59

Hnh 6.18. Mt sdng tn hiu cbn

Ch6 Analog 60

To tn hiu hnh sin: ly n+1 mu

For i:= 0 to n doAA[i] : = Round(Truc_gia + (Um/Ulsb * sin

(2*pi*i/n)));

Vi : AA[i]l bin mng c n+1 phn t kiu byte Truc_gia l gi tr cng thm vo hnh sin tn hiu ra

khng c phn m, dng cho cc DAC n du (singlepolar), khng to c in p m. Thng gn gi tr bngna thang. TVDN l 128 - ng vi U=5.12V

Ampll bin ca hnh sin, theo u bi cho, khng ln

hn 5,08VKhi pht: theo yu cu: 1 dy m chu k hoc pht

lin tc theo 1 iu kin no hoc nhiu chu k ca1 phn hnh sin


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Ch6 Analog 61

Pht m chu k hnh sin:

For j:= 1 to m do

For i:= 0 to n-1 do

Begin {pht 1 chu k}

Port[dac]:= AA[i];

Delay (t) {t - khong tg gia 2 mu}End;

Port[dac]:= AA[n];

Ch6 Analog 62

Mch pht in p mu, dn Chun ha v In mch ng hodng, p xoay chiu: Vi iu khin ATmega32, EPROM v DAC1210


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Ch6 Analog 63

Hnh 6.19. Mt s dng sng iu ch

Ch6 Analog 64

PH LC:Application Hint How to delay @ us:PIT 8254 (Programmable Interval Timer) 3 T/Cs. TC0dng Sys. Timer: 18.2Hz.Cc bm v timer l 16 bit, count downInput Clock: 14.31818MHz/3 = 4,77MHz

4.77MHz/4 [2] = 1.19[2.38MHz] T/C0: mode0, divisor 65536 => 55ms pht 1 xung =>IRQ0 system timer interrupt T/C1: Mode0, divisor 18 => lm ti DRAM

T/C2: Mode0, divisor thay i to m thanh cho PCspeaker.Cc my tnh c Clock In 1.19MHz or 2.38 MHz. PPkim tra?


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Ch6 Analog 65

Asm

mov al,0

out 43h,al ; latch T/C0

in al, 40h

xchg ah, al

in al, 40h

xchg ah, al

mov t1, ax ; t, t1, t2 ~ word typed

Call delay(1) ; tr 1 msmov al,0

out 43h,al ; latch T/C0

in al, 40h

xchg ah, al

in al, 40h

xchg ah, almov t2, ax ;

End;

Ch6 Analog 66

If t1>t2 then t:= Round((t1-t2)/1.19)

Else t:=Round((t1+65536-t2)/1.19);

Writeln(t);

{Nu t=1001 => fclock = 1.19MHz; t=2002 => fclock =2.38MHz }

How do delay 15s? surpose that fCLOCK= 2.38636MHz, ( from ((14.31818/3)/2)

=> 1 count # 0.419 s => 15s # 36 counts - rounded

STEP LIST:

1. Cm ngt, tt2. Get t1,3. Repeat get t2 Until t2 < = t1-36

4. Stop

5. Cho php ngt


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Ch6 Analog 67

6.3.5. THAM KHO: (y/c bnh thng /v CQ)

Tra cu cc vi mch DAC: (pdf files v AN)www.national.com/product/interface/ad-da DAC0808 - single pole, 8 bit, 100ns

DAC0800 - signed voltage output, 8 bit, 100ns

DAC0832 - latched 8 bit dac - bus interface directly,

DAC1210 - latched 12 bit dac 8/16 bit bus

interface directly, 200ns

Ch6 Analog 68

6.3.6. Bi tp: pht hm vi cc to dac8bit/12bit/du: + Squarewave: (A0-t0, A1-t1) + Multi-Level Squarewave: (A0-t0, A1-t1, A2-

t2...) + SawTeeth / or \ : Samples/Cycle + Tri-Angle: Samples/Slope + Sine: Spc, a sector of sinous cycle: Spc? + Multi wave form

+ Random. + Cc bi trn c iu ch tn hiu bin , tn s, rng


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Ch6 Analog 69

6.4. ADC: Analog to Digital Convertors

6.4.1. Khi nim:

L thit bc 2 chc nng: Ri rc ha tn hiu v thi gian

S ha tn hiu v bin =>Lng t ha

Phn loi: Theo ng dng: ADCxl th v o

Chuyn i gin tip: u(t) => time (ilng trung gian) => code

Chuyn i trc tip: u(t) => code

Chuyn i phi tuyn: CODEC (TP3057 -Mitel hay AC97 Intel)

...

Ch6 Analog 70

Chuyn i gin tip: tch phn 2 sn dc u(t) => Time Interval/f/T => code

Chm, r tin ($s), phn ly v chnh xc cao

Dng cho o lng, thu thp s liu trong cngnghip... khng cn nhanh, loi c nhiu

Chuyn i trc tip: u(t) => code Nhanh, phn ly thp hn [t tin], dng thu

thp v x l tn hiu bin thin nhanh

Chuyn i kiu xp x lin tip:10k..10MSps Chuyn i song song: 10M..500 MSps


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Ch6 Analog 71

6.4.2. nh l ly mu Shannon - Kochennicov:

Pht biu:

Tn hiu u(t) lin tc, trong n c cha thnhphn fMAX, (nng lng ca tn hiu fMAX =0)th c th khi phc li tn hiu khng b sai tnhng gi tr gin on, vi iu kin:

fSAMPLE >= 2fMAX

Ch6 Analog 72

Comment: Not for sinous signals. i vi sinous signals,

phi c 10..100 Spc (Samples per Cycle) What is fMAX ?

Thnh phn bc cao nht , W(fMAX) = 0 s khi phctn hiu khng sai.

Lc b thnh phn bc cao. V din thoi s: LPFvi fCUT = 4kHz => 8kSps (64 kbps - PCM, A lawhoc Law).

nh l ny c tnh php l. cho k s hiu s mu ti thiu bao nhiu l

, khng dy qu => trnh lng ph (tc ADC, thi gian x l, b nh) ; ly tha th tito s b sai.


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Ch6 Analog 73

6.4.3. Chuyn i gin tip: Hnh s 6.20. Tch phn 2 sn dc - Dual SlopeIntegration ADC:c im:

Chm, hng chc..hng trm ms - converssion time

Loi bc nhiu li cng nghip (50/60 Hz)

R, phn li cao, chnh xc cao, nu Internal Refv clock th t hn

=> Dng o lng, thu thp s liu trong cngnghip

Ch6 Analog 74

V d ICs: ICL 7107, 15..17k,

In: -2V..2V, Out: -1999 => 1999, 4.000 counts 12 bit,

LED 7 Seg drive directly w current soursers for display

Converssion time: 20..40ms

ICL 7135, 25..30k, Inp: -0.2V +02.V hoc -2V..+2V, Out: -19999

=>+19999, 40.000 count > 15bit, 400 ms converssion time

De-Multiplexed Out BCD for 5 digits of 7 Seg, scanned

ICL 7109, 120k, w REF & Clock Inp: -2V..+2V, Out: 12 bin + pole, 8/16 bit interface to CS


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Ch6 Analog 75

Hnh 6.20. Dual Slope Integration ADC

Ch6 Analog 76

Nguyn l cu trc: hnh 6.20 UIN: in p cn chuyn i, Switch: SPTT, chuyn mch theo cc phase hot ng.

1 t2 Integrator: Ua = - ----- (UINdt)

RICI t1

AC: Analog Comparator: V+ > V- => Out = 1V+ < V- => Out = 0

Ch : khng c khi nim V+=V- B "o du" UREF, v d: UREF= -1,000 Volt khi UIN > 0 V

UREF= +1,000 Volt khi UIN < 0 V

Timing-Control: iu khin hot ng ca ADC Counter: m thi gian (t3-t2), bin/BCD Output Latch: cht s liu ra: 7seg/bcd/bin; [3state] ghp

ni bus trc tip, c tn hiu Hi/Low byte enable


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Ch6 Analog 77

Hotng: Chia thnh 3 phase, Free Run, khngcn CS khi ng. CS c th HOLD/RUN

Zeroing Phase: (0.. t1) K1 => grounded, K2, K3 closed => kh bin p d

trn cc phn t (tare - tr b)

Integrating Phase: (t1=>t2) K1=> U IN, K2, K3 Opened

1 t2

Ua(t2) = - ----- (UIN dt) + Ua(t1)R

IC

I

t1

Tuy nhin, Ua(t1) c qui zero trc .

Ch6 Analog 78

De-integration Phase: (t2=>t3), K1 => "-UREF", K2,K3 Opened

1 t3

Ua(t3) = - ----- (-UREF dt) + Ua(t2) = 0RICI t2

t2 t3

UIN dt = UREF dtt1 t2

UIN ~ (t3-t2)

UIN* = k (t3 - t2);vi UIN* l trung bnh tch phn ca UIN t t1 => t2


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Ch6 Analog 79

d. C trc tip: ngl xp x lin tip - SuccessiveApproximation ADC:

c im: Nhanh: Vi trm ns - 100 s

Input: 0..5V, -5..+5V, -10..+10V (cao, K nhiu)

Digital Out: 3state, Binary, bus interface directly

Thng x l tn hiu bin thin nhanh: m thanh, voice,radar, x l nh ...

[t tin hn]: 12 bit-10 s @ 20US$ - $40, AD7914,Analog Device Inc. 10bit, 1MSps, 4 Channel Inp, Serial Out,Ext Ref & Clock ($5 each package 500pcs)

Gi thnh cn ph thuc Internal/External Clock and/orReference.

Ch6 Analog 80

Nguyn l cu trc: (Hnh 6.22) SAR: Successive Approximation Register: l 1sequenceriu khin hot ng ca ADC,

Inp.: clock v AC out = 1/0;

Outp. l Qi c to ra, qua b DAC thm d, so vigi tr vo UIN. Vic thm d theo nguyn l cy nhphn.

DAC v UREF: To in p mu so vi UIN AC: Analog Comparator, so snh UIN v UDAC-OUT,

khng c kt qu bng nhau. 3 state buffer: Hi-Z ghp vi bus khi khng c

chn. Khi c chn, t hp -CS = 0 v -IOR = 0.Ghp trc tip vi bus


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Ch6 Analog 81

Hnh 6.22. Nguyn l cu trc v hot ng ca SA ADC

Ch6 Analog 82

Hotng: n bit => c n steps. Mi chu k chuyn i u do CPU khi ng hoc Free

Run, chuyn i xong bo tn hiu EOC (End OfConverssion) hoc status

Start ADC: mov dx, adc_portout dx, al ; don't care al, -CS=0 v -IOW = 0

hoc Pascal:port[adc_port]:=a12; {a12 l bin/hng bt k}

Khng quan tm al = ?, ch cn a ch => -CS v -IOW =>

s -start ADC). Sau starting, SAR bt u hot ng: Theo hnh 6.22 v cng thc chuyn i.


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Ch6 Analog 83

Hot ng l do SARiu khin:

Step 1: Qn-1= 1 (only), (Ch : Qi thay cho bitrong cng thc C)

Ua= (2n-1/2n) UREF< UIN => GN Qn-1TVDN

Step 2: GN Qn-1, set Qn-2=1, remainders = 0s

Ua= ((2n-1 + 2n-2)/2n) UREF> UIN => reset Qn-2TVDN

Step 3: GN Qn-1, Qn-2, set Qn-3 = 1, rems = 0s

Ua= ((2n-1

+ 2n-3

)/2n

) UREF< UIN => GN Qn-3=1TVDN

Ch6 Analog 84

Step 4, 5...

Step n:...

UIN Ua (analog comparator) =>Approximation


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Ch6 Analog 87Hnh 6.21. Interfacing to the ICL - 7135 ADC

Ch6 Analog 88Hnh 6.23. Interfacing to the ADC 0809

www.nselectronics.com/product/interface/ad-da


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Ch6 Analog 89

ADC0809 National Semiconductor ADC 8 bit, 8 Analog Input Channels, selected by

3 addr bit A2, A1, A0

Conversion time 100s @ clock freq.=640kHz

05V Analog Input Volt.; Ref. Volt 5.00V

Signals/Pins: 8 data bit out - 01 EOC =

01 start = - Stobe =

ALE = latch address

C th ni STROBE vi ALE, gim t/h /k

Ch6 Analog 90

Operation: Channel Select: 000 111, 1 of 8 channel

selected

Starting: set start = , delay #3s

Delay 110 s, waiting for ADC converting orpoll EOC for or IRQ

Set Strobe = to open 3 state output gate,

reading data

ADC0809 National Semiconductor


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Ch6 Analog 91

Hnh 6.25. Timing diagram of ADC 0809

Ch6 Analog 92

Hnh 6.26. AD 574/AD1674: 8/12 bit, 35us/10us,

Int. Clk & Ref. Volt.


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Ch6 Analog 93

Ch6 Analog 94

6.4.6. Multi I/O card:Hnh 6.27

Dng 01 PPI8255, 01 DAC n bit + OpAmp,01 analog comparator, 01 analog MUX to: 01 Analog Out channel (8/12 bit)

8 channels of analog Input (range ~ dac out)theo nguyn l counting hay xp x lin tip

Digital Inputs (TTL), c th thm b cch lyquang hc,

Digital Outputs, c th c relay_out


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Ch6 Analog 95

Hnh 6.27. Multi IO card: DI/ DO/ AI/ AO

Ch6 Analog 96

6.4.7. THAM KHO (Y/c bnh thng /vCQ)

ADC 0809/0816: 8/16 input channels of0..5V, 8bit, 100s

ADC0800 (MM5357 Motorola) 8bit, 40s

AD 574/AD1674, AnalogDevice, 12bit,35/10s, AD7914...

Nng cao: CODEC TP3057, AC97...

AD7914, ADC124S101CIMM ($2.21)


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Ch6 Analog 97

Ch6 Analog 98


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Ch6 Analog 99

Ch6 Analog 100


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Ch6 Analog 101

Ghp ni DAC: DAC 0800/8; DAC1210 (12 bit) vi hVXL bt k (ISA bus, LPT, Micro Controllers...) to inp analog, to cc hm

ADC tch phn 2 sn: ICL7109/ ICL7135...

SA ADCs: ADC0800/4; ADC 0808/9; AD574/AD1674 ,adi.com (Analog Device Inc. adi.com)

Serial ADC, 5V, 100k - 10 MSps ghp vi FPGA(www.national.com, Analog Devices www.analog.com)

bi tp chng 6

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