George Mason University ECE 448 – FPGA and ASIC Design with VHDL Data Flow Modeling of Combinational Logic Simple Testbenches ECE 448 Lecture 3.

George Mason University ECE 448 – FPGA and ASIC Design with VHDL

Data Flow Modeling of

Combinational Logic

Simple Testbenches

ECE 448Lecture 3

2 ECE 448 – FPGA and ASIC Design with VHDL

Required reading

• S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design

Chapter 6, Combinational-Circuit Building

Blocks (sections 6.6.5-6.6.7 optional)

Chapter 5.5, Design of Arithmetic Circuits

Using CAD Tools


Optional Reading

• Sundar Rajan, Essential VHDL: RTL Synthesis

Done Right

Chapter 3, Gates, Decoders and Encoders (see errata at http://www.vahana.com/bugs.htm)


Recommended reading

• S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design

Chapter 7, Flip-Flops, Registers, Counters,

and a Simple Processor

(7.14 optional)

Material covered next week

and required during the second lab experiment


VHDL Design Styles


VHDL Design Styles

Components andinterconnects

structural

VHDL Design Styles

dataflow

Concurrent statements

behavioral

• Registers• State machines

Sequential statements

Subset most suitable for synthesis

• Testbenches


xor3 Example


Entity xor3

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY xor3 IS

PORT(

A : IN STD_LOGIC;

B : IN STD_LOGIC;

C : IN STD_LOGIC;

Result : OUT STD_LOGIC

);

end xor3 ;


Dataflow Architecture (xor3 gate)

ARCHITECTURE dataflow OF xor3 ISSIGNAL U1_OUT: STD_LOGIC;BEGIN

U1_OUT <= A XOR B;Result <= U1_OUT XOR C;

END dataflow;

U1_OUT


Dataflow Description

• Describes how data moves through the system and the various processing steps.

• Data Flow uses series of concurrent statements to realize logic. Concurrent statements are evaluated at the same time; thus, order of these statements doesn’t matter.

• Data Flow is most useful style when series of Boolean equations can represent a logic.


Structural Architecture (xor3 gate)

ARCHITECTURE structural OF xor3 ISSIGNAL U1_OUT: STD_LOGIC;

COMPONENT xor2 PORT(

I1 : IN STD_LOGIC; I2 : IN STD_LOGIC; Y : OUT STD_LOGIC

);END COMPONENT;

BEGINU1: xor2 PORT MAP (I1 => A,

I2 => B, Y => U1_OUT);

U2: xor2 PORT MAP (I1 => U1_OUT,

I2 => C, Y => Result);

END structural;

A

B

C

Resultxor3

I1

I2Y I1

I2Y

U1_OUT


xor2

LIBRARY ieee;USE ieee.std_logic_1164.all;

ENTITY xor2 ISPORT( I1 : IN STD_LOGIC;

I2 : IN STD_LOGIC; Y : OUT STD_LOGIC);

END xor2;

ARCHITECTURE dataflow OF xor2 ISBEGIN

Y <= I1 xor I2;END dataflow;

xor2.vhd


Structural Description

• Structural design is the simplest to understand. This style is the closest to schematic capture and utilizes simple building blocks to compose logic functions.

• Components are interconnected in a hierarchical manner.

• Structural descriptions may connect simple gates or complex, abstract components.

• Structural style is useful when expressing a design that is naturally composed of sub-blocks.


Behavioral Architecture (xor3 gate)

ARCHITECTURE behavioral OF xor3 ISBEGINxor3_behave: PROCESS (A,B,C)BEGIN

IF ((A XOR B XOR C) = '1') THENResult <= '1';

ELSEResult <= '0';

END IF;END PROCESS xor3_behave;END behavioral;


Behavioral Description

• It accurately models what happens on the inputs and outputs of the black box (no matter what is inside and how it works).

• This style uses PROCESS statements in VHDL.


Describing

Combinational Logic

Using

Dataflow Design Style


Register Transfer Level (RTL) Design Description

Combinational Logic

Combinational Logic

Registers

…

Today’s Topic


VHDL Design Styles


structural

VHDL Design Styles

dataflow


behavioral

• Registers• State machines


Subset most suitable for synthesis

• Testbenches


Synthesizable VHDL

Dataflow VHDL

Design Style

VHDL code

synthesizable

VHDL code

synthesizable

Dataflow VHDL

Design Style


Data-flow VHDL

• concurrent signal assignment ()• conditional concurrent signal assignment (when-else)• selected concurrent signal assignment (with-select-when)• generate scheme for equations (for-generate)

Major instructions



Data-flow VHDL


Major instructions



Data-flow VHDL: Example

0 0 0 1 0 1 1 1

c i 1 +

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

c i x i y i

00 01 11 10

0

1

x i y i c i

1

1

1

1

s i x i y i c i =

00 01 11 10

0

1

x i y i c i

1

1 1 1

c i 1 + x i y i x i c i y i c i + + =

c i

x i

y i s i

c i 1 +

(a) Truth table

(b) Karnaugh maps

(c) Circuit

0 1 1 0 1 0 0 1

s i


Data-flow VHDL: Example (1)

LIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY fulladd ISPORT ( x : IN STD_LOGIC ;

y : IN STD_LOGIC ; cin : IN STD_LOGIC ;

s : OUT STD_LOGIC ; cout : OUT STD_LOGIC ) ;END fulladd ;


Data-flow VHDL: Example (2)

ARCHITECTURE dataflow OF fulladd ISBEGIN

s <= x XOR y XOR cin ;cout <= (x AND y) OR (cin AND x) OR (cin AND y) ;

END dataflow ;


Logic Operators

• Logic operators

• Logic operators precedence

and or nand nor xor not xnor

notand or nand nor xor xnor

Highest

Lowest

only in VHDL-93


Wanted: y = ab + cdIncorrecty <= a and b or c and d ; equivalent toy <= ((a and b) or c) and d ;equivalent toy = (ab + c)d

Correcty <= (a and b) or (c and d) ;

No Implied Precedence


Arithmetic Operators in VHDL (1)

To use basic arithmetic operations involving

std_logic_vectors you need to include the

following library packages:

LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_unsigned.all;orUSE ieee.std_logic_signed.all;


Arithmetic Operators in VHDL (2)

You can use standard +, -, * operators

to perform addition and subtraction:

signal A : STD_LOGIC_VECTOR(3 downto 0); signal B : STD_LOGIC_VECTOR(3 downto 0); signal C : STD_LOGIC_VECTOR(3 downto 0);

……

C <= A + B;


16-bit Unsigned Adder

16 16

X Y

16

CinCoutS


VHDL code for a 16-bit Unsigned Adder

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_unsigned.all ;

ENTITY adder16 ISPORT ( Cin : IN STD_LOGIC ;

X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ;S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ;Cout : OUT STD_LOGIC ) ;

END adder16 ;

ARCHITECTURE dataflow OF adder16 IS SIGNAL Sum : STD_LOGIC_VECTOR(16 DOWNTO 0) ;

BEGINSum <= ('0' & X) + Y + Cin ;S <= Sum(15 DOWNTO 0) ;Cout <= Sum(16) ;

END dataflow ;


Data-flow VHDL


Major instructions



Conditional concurrent signal assignment

target_signal <= value1 when condition1 else value2 when condition2 else . . . valueN-1 when conditionN-1 else valueN;

When - Else


Most often implied structure

target_signal <= value1 when condition1 else value2 when condition2 else . . . valueN-1 when conditionN-1 else valueN;

When - Else

.…Value N

Value N-1

Condition N-1

Condition 2

Condition 1

Value 2

Value 1

Target Signal

…0

1

0

1

0

1


Operators

• Relational operators

• Logic and relational operators precedence

= /= < <= > >=

not= /= < <= > >=and or nand nor xor xnor

Highest

Lowest


compare a = bc

Incorrect

… when a = b and c else …

equivalent to

… when (a = b) and c else …

Correct

… when a = (b and c) else …

Priority of logic and relational operators


VHDL operators


2-to-1 Multiplexer

(a) Graphical symbol

f

s

w0

w1

0

1

(b) Truth table

0

1

fs

w0

w1


VHDL code for a 2-to-1 Multiplexer


ENTITY mux2to1 ISPORT ( w0, w1, s : IN STD_LOGIC ;

f : OUT STD_LOGIC ) ;END mux2to1 ;

ARCHITECTURE dataflow OF mux2to1 ISBEGIN

f <= w0 WHEN s = '0' ELSE w1 ;END dataflow ;


Cascade of two multiplexers

s1

w3

w1

0

1

s2

w2

0

1 y


VHDL code for a cascade of two multiplexers


ENTITY mux_cascade ISPORT ( w1, w2, w3: IN STD_LOGIC ;

s1, s2 : IN STD_LOGIC ;f : OUT STD_LOGIC ) ;

END mux_cascade ;


f <= w1 WHEN s1 = ‘1' ELSE w2 WHEN s2 = ‘1’ ELSE w3 ;END dataflow ;


conditional concurrent signal assignment (when-else)

Other examples of use of


Tri-state Buffer – example (1)

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY tri_state IS

PORT ( ena: IN STD_LOGIC;

input: IN STD_LOGIC;

output: OUT STD_LOGIC

);

END tri_state;


Tri-state Buffer – example (2)

ARCHITECTURE dataflow OF tri_state IS

BEGIN

output <= input WHEN (ena = ‘0’) ELSE ‘Z’;

END dataflow;


4-bit Number Comparator

4

4

A

B

AeqB

AgtB

AltB


VHDL code for a 4-bit Unsigned Number Comparator

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_unsigned.all ;

ENTITY compare ISPORT ( A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;

AeqB, AgtB, AltB : OUT STD_LOGIC ) ;END compare ;

ARCHITECTURE dataflow OF compare ISBEGIN

AeqB <= '1' WHEN A = B ELSE '0' ;AgtB <= '1' WHEN A > B ELSE '0' ;AltB <= '1' WHEN A < B ELSE '0' ;

END dataflow ;


VHDL code for a 4-bit Signed Number Comparator

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_signed.all ;

ENTITY compare ISPORT ( A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;

AeqB, AgtB, AltB : OUT STD_LOGIC ) ;END compare ;

ARCHITECTURE dataflow OF compare ISBEGIN

AeqB <= '1' WHEN A = B ELSE '0' ;AgtB <= '1' WHEN A > B ELSE '0' ;AltB <= '1' WHEN A < B ELSE '0' ;

END dataflow ;


Priority Encoder

w 0

w 3

y 0

y 1

d001

010

w0 y1

d

y0

1 1

01

1

11

z

1xx

0

x

w1

01x

0

x

w2

001

0

x

w3

000

0

1

z

w 1

w 2


VHDL code for a Priority Encoder


ENTITY priority ISPORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;

y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;z : OUT STD_LOGIC ) ;

END priority ;

ARCHITECTURE dataflow OF priority ISBEGIN

y <= "11" WHEN w(3) = '1' ELSE "10" WHEN w(2) = '1' ELSE"01" WHEN w(1) = '1' ELSE"00" ;

z <= '0' WHEN w = "0000" ELSE '1' ;END dataflow ;


Data-flow VHDL


Major instructions



Selected concurrent signal assignment

with choice_expression select target_signal <= expression1 when choices_1, expression2 when choices_2, . . . expressionN when choices_N;

With –Select-When


Most Often Implied Structure

with choice_expression select target_signal <= expression1 when choices_1, expression2 when choices_2, . . . expressionN when choices_N;

With –Select-When

choices_1

choices_2

choices_N

expression1

target_signal

choice expression

expression2

expressionN


Allowed formats of choices_k

WHEN value

WHEN value_1 | value_2 | .... | value N

WHEN OTHERS


Allowed formats of choice_k - example

WITH sel SELECT

y <= a WHEN "000",

c WHEN "001" | "111",

d WHEN OTHERS;


f

s 1

w 0

w 1

00

01

(b) Truth table

w 0

w 1

s 0

w 2

w 3

10

11

0

0

1

1

1

0

1

f s 1

0

s 0

w 2

w 3

(a) Graphic symbol

4-to-1 Multiplexer


VHDL code for a 4-to-1 Multiplexer


ENTITY mux4to1 ISPORT ( w0, w1, w2, w3 : IN STD_LOGIC ;

s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;f : OUT STD_LOGIC ) ;

END mux4to1 ;


WITH s SELECTf <= w0 WHEN "00",

w1 WHEN "01",w2 WHEN "10",w3 WHEN OTHERS ;

END dataflow ;


selected concurrent signal assignment (with-select-when)

Other examples of use of


2-to-4 Decoder

0

0

1

1

1

0

1

y 0

w 1

0

w 0

x x

1

1

0

1

1

En

0

0

0

1

0

y 1

1

0

0

0

0

y 2

0

1

0

0

0

y 3

0

0

1

0

0

w 0

En

y 0

w 1

y 1

y 2

y 3

(a) Truth table (b) Graphical symbol


VHDL code for a 2-to-4 Decoder


ENTITY dec2to4 ISPORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;

En : IN STD_LOGIC ;y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ;

END dec2to4 ;

ARCHITECTURE dataflow OF dec2to4 ISSIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ;

BEGINEnw <= En & w ;WITH Enw SELECT

y <= "1000" WHEN "100","0100" WHEN "101","0010" WHEN "110","0001" WHEN "111","0000" WHEN OTHERS ;

END dataflow ;


MLU Example


MLU: Block Diagram

B

A

NEG_A

NEG_B

IN0

IN1

IN2

IN3 OUTPUT

SEL1

SEL0

MUX_4_1

L0L1

NEG_Y

Y

Y1

A1

B1

MUX_0

MUX_1

MUX_2

MUX_3


MLU: Entity Declaration

LIBRARY ieee;USE ieee.std_logic_1164.all;

ENTITY mlu IS PORT(

NEG_A : IN STD_LOGIC; NEG_B : IN STD_LOGIC; NEG_Y : IN STD_LOGIC; A : IN STD_LOGIC; B : IN STD_LOGIC; L1 : IN STD_LOGIC; L0 : IN STD_LOGIC; Y : OUT STD_LOGIC

);END mlu;


MLU: Architecture Declarative Section

ARCHITECTURE mlu_dataflow OF mlu IS

SIGNAL A1 : STD_LOGIC;SIGNAL B1 : STD_LOGIC;SIGNAL Y1 : STD_LOGIC;SIGNAL MUX_0 : STD_LOGIC;SIGNAL MUX_1 : STD_LOGIC;SIGNAL MUX_2 : STD_LOGIC;SIGNAL MUX_3 : STD_LOGIC;SIGNAL L: STD_LOGIC_VECTOR(1 DOWNTO 0);


MLU - Architecture BodyBEGIN

A1<= NOT A WHEN (NEG_A='1') ELSEA;

B1<= NOT B WHEN (NEG_B='1') ELSE B;

Y <= NOT Y1 WHEN (NEG_Y='1') ELSEY1;

MUX_0 <= A1 AND B1;MUX_1 <= A1 OR B1;MUX_2 <= A1 XOR B1;MUX_3 <= A1 XNOR B1;

L <= L1 & L0;

with (L) select Y1 <= MUX_0 WHEN "00",

MUX_1 WHEN "01", MUX_2 WHEN "10",

MUX_3 WHEN OTHERS;

END mlu_dataflow;


Behavioral Design Style

for Testbenches


VHDL Design Styles


structural

VHDL Design Styles

dataflow


behavioral

• Testbenches



• A process can be given a unique name using an optional LABEL

• This is followed by the keyword PROCESS

• The keyword BEGIN is used to indicate the start of the process

• All statements within the process are executed SEQUENTIALLY. Hence, order of statements is important.

• A process must end with the keywords END PROCESS.

TESTING: process begin

TEST_VECTOR<=“00”;wait for 10 ns;




end process;

• A process is a sequence of instructions referred to as sequential statements.

What is a PROCESS?

The Keyword PROCESS


Execution of statements in a PROCESS

• The execution of statements continues sequentially till the last statement in the process.

• After execution of the last statement, the control is again passed to the beginning of the process.

Testing: PROCESS BEGIN

test_vector<=“00”;WAIT FOR 10 ns;test_vector<=“01”;WAIT FOR 10 ns;test_vector<=“10”;WAIT FOR 10 ns;test_vector<=“11”;WAIT FOR 10 ns;

END PROCESS;O

rde

r o

f exe

cutio

nProgram control is passed to the

first statement after BEGIN


PROCESS with a WAIT Statement

• The last statement in the PROCESS is a WAIT instead of WAIT FOR 10 ns.

• This will cause the PROCESS to suspend indefinitely when the WAIT statement is executed.

• This form of WAIT can be used in a process included in a testbench when all possible combinations of inputs have been tested or a non-periodical signal has to be generated.

Testing: PROCESSBEGIN

test_vector<=“00”;WAIT FOR 10 ns;test_vector<=“01”;WAIT FOR 10 ns;test_vector<=“10”;WAIT FOR 10 ns;test_vector<=“11”;WAIT;

END PROCESS;

Program execution stops here

Ord

er

of e

xecu

tion


WAIT FOR vs. WAIT

WAIT FOR: waveform will keep repeating itself forever

WAIT : waveform will keep its state after the last wait instruction.

0 1 2 3

…

0 1 2 3 …


Simple

Testbenches


Generating selected values of one input

SIGNAL test_vector : STD_LOGIC_VECTOR(2 downto 0);

BEGIN

.......testing: PROCESS

BEGIN

test_vector <= "000";

WAIT FOR 10 ns;


WAIT FOR 10 ns;


WAIT FOR 10 ns;


WAIT FOR 10 ns;


WAIT FOR 10 ns;

END PROCESS;

........

END behavioral;


Generating all values of one input

SIGNAL test_vector : STD_LOGIC_VECTOR(3 downto 0):="0000";

BEGIN

.......

testing: PROCESS

BEGIN

WAIT FOR 10 ns;

test_vector <= test_vector + 1;

end process TESTING;

........

END behavioral;


SIGNAL test_ab : STD_LOGIC_VECTOR(1 downto 0);

SIGNAL test_sel : STD_LOGIC_VECTOR(1 downto 0);

BEGIN

.......

double_loop: PROCESSBEGIN

test_ab <="00";test_sel <="00";for I in 0 to 3 loop for J in 0 to 3 loop

wait for 10 ns;test_ab <= test_ab + 1;

end loop; test_sel <= test_sel + 1;end loop;

END PROCESS;

........

END behavioral;

Generating all possible values of two inputs


Generating periodical signals, such as clocks

CONSTANT clk1_period : TIME := 20 ns;

CONSTANT clk2_period : TIME := 200 ns;

SIGNAL clk1 : STD_LOGIC;

SIGNAL clk2 : STD_LOGIC := ‘0’;

BEGIN

.......

clk1_generator: PROCESS

clk1 <= ‘0’;

WAIT FOR clk1_period/2;

clk1 <= ‘1’;

WAIT FOR clk1_period/2;

END PROCESS;

clk2 <= not clk2 after clk2_period/2;

.......

END behavioral;


Generating one-time signals, such as resets

CONSTANT reset1_width : TIME := 100 ns;

CONSTANT reset2_width : TIME := 150 ns;

SIGNAL reset1 : STD_LOGIC;

SIGNAL reset2 : STD_LOGIC := ‘1’;

BEGIN

.......

reset1_generator: PROCESS

reset1 <= ‘1’;

WAIT FOR reset_width;

reset1 <= ‘0’;

WAIT;

END PROCESS;

reset2_generator: PROCESS

WAIT FOR reset_width;

reset2 <= ‘0’;

WAIT;

END PROCESS;

.......

END behavioral;


Typical error

SIGNAL test_vector : STD_LOGIC_VECTOR(2 downto 0);

SIGNAL reset : STD_LOGIC;

BEGIN

.......

generator1: PROCESS

reset <= ‘1’;

WAIT FOR 100 ns

reset <= ‘0’;

test_vector <="000";

WAIT;

END PROCESS;

generator2: PROCESS

WAIT FOR 200 ns


WAIT FOR 600 ns


END PROCESS;

.......

END behavioral;

George Mason University ECE 448 – FPGA and ASIC Design with VHDL Data Flow Modeling of Combinational Logic Simple Testbenches ECE 448 Lecture 3.

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