Gedae Portability: From Gedae Portability: From Simulation to DSPs to the Simulation to DSPs to the Cell Broadband Engine Cell Broadband Engine James Steed, William Lundgren, Kerry James Steed, William Lundgren, Kerry Barnes Barnes Gedae, Inc. Gedae, Inc. www.gedae.com 856 - 231- 4458 856 - 231- 4458 HPEC 2007: Multicore Processors and Their Impact on DoD HPEC Systems
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Gedae Portability: From Simulation to DSPs to the Cell Broadband Engine
HPEC 2007: Multicore Processors and Their Impact on DoD HPEC Systems. Gedae Portability: From Simulation to DSPs to the Cell Broadband Engine. James Steed, William Lundgren, Kerry Barnes Gedae , Inc. www.gedae.com 856 - 231- 4458. The Software Architecture Makes Hardware Refreshes Difficult. - PowerPoint PPT Presentation
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Gedae Portability: From Simulation to Gedae Portability: From Simulation to DSPs to the Cell Broadband EngineDSPs to the Cell Broadband Engine
James Steed, William Lundgren, Kerry BarnesJames Steed, William Lundgren, Kerry Barnes
HPEC 2007: Multicore Processors and Their Impact on DoD HPEC Systems
The Software Architecture Makes The Software Architecture Makes Hardware Refreshes DifficultHardware Refreshes Difficult
HPEC 2007HPEC 2007Gedae, Inc.Gedae, Inc.
www.gedae.comwww.gedae.com 22
PE-0PE-0
Code0
PE-1PE-1
Code1
PE-2PE-2
Code2
PE-3PE-3
Code3
PE-APE-A
CodeA
PE-BPE-B
CodeB
PE-CPE-C
CodeC
PE-DPE-D
CodeD
PE-EPE-E
CodeE
PE-FPE-F
CodeF
Old System
New System
Problems that Reduce Software Problems that Reduce Software PortabilityPortability
Languages and compilers are based on serial processorsLanguages and compilers are based on serial processors
Software architecture is buried in the codeSoftware architecture is buried in the code
Differences in multiprocessor/multicore hardware necessitate Differences in multiprocessor/multicore hardware necessitate changes to the software architecturechanges to the software architecture– Number of processorsNumber of processors
– InterconnectionInterconnection
– BandwidthBandwidth
– Processor speedProcessor speed
– Memory sizeMemory size
– Memory structureMemory structure
Gedae mitigates the risk of porting software by automating the Gedae mitigates the risk of porting software by automating the incorporation of the software architecture incorporation of the software architecture
HPEC 2007HPEC 2007Gedae, Inc.Gedae, Inc.
www.gedae.comwww.gedae.com 33
Application EnvironmentApplication Environment
Search and track using four audio channelsSearch and track using four audio channels
Display using camera directed by pan-tilt unitDisplay using camera directed by pan-tilt unit
Nonblocking transfer of audio data from host to PowerPCs
Strip mine for cache performance
Cell/B.E. ArchitectureCell/B.E. Architecture
Power Processing Power Processing Element (PPE)Element (PPE)
8 Synergistic 8 Synergistic Processing Elements Processing Elements (SPE)(SPE)– VMX SIMD VMX SIMD
instruction setinstruction set
– DMA enginesDMA engines
– 256 kB Local 256 kB Local Storage (LS)Storage (LS)
System MemorySystem Memory
Element Interconnect Element Interconnect Bus (EIB)Bus (EIB)– Over 200 GB/sOver 200 GB/s
HPEC 2007HPEC 2007Gedae, Inc.Gedae, Inc.
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Cell/B.E. ImplementationCell/B.E. Implementation
Alter implementation to use 6 Alter implementation to use 6 SPEsSPEs
Alter implementation to fit in Alter implementation to fit in the SPEs’ 256KB Local Storagethe SPEs’ 256KB Local Storage
Maximize use of SPEsMaximize use of SPEs
HPEC 2007HPEC 2007Gedae, Inc.Gedae, Inc.
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Put Preprocessing of 4 channels in 4 partitions
Strip mine to reduce memory footprint
Map partitions to 6 SPEs
Use 2 SPEs to perform 1st stage of correlation
Gedae was used to easily move the application to new Gedae was used to easily move the application to new hardwarehardware
Changes to the implementation were handled by automation Changes to the implementation were handled by automation and simple GUIs, not changes to codeand simple GUIs, not changes to code
High performance gains were realized with minimal effortHigh performance gains were realized with minimal effort