Gate Sizing for Cell Library Based Designs Shiyan Hu*, Mahesh Ketkar**, Jiang Hu* *Dept of ECE, Texas A&M University **Intel Corporation.

Gate Sizing for Cell Library Based Designs

Gate Sizing for Cell Library Based Designs

Shiyan Hu*, Mahesh Ketkar**, Jiang Hu*Shiyan Hu*, Mahesh Ketkar**, Jiang Hu*

*Dept of ECE, Texas A&M University*Dept of ECE, Texas A&M University

**Intel Corporation**Intel Corporation

2

OutlineOutline

IntroductionIntroduction MotivationMotivation Problem FormulationProblem Formulation Algorithms Algorithms

– Continuous solution guided dynamic Continuous solution guided dynamic programmingprogramming

– Node pruning and Stage pruningNode pruning and Stage pruning– Locality Sensitive Hashing based pruningLocality Sensitive Hashing based pruning

Experimental ResultsExperimental Results ConclusionConclusion

3

Gate Sizing ProblemGate Sizing Problem

Size a gate Size a gate – Gate powerGate power– Driving Driving

resistanceresistance– Input capacitanceInput capacitance

Gate sizing problemGate sizing problem– Minimize power Minimize power

subject to timing subject to timing constraintconstraint

Gate sizing for timing-power tradeoff

4

Continuous Gate SizingContinuous Gate Sizing

Previous worksPrevious works– Fishburn and Dunlop, ICCAD’85Fishburn and Dunlop, ICCAD’85– Sapatnekar, Rao, Vaidya, and Kang TCAD ’93Sapatnekar, Rao, Vaidya, and Kang TCAD ’93– Chen, Chu, and WongChen, Chu, and Wong, , TCAD’99TCAD’99

Continuous problem formulationContinuous problem formulation

Minimize Area (Power)Minimize Area (Power)

Subject to:Subject to:

Delay Delay T T XXmin min X X X Xmaxmax

1

X1

X2

X3

2

3

5

MotivationMotivation

Trend: cell library based designTrend: cell library based design– Discrete gate sizesDiscrete gate sizes

Need to round continuous gate sizesNeed to round continuous gate sizes Sparseness of gate library Sparseness of gate library big rounding big rounding

errorerror

Timing violation

6

Nearest Rounding Does Not WorkNearest Rounding Does Not Work

-2500

-2000

-1500

-1000

-500

0

Sla

ck (

ps)

C432 C499 C880 C1355 C1908 C2670 C3540 C5315 C6288 C7552

Continuous solution by mathematical Continuous solution by mathematical programmingprogramming

Rounding continuous sizes to nearest discrete Rounding continuous sizes to nearest discrete sizessizes

7

Discrete Gate SizingDiscrete Gate Sizing

Very few existing approachVery few existing approach GS approach [Coudert, TVLSI’97]GS approach [Coudert, TVLSI’97]

– Trial-and-error style algorithmTrial-and-error style algorithm Based on slacks, pick a group of gates for sizingBased on slacks, pick a group of gates for sizing Random perturbationRandom perturbation Repeat until convergenceRepeat until convergence

– Significant room for improvementSignificant room for improvement

8

Our ChoicesOur Choices

Discrete gate sizing is an integerDiscrete gate sizing is an integerprogramming problemprogramming problem– Hard to solve for large circuitsHard to solve for large circuits

Rounding?Rounding?– Not good solution qualityNot good solution quality– Very fastVery fast

Dynamic programming?Dynamic programming?– Best solution qualityBest solution quality– Computationally prohibitiveComputationally prohibitive

9

Our IdeaOur Idea

Dynamic programming based roundingDynamic programming based rounding– Continuous solution guided dynamic Continuous solution guided dynamic

programmingprogramming Largely reduce search spaceLargely reduce search space Keep solution qualityKeep solution quality

– At each cell, try discrete gate sizes around the At each cell, try discrete gate sizes around the obtained continuous sizeobtained continuous size

– For “critical” cells, try more gate sizesFor “critical” cells, try more gate sizes

10

Overall FlowOverall Flow

Circuit partitioning

Process stage by stage

Pick best solutions at PO

For each gate, sizing around continuous solution and perform node pruning

Locality sensitive hashing based pruning

Stage pruning

11

Circuit PartitioningCircuit Partitioning

A cutline

A cutline – prune solutions for acceleration

A stage - solution propagation

12

Dynamic Programming Based RoundingDynamic Programming Based Rounding

Try gate sizes around continuous solution

For timing critical nodes, try more sizes

13

Pruning For AccelerationPruning For Acceleration

Three types of pruningThree types of pruning– Node pruningNode pruning

Inside a stageInside a stage– Stage pruningStage pruning

At cutlineAt cutline– Locality Sensitive Hashing based pruningLocality Sensitive Hashing based pruning

At cutlineAt cutline

14

Node Pruning (I)Node Pruning (I)

Solution CharacterizationSolution Characterization– A solution s is characterized by D(s) and W(s).A solution s is characterized by D(s) and W(s).

D(s): maximum delay from any primary input to D(s): maximum delay from any primary input to any processed gateany processed gate

W(s): cumulative gate area for all processed W(s): cumulative gate area for all processed gatesgates

Node PruningNode Pruning– Two solutions s1, s2Two solutions s1, s2

s1 is pruned ifs1 is pruned if– D(s1) D(s1) D(s2): larger delay, and D(s2): larger delay, and– W(s1) W(s1) W(s2): larger area. W(s2): larger area.

15

Node Pruning (II)Node Pruning (II)

Solution 1: (D,W)=(11,4)

Solution 2: (D,W)=(10,3)

PrunedD

1x 2x

1x

1x 1x

1x

D

16

Stage PruningStage Pruning

Solution CharacterizationSolution Characterization– A solution s is characterized by f(s) and W(s).A solution s is characterized by f(s) and W(s).

f(s) measures the proximity to the continuous f(s) measures the proximity to the continuous solutionsolution

– gategateii: discrete size, gate: discrete size, gateiicc: continuous size: continuous size

W(s): cumulative gate area for all processed W(s): cumulative gate area for all processed gatesgates

Stage PruningStage Pruning– Two solutions s1, s2Two solutions s1, s2

s1 is pruned ifs1 is pruned if– f(s1) f(s1) f(s2): farther to continuous solution, and f(s2): farther to continuous solution, and– W(s1) W(s1) W(s2): larger area. W(s2): larger area.

gates along the cutline gates along the cutline

| ( ) - ( )| | ( ) - ( )|c ci i i if D gate D gate W gate W gate

17

Locality Sensitive Hashing Based PruningLocality Sensitive Hashing Based Pruning

Maintain diversity in solutionsMaintain diversity in solutions– Do not spend timeDo not spend time

in checkingin checkingsimilar solutionssimilar solutions

How?How?– Cluster solutionsCluster solutions– For each cluster, pick a few representative For each cluster, pick a few representative

solutions for propagationsolutions for propagation

18

Solution ClusteringSolution Clustering

A gate A gate a dimension a dimension Coordinate = gate implementation IDCoordinate = gate implementation ID Large circuit Large circuit many dimensions many dimensions Efficient clustering neededEfficient clustering needed

– Most existing approaches does not scaleMost existing approaches does not scalewell with dimensionalitywell with dimensionality

19

Locality Sensitive Hashing Locality Sensitive Hashing

For m solutions in d dimensions,For m solutions in d dimensions,clustering runs in only O(dmlogm) timeclustering runs in only O(dmlogm) time– Linear in dimensionLinear in dimension

Idea: Idea: – For a solution, concatenate coordinates inFor a solution, concatenate coordinates in

all d dimensions to a single stringall d dimensions to a single string– Map it to a much shorter one while preserving Map it to a much shorter one while preserving

distance propertiesdistance properties– Many solutions Many solutions many short strings. Cluster many short strings. Cluster

them.them.

20

Solution 1Solution 1

1x 2x 5x

1, 2, 5

Concatenate discrete gate

sizes to form a string

00001,00011,11111

Unary representation

21

Solution 2Solution 2

1x 2x 3x

00001,00011,00111

Unary representation

1, 2, 3

Concatenate discrete gate

sizes to form a string

22

Hashing (I)Hashing (I)

00001,00011,11111

00001,00011,00111

Randomly pick k=5

locations

Solution 1

Solution 2

01011Solution 1

01001Solution 2

Shorter

strings

23

Hashing (II)Hashing (II)

Same shorter strings Same shorter strings Hash to same bucket Hash to same bucket Indyk et al, prove thatIndyk et al, prove that

– With large probability, geometrically close With large probability, geometrically close points are hashed together and geometrically points are hashed together and geometrically far-apart points are hashes into different far-apart points are hashes into different buckets.buckets.

– A bucket = a cluster.A bucket = a cluster.

24

Experimental SetupExperimental Setup

ISCAS’85 benchmark circuitsISCAS’85 benchmark circuits X86 computer with 3.2Ghz CPU and 1G X86 computer with 3.2Ghz CPU and 1G

memorymemory 130nm technology130nm technology 10 geometrically spaced gate sizes per gate 10 geometrically spaced gate sizes per gate

typetype Compare to nearest rounding and GS Compare to nearest rounding and GS

approachapproach

25

Comparison on Slack and AreaComparison on Slack and Area

-2500

-2000

-1500

-1000

-500

0C432 C880 C1355 C5315 C6288 C7552

Slack for GS: 2ps - 21ps

Slack for ours: 1ps - 45ps

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

C432 C880 C1355 C5315 C6288 C7552

Rounding Ours

Area saving ratio over GS

Slack from rounding:

Slack(ps)

Area Reduction

26

CPU ComparisonCPU Comparison

0

500

1000

1500

2000

2500

3000

3500

4000

C432 C880 C1355 C5315 C6288 C7552

CPU

(s)

GSOurs

27

ObservationsObservations

Nearest rounding introduces significantNearest rounding introduces significanttiming violationstiming violations

Our algorithm saves 9%-31% area over GS Our algorithm saves 9%-31% area over GS while still improving slacks in many caseswhile still improving slacks in many cases

Runtime of our algorithm is on average 1.7x Runtime of our algorithm is on average 1.7x of GS.of GS.

28

Delay-Cost TradeoffDelay-Cost Tradeoff

Provide more choices to designersProvide more choices to designers Help users get better timing constraint for circuitHelp users get better timing constraint for circuit Two continuous solutions to guide our approach and Two continuous solutions to guide our approach and

two curves are obtainedtwo curves are obtained

29

ConclusionConclusion

Propose a dynamic programming algorithm Propose a dynamic programming algorithm for discrete gate sizing problem. for discrete gate sizing problem. – Reduce search space by continuous solution Reduce search space by continuous solution

guider.guider.– Node pruning, Stage pruning, and Locality Node pruning, Stage pruning, and Locality

Sensitive Hashing based pruning for improving Sensitive Hashing based pruning for improving runtime.runtime.

9%-31% area reduction compared to GS.9%-31% area reduction compared to GS. Future work seeks to handling variations inFuture work seeks to handling variations in

our approach.our approach.