Ashwath Hegde (1) , Yu Long (2) , Esko Mikkola (2) , Jennifer Kitchen (1) , Phaneendra Bikkina (2) , Andrew Levy (2) , Lloyd Linder (2) (1) Arizona State University, (2) Alphacore, Inc. GaN-Based Radiation Hardened High-Speed DC-DC Converter Develop reliable, low-mass, small-form factor, radiation-tolerant, high-performance, single-module point-of-load (POL) DC-DC buck converter(s) that support high particle energy, high radiation or space applications. It will have not only a direct application to the existing power conversion system for the large hadron collider (LHC), but also board applications to the DOE’s future medium- power POL converters. • Robust to radiation and magnetic field tolerant environments. • Efficiently converts an input voltage of 18V-24V to a regulated output of 1.0V to 3.3V with up to 7A load current. • Realized within a small form factor for integration within the LHC. This work has been funded by a Department of Energy SBIR Phase I Contract # DE-SC0015764 Customized rad-hard IC Prototype • Develop reconfigurable capabilities: frequency selection, dead-time, soft-start adjustment. Upgrade to a customized output air-core inductor to achieve optimal converter efficiency and volume requirement. • Add function of rad-hard redundancy at system and circuit levels with techniques such as triplication and voting for both analog and digital blocks. • Update the off-chip passive components for control-loop compensation to a fully on-chip compensation. Improve performance of non-BJT BGR, on-chip voltage regulation options for a stable multiple voltage supply. • Add protection schemes such as under-voltage lockout (UVLO), over-current protection (OCP), over-temperature protection (OTP), output voltage protection, adaptive dead- time control, etc to the next prototype IC tape-out. • Improve circuit performance, such as sink/source current capability and driving transition for output driver, closed- loop response stability and control band-width, efficiency and conversion ratio for converter, volume and weight for off-chip passive components. • Approximate tape-out schedules in 2018 are January/March and September. Final testing and assembly should be finished within 2019. Input Output epm enm VDD GND Input Output ENM_10_0P4_DG_BODY VDD GND epm mosW = 360 mosL = 0.35 m = 20 mosSeg = 20 mosW = 360 mosL = 0.35 m = 20 mosSeg = 20 mosW = 89 mosL = 0.4 m = 20 mosSeg = 20 mosW = 10.5956 mosL = 0.4203 m = 180 mosSeg = 1 pwlned nlvd nlvd Conventional NMOS Customized Radhard NMOS nhvd Parasitic Junction Diodes • Highly integrated, high switching speed buck converter topology to achieve a small physical form-factor. • Optimal division of functionality between Silicon and GaN to take advantage of inherent high current density and high switching speed of GaN devices for the crucial power stage and the versatility of CMOS to implement the bulk of the controller functionality . • Built-in-self test (BIST) that runs in the background to measure loop parameters, diagnose loop components, and estimate remaining lifetime to ensure reliable operation. • An enclosed layout transistor (ELT) technique and design flow to reduce the total ionized dose (TID) induced leakage [1] . • Innovative CMOS-based gate driver architectures that directly control the converter’s high voltage GaN power stage by employing only thin gate-oxide low-voltage devices to maintain highest radiation hardening [2] . • On-chip high-efficiency voltage regulation and distribution schemes. • Accurate Bandgap Reference (BGR) employing CMOS devices without radiation-prone bipolar devices [3] . [1] R. C. Lacoe, “Improving Integrated Circuit Performance Through the Application of Hardness- by-Design Methodology,” IEEE Transaction Nuclear Science, vol. 55, no. 4, Aug. 2008, pp. 1903-1925. [2] F. Faccio, G. Blanchot, et. al, “FEAST2: A radiation and magnetic field tolerant Point-of-Load buck DC-DC converter,” 2014 IEEE Radiation Effects Data Workshop (REDW), Paris, France, Jul. 2014. [3] J. Ramos-Martos, A. Arias-Drake, et al., “Evaluation of the AMS 0.35 um CMOS Technology for Use in Space Applications,” the 4th International Workshop on Analog and Mixed-Signal Integrated Circuits for Space Applications (AMICSA), Noordwijk, Netherlands, Aug. 2012. [4] J. Wibben and R. Harjani, “A High-Efficiency DC–DC Converter Using 2 nH Integrated Inductors”, IEEE Journal of Solid State Circuits, vol. 43, no. 4, pp.844-854, Apr. 2008. [5] A. Hegde, Y. Long and J. Kitchen, “A Comparison of GaN-Based Power Stages for High- Switching Speed Medium-Power Converters,” the 5 th Workshop on Wide Bandgap Power Devices and Applications (WiPDA), Albuquerque, NM, USA, Nov. 2017. [6] F. Neveu, B. Allard, C. Martin, P. Bevilacqua and F. Voiron “A 100 MHz 91.5% Peak Efficiency Integrated Buck Converter With a Three-MOSFET Cascode Bridge,” IEEE Transactions on Power Electronics, vol. 31, no. 6, June 2016, pp.3985-3988. [7] L. Salem, J. Buckwalter and P. Mercier, “A Recursive House-of-Cards Digital Power Amplifier Employing a λ/4-less Doherty Power Combiner in 65nm CMOS,” in Proc. of IEEE 42 nd European Solid-State Circuits Conference (ESSCIRC) Conference, Lausanne, Switzerland, Sep. 2016, pp. 189-192. GaN Single Stage Vout L 1 L 2 C 1 C 3 Vin R_load 24V 5.4V (Imax 10A) P 1 S 1 S 2 110uF 350nH 110nH 4.7uF IL 2 Vout Vin GaN Multi-Phase R_load 24V 5.4V (Imax 10A) 110uF 350nH 110nH 110nH 4.7uF L 1 L 2 C 1 C 3 L 3 P 2 S 4 S 3 P 1 S 1 S 2 IL 2 IL 3 Vout L 1 L 2 C 1 C 3 L 3 Vin GaN Stacked Interleaved R_load 24V 5.4V (Imax 10A) P 2 S 4 S 3 110uF 350nH 110nH 110nH C 1 ' 10uF 4.7uF P 1 S 1 S 2 IL 2 IL 3 Power Stages Prototype Three architectures have been selected for the DC-DC buck converters to evaluate performance of the different power stages. For comparison purposes, the measured results for each architecture in the figure below are configured as open-loop and the control signals are provided by function generator. • Multi-phase architecture has the advantages of high efficiency at large load at 10A. • Stacked interleaved architecture [4] reaches best performance at middle load range at 5A with a duty-cycle independent ripple cancelation. • single-phase stage has a reasonable performance based on the trade-off between the size, volume and efficiency. A fully customized ELT-type NMOS low-voltage core transistor library cells including different sizes of primitive cells (p-cell) based on the selected 0.35um CMOS process is developed to assist EDA design flow such as DRC, VLS and PEX process. The procedures can be divided into four steps. • Approximate a standard NMOS W, L and W/L with a Calibre extracted layout view. • Create a complete DRC and LVS clean cell with all isolation ring, body contact and parasitic diodes added, run PEX simulation if necessary. • Create a core device cell views with only gate, source and drain connection kept the last step. • Create/Update Cadence component description format (CDF) parameters for the core cells created above. These Figures show the cell views of schematic, symbol and layout for a customized ELT NMOS. A buffer with multiplier and isolation rings is generated and verified in pre and post layout simulation. At circuit level low-voltage 3.3V core MOSFET’s have to be used to provide 5V gate driver output. A cascoded, or “house-of-card” structure is used to achieve the 5V output swing without exceeding the 3.3V V DS break-down voltage [6] [7] . The high-side (HS) or low-side (LS) driver is shown in the figures. The schematic and its simulation waveforms at 2-20 MHz frequency with 20% duty-cycle validate the functions. The rad- hard layout with 25V isolation rings is shown below. approx. size: 880 um x 440 um Figure below on the left is the top-level diagram of the whole customized rad-hard driver and controller IC. The I/O LC filters, single-phase GaN power stage, and the passives compensation are off-chip. The circuit on the left pad-frame contains individual blocks for testing, the larger pad-frame on the right is the full complete prototype IC. The final package is 64-lead QFN (9×9). Design Innovations Acknowledgements Motivation Design Approach The design in this phase involves three steps. • A printed circuit board (PCB) prototype design using discrete component-of-the-shelf (COTS) driver and controller IC’s has been fabricated and tested in February. • A fully customized driver IC with conventional analog/digital design techniques has been tape-out with a 0.35um CMOS process in April. • A fully customized single-chip driver and controller IC employed with various RHBD techniques has been taped out with a 0.35um CMOS process in July. Parameter Specifications Unit Input Voltage 16 - 24 V Output Voltage 1.0 - 2.7 V Load Current 5 - 7 A Overall Efficiency ~ 80 % Switching Speed > 10 MHz Temperature range -55 to 125 °C TID tolerance 3 Mrad Mean Time to Failure 4e7 @ 150 ºC hours Efficiency Drop @1Mrad TID < 6 % Physical Dimensions 38mm x 17mm x 8mm mm Based on the simulation and measured results in the figures, based on the stringent form-factor requirement, the single-phase stage has been selected for next step development due to its optimal trade-off between the size, volume and efficiency [5] . Customized ELT NMOS P-cell Library 5 V 0 V 2.5 V 5 V 0 V 5 V 5 V 2.5 V 2.5 V 2.5 V 2.5 V 0 V 0 V Full Tape-out Schematic & Layout To drive the cascaded output driver, a complementary signal pair with one swing range of 2.5-5V and the other one of 0-2.5V is needed. A level shifter also used the radiation tolerant thin gate- oxide low-voltage LDMOS provided in the 0.35um CMOS process. Simulation shows the simulation waveforms with 2-3ns dead-time at 20 MHz with 20% duty cycle. VL VH VH VH VL VL VL VH Isolated HV domain Common LV domain approx. size: 420 um x 500 um Future Developments References LC Passive Output Network 5V BS Supply 5V Supply High-side Low-side Gate Drive Signal Generation BIST Circuitry & Modulator 3.3V Supply 18V Supply Off-chip Passive Compensation 1.7V Load Off-chip Passive Module eGaN Single-Phase CMOS IC 0.35um Process Converter Power Stage Level Shifter Dead- time BGR Ramp Generator Error Amplifier Type III Compensation V out = 1.0-2.7V, I out,nom = 5 A, I out,max = 7 A C Load R Load V in = 18-24V LDO2 LDO1 V in V drv = 5V V ctl = 3.3V High-Speed Comparator HS Driver LS Driver 5V Domain 3.3V Domain 25V Iso. Domain