FVCAG: A framework for formal verification driven power modelling and verification

FVCAG: A framework for formal verification driven power modelling and verification

Arun Joseph, Spandana Rachamalla, Rahul Rao, Anand Haridass, Pradeep Nalla

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Agenda

Background

Limitations of Existing approaches

FVCAG Methodology

Experimental Evaluation

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Background

o Determining power model generation simulation conditions for different input pins of an IP is critical for the accuracy of the power model.

o Identifying instances of IP in a design, where these preferred input pin conditions are violated is also desired.

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IP-1 Netlist

IP-1 Power Model

IP-2 Netlist

IP-2 Power Model

Context 1: Offline flow for IP power characterization

Context 2: Higher level design (D1) using IP-1 & IP-2

IP-1 Netlist

IP-1 Netlist

IP-2 Netlist

IP-2 Netlist

Background

o Modern day microprocessors are complex hierarchical designs

o Industry class microprocessors are designed using a very large number of IPs and IP types and these need to be characterized under different conditions.

o Also, higher level power models when created using inaccurate lower level power models, results in additional errors.

o POWER8 chip photomicrograph indicates regions occupied by the microprocessor cores, interconnect, L2 cache, L3 cache, memory controllers, and other components in the microprocessor.

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Existing Approaches: Limitations

o Manual approaches based on IP design guides, and consultation with design experts.

o Not scalable and not efficient.

o Power modelling and validation is time consuming and highly error prone.

o As IP designs evolve over time, power modelling criteria also need to be constantly updated.

o Additional challenges for power modelling of vendor IP.5

FVCAG: Overview

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FVCAGDesign RTL

FVCAG Config

IP power modelling conditions

IP power violations

Phase 1: Perform higher level

formal verification checks

Phase 2: Analyze check results to simultaneously determine conditions & design errors

FVCAG

FVCAG: Highlights First such industry-class, automated, framework.

Done using a single formal verification run.

Minimal knowledge of the IP design is required.

Much faster and with reduced power modelling errors.

Equally applicable for designs with IP from external vendors.

Re-uses existing design RTL and formal verification tools.

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Formal Verification Engine used in FVCAG

FVCAG uses RuleBase SixthSense Edition, an industrial strength formal verification platform.

RuleBase SixthSense Edition has been used to formally verify designs for more than two decades, running on different design types of different sizes, with different proof algorithms.

It includes a reach set of model checking engines which run in a transformation-based verification framework (TBV).

The TBV framework enables transferring a given model checking problem from one engine to the other while gradually simplifying the problem until it is completely solved.

FVCAG Methodology: Phase 1o Step 1:

Select a higher level RTL design (R) with M instances of the IP of interest.

o Step 2:

Determine input pins of “interest” (n).

These are subset of IP input pins whose condition for power modelling needs to be determined.

The list of such input pins can be either asserted or can be determined automatically.

o Step 3:

Define N=2^n formal verification checks for the pins of interest.

Perform formal verification, configured for the mode of interest, at this higher level of design hierarchy to check for these N checks.

Observe the number of fails (FN) for each of the N checks.

Phase 1: Perform higher level

formal verification checks

Phase 2: Analyze check results to simultaneously determine conditions & design errors

FVCAG

FVCAG Methodology: Phase 2

o Step 4:

Find the check for which number of fails (FN) is zero or minimum.

This is the condition that should be used for power modelling of this cell.

For correct RTL designs, FN will be zero. But will be a non-zero minima for designs with errors.

The instances of IP in R, which contribute to the non-zero minima of FN are those instances, which have design errors.

Using the one condition determined, perform formal verification across more RTL designs to find errors in those designs.

Phase 1: Perform higher level

formal verification checks

Phase 2: Analyze check results to simultaneously determine conditions & design errors

FVCAG

FVCAG: Application ExamplePhase 1: Perform higher level formal verification checksoStep 1:

Say IP of interest is a non-combinatorial standard cell, with a total of 5 input pins. A higher level macro RTL (R), which has say 189 instances of the said IP is selected.

oStep 2: Of the total 5 IP input pins, say 3 pins (P1, P2, and P3) are the pins of interest. The 3 pins of interest are specified so in the FVCAG Config file, along with the mode

information settings for the design RTL .oStep 3:

FVCAG creates N=2^3=8 formal verification checks. Performs formal verification to check for these 8 checks on each of the 189 IP

instances. FVCAG then observes the number of fails (FN) for each of the 8 checks.

Phase 2: Analyze check results to determine conditions and design errorsoStep 4:

Check 7 has the minimum number of fails (13). Check 7 is chosen as the power modelling condition for the IP. The 13 IP instances in the design, which fail check 7 are the design errors. Using the Check 7 conditions, perform formal verification across more RTL designs

to find errors in those designs.

Experimental Evaluation

o Contributor based power modeling framework is used to assess the impact of the FVCAG.

12Reference power analysis tool chain

Experimental Evaluation: Standard Cell Power Modelling

o Compare FVCAG based approaches and manual approaches.

Correct input pin conditions of different LCBs.

Time required to arrive at the correct conditions.

Tracked design errors across macros, releases.

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FVCAG

Core and uncore macro RTL

Config Core and uncore macro RTL

Core and uncore macro RTL

Power modelling criteria for the different LCB types

LCB Design Guide

Design Expert

Manual Approach

Power modelling criteria for the different LCB types

Compare

Experimental Results: Standard Cell Power Modelling

MacroNumber of LCB

instances

Number of violations at the

correct condition

Number of violations at the other wrong

conditionsMacro 1 9 0 9Macro 2 11 0 11Macro 3 31 0 31Macro 4 12 0 12Macro 5 9 0 9Macro 6 109 1 108, 109Macro 7 40 1 39, 40Macro 8 11 0 11Macro 9 20 0 20

Macro 10 48 0 48Macro 11 43 0 43Macro 12 8 0 8Macro 13 28 0 28Macro 14 94 1 93, 94Macro 15 17 0 17Macro 16 12 0 12Macro 17 7 0 7

FVCAG results for LCB power modelling

o Evaluation done across a large number of macros from the core and the uncore units.

o Input simulation condition for different LCB types derived from FVCAG was consistent across the macros.

o Even for macro 6, (highest number of LCBs) the correct simulation condition for all LCB types obtained using FVCAG took less than a minute as opposed to the manual approaches that took more than a day.

Experimental Results: Standard Cell Power Modelling

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All macros across unit

Number of LCBs

Number of violations

Time taken(sec)

Unit1 3179 16 53.4Unit2 225 10 12.97Unit3 990 0 42.34Unit4 1191 16 31.28

FVCAG LCB results across processor units LCBX power modelling differences

o FVCAG was able to correctly identify and report the violating LCB instances in less than a minute, across 4 different units of the microprocessor,

o Wrong setting of a single input pin (PN) of the most widely used LCB results in 50% pessimism in the free running clock power estimation of the LCBX.

Experimental Evaluation: Macro Dynamic Power Modelling

o Compare FVCAG based approaches and manual approaches.

The primary input conditions for the macros.

The macro power seen under TDP (Thermal Design Point) workload conditions of the microprocessor.

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Macro pin conditionsmanually created by

design experts

Macro power modelling tool chain Macro power

FVCAG based macro pin conditions & violation count

Macro power modelling tool chain Macro power

Compare - 2

FVCAG

Violation count in manual conditions

Compare - 1

Experimental Results: Macro Dynamic Power Modelling

o Experiments across the ten macros, where the number of IP in these macros ranged from 17 to 109.

o The overall error in PiSfDepCeff power was found to be in the range of 0 to 39.32%, and error in macro ac power was in the range of 0 to 5.92%.

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Conclusion

Introduced FVCAG, a framework for enabling efficient and accurate pre-silicon IP power modelling.

Advocate supplementing existing power modelling flows with FVCAG.

FVCAG can be implemented using existing design RTL and formal verification tools.

Experimental evaluation of FVCAG demonstrates the efficiency and accuracy.

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