Future trends for SiP In Medical Implant Applications · Future trends for SiP In Medical Implant Applications Piers Tremlett, Zarlink Semiconductor NMI at TWI, 12 Dec 07 [Page 1]

C O N F I D E N T I A L

Future trends for SiP

In Medical Implant Applications

Piers Tremlett,

Zarlink Semiconductor

NMI at TWI, 12 Dec 07

C O N F I D E N T I A L[Page 1]

A case study

� This presentation uses Zarlink’s Medical RF device

� To consider potential embedded component designs

� The main objective is to reduce SiP size

� And ensure suitability for Pacemaker applications

C O N F I D E N T I A L[Page 2]

Introduction

� Introduction to the Packaging Foundry at Zarlink

� Design requirements for RF SiP in Pacemakers

� Zarlink’s embedded component research projects

� Review of other embedded component design options

� The future of embedded component in Zarlink RF SiP’s

C O N F I D E N T I A L

Introduction to Zarlink

Microelectronics

Packaging Foundry

C O N F I D E N T I A L[Page 4]

Zarlink

Microelectronics

� Packaging foundry

– 75% packages for implantable medical devices

– 25% merchant subcontract packaging

� Module and Packaging design

� 75 employees

� Based in Caldicot, South Wales

� Part of a multinational company – Zarlink Semiconductor

C O N F I D E N T I A L[Page 5]

History

� 1983 Established as manufacturer of ceramic hybrid circuits

– SLIC for telecom applications

� 2001 Packaging facility

� Specialist packaging

� Mainly Medical Microelectronics

C O N F I D E N T I A L

Design requirements for the

Pacemaker

C O N F I D E N T I A L[Page 7]

Example Conditions and Implants

� Implantable electronic devices treat these conditions:

– Profound DeafnessCochlear Implant

– Heart conditions

Pacemakers

– DiabetesInsulin pumps

– ParalysisStroke victims“Dropped Foot Implant”

C O N F I D E N T I A L[Page 8]

Pacemakers

� Pacemakers dominate the implant market

� It is the most effective was to treat arrhythmia

� Relatively young people affected by arrhythmia

� Arrhythmia is a common condition

� Most other implant devices:

– Too expensive or risky

– Only the elderly affected

– Rare condition, low volume

C O N F I D E N T I A L[Page 9]

Pacemaker requirements for

new RF SiP design technologies

� Space is a premium

� SiP format

– Narrow long PCB circuits

– Low profile SMT format

� Reliability

� Provide RF shielding?

� Component protection - handling

� Reduced cost

C O N F I D E N T I A L

Zarlink’s embedded component

research projects

C O N F I D E N T I A L[Page 11]

Zarlink research projects

� SHIFT

– Active die embedded in flex

– EU FP6 integrated project, 1st demonstrator due shortly

� CiP

– Embedded die in PCB

– Zarlink funded project

– Collaboration with Technical University of Berlin

� ADEPT

– Embedded planar passive components

– Emphasis on characterisation and simulation

– Collaboration with TWI

C O N F I D E N T I A L[Page 12]

Difficulties for embedded components

� Full PCB manufacturing panels sizes are used

– 12” x 18”” panel size or more

– Much larger than normal PCBs

� Very demanding accuracies are required

– IC dimensions

� PCB manufacturers lack

– Pick and place machines / skills

– Test equipment and skills eg for testing active die

� Lack of equipment for large area PCBs

– Pick and place machines

– Testers

C O N F I D E N T I A L

SHIFT project concept

C O N F I D E N T I A L[Page 14]

Objectives of SHIFT

� To Embed active die on Flex

� To provide working demonstrators

� To evaluate reliability

Die Flex substrate

Stud Bump the die

(Use solder bumps at higher volumes?)

Image:- courtesy of Thales

C O N F I D E N T I A L[Page 16]

Assemble die to Flex

� Thermo compression bond die to flex substrate

� Underfill the die

� (Reflow solder solder bumps at higher volume?)

Die

Gold stud bump

Flex

Copper tracking

C O N F I D E N T I A L[Page 17]

Laminate flex/die with PrepregsLaminate flex/die with PrepregsLaminate flex/die with PrepregsLaminate flex/die with Prepregs

Image:- courtesy of RL Design

PolyimideFlex

substrate

2nd Prepreg

1st Prepreg with

holes for die

Create Vias

C O N F I D E N T I A L[Page 18]

Final Assembly

Place SMT

components

Fold Module

C O N F I D E N T I A L[Page 19]

Will SHIFT meet Zarlink RF module

objectives?

� Space / Format

– Will reduce module size

– Will suit module with flex tail

� Reliability

– Testing not yet started

� RF shielding / component protection

– Partial shielding and component protection - might require a shield

� Reduced cost

– Flex “tail” reduces number of circuits per panel

– Known Good Die issue / Novel process – low yields?

– Limited supplier base – higher cost

C O N F I D E N T I A L

CiP

Chip in Polymer

C O N F I D E N T I A L[Page 21]

Objectives of CiP

� Reduce RF module SiP to less than half the current size

� Surface mountable LGA format

� Demonstrate a working RF transciever

9mm

20mm

C O N F I D E N T I A L[Page 22]

CiPs structure

Pictures courtesy of TUB

� Based upon FR4 core

� Plated via connections to die

C O N F I D E N T I A L[Page 23]

Plate the die wire bond pads

� Bond pads must be plated to “stop” the laser beam

Electroless Ni/Au

Or

Electroplated Cu

Laser beam drills

to create via hole

Pictures courtesy of TUB and IMEC

C O N F I D E N T I A L[Page 24]

CIPS embedded die

RCC

C O N F I D E N T I A L[Page 25]

CiPS module

Embedded

die

SMT components

LGA solder pads

� SMT module

� Working RF module

C O N F I D E N T I A L[Page 26]

Will CiP meet Zarlink RF module

objectives?

� Space / Format

– Will reduce module size

– Will suit low profile SMT format

� Reliability

– 3000 thermal cycles

– Vibration and shock

– MSL 3, MSL 2 soon

� Reduced cost

– Extra cost to plate the die pads

– Known Good Die issue / Novel process – low yields?

– Limited supplier base – high prices?

C O N F I D E N T I A L

Other embedded component

technologies

Embedded Passives

C O N F I D E N T I A L[Page 28]

Planar embedded passive components

� Laminate layer capacitors, inductor and resistors

� Compatible with PCB manufacturing techniques

� Inductors

– Planar spiral inductors to be investigated in ADEPT project

– Could be etched into available copper area in RF module

� Resistors

– Good for PCBs with many resistors with wide tolerances

– Zarlink RF module has 1 resistor… cost / size benefit?

� Capacitors

– Good for decoupling ground/ power planes on large PCBs

– Capacitance too low for Zarlink RF module

C O N F I D E N T I A L[Page 29]

Embed SMT type passives?

� This structure is currently used in products in Japan

� PCB yield loss involves cheap passives and not die

� Would costs be lower?

Flip chip

SMT type

passives

C O N F I D E N T I A L[Page 30]

Integrate thin film passive IC

Thin film

passives die

RF die

� Die with thin film passives on it surface

� Embed two die to produce smallest format?

� Lowest yield format – expensive?

C O N F I D E N T I A L

Potential Zarlink module design

A “road map” design

C O N F I D E N T I A L[Page 32]

Potential Zarlink module design

� Normal PCB and SMT assembly

� Then laminate and encapsulate both sides

� Use etch and via process to provide:

– Integral shield and

component protection

– LGA pads

C O N F I D E N T I A L[Page 33]

Potential Zarlink module reviewed� Size / format

– Reduced size

– Low profile LGA

� Reliability

– Similar to CiP

� RF shielding / Component protection

– An integral shield

– Protect components

� Reduced cost

– Starts with normal SMT process at Zarlink

– Completed by PCB manufacturer

– Individual components returned to Zarlink

C O N F I D E N T I A L[Page 34]

Further development needed

� Need to complete CiP and Shift Projects

� Need to develop a process to embed SMT type passives

� Need to work with an interested PCB supplier

C O N F I D E N T I A L

Still some way to go before

Zarlink develops what it wants!

However, these are early stage projects

that will provide us with an exciting roadmap

to deliver the next generation of miniaturisation.

C O N F I D E N T I A L[Page 36]

Conclusion

� PCB, IC and SMT technology are converging

– Zarlink intends to understand these new design technologies

– And be involved in new packaging development projects

� Currently the supply chain is immature

– Few suppliers

– Equipment needs developing ( eg large area pick and place machines)

– Specialist passives need developing for embedding

� Zarlink is investigating embedded components for SiP

– to enable miniaturisation

– but high yields and lower costs need to be demonstrated

ZARLINK SEMICONDUCTOR

Piers Tremlett

[email protected]

+44 1291 435370