Hiroshi Iwai Frontier Research Center Tokyo Institute of Technology Future of Nano CMOS Future of Nano CMOS Technology Technology September 9, 2013, EDS Mini Colloquium – by Student Chapter at UNICAMP, Campinas, Brazil UNICAMP: Universidate Estadual de Campenus 1
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Hiroshi Iwai
Frontier Research CenterTokyo Institute of Technology
Future of Nano CMOS Future of Nano CMOS TechnologyTechnology
September 9, 2013, EDS Mini Colloquium – by Student Chapter at UNICAMP, Campinas, BrazilUNICAMP: Universidate Estadual de Campenus
1
1. Back ground for nano-electronics
2
1900 “Electronics” started.
Device: Vacuum tubeDevice feature size: 10 cm
1970 “Micro-Electronics” started.
Device: Si MOS integrated circuitsDevice feature size: 10 µm
Major Appl.: Amplifier (Radio, TV, Wireless etc.)
Major Appl.: Digital (Computer, PC, etc.)
Technology Revolution
Technology Revolution
3
2000 “Nano-Electronics” started.
Device: Still, Si CMOS integrated circuitsDevice feature size: 100 nmMajor Appl.: Digital (µ-processor, cell phone, etc.)
Technology Revolution??
Maybe, just evolution or innovation!
But very important so many innovations!
4
Now, 2013 “Nano-Electronics” continued.
Device: Still, Si CMOS integrated circuitsDevice feature size: near 10 nmMajor Appl.: Still Digital (µ-processor, cell phone, etc.)
But, so many important emerging applications for smart society.
Still evolution and innovation..
5
Future, “Nano-Electronics” still continued?
Device: Still, Si CMOS integrated circuits?
Device feature size: ? nm, what is the limit?
Application: New application?
Any Technology Revolution?
Questions for future
6
What is special or new for Nano-Electronics?
In 1990’s, people expected completely new mechanism or operational principle due the nano size, like quantum mechanical effects.
However, no fancy new operational principle was found.
At least for logic application, there is no success story for “Beyond CMOS devices” to replace Si-CMOS.
Of course, I do not deny the importance of Beyond CMOStechnology development. It is becoming very importantas CMOS approach its limit.
7
λ>>LDiffusive transport
λ<LBallistic transport
λ~LQuasi-Ballistic transport
Lλ :Mean free pathsource drain
RM
Back scatteringfrom drain
Ballistic transport will never happen for MOSFET because of back scattering at drain
With decreasing channel length,Drain current increase continue.
Also, 1D quantum conduction, or ballistic conduction will not happen.
Ballistic conduction will not happeneven decreasing channel lengh.
(1D quantum conduction: 77.8µS regardless of the length and material).8
2. Importance of nano-electronics as integrated circuits
9
First Computer Eniac: made of huge number of vacuum tubes 1946Big size, huge power, short life time filament
Today's pocket PCmade of semiconductor
has much higher performance with
extremely low power consumption
dreamed of replacing vacuum tube with solid‐state device
What are volume, weight, power consumption for 1Tbit
14
Old Vacuum Tube:5cm X 5cm X 10cm
1Tbit = 10,000 X 10,000 X 10,000 bitVolume = (5cm X 10,000) X (5cm X 10,000)
X (10cm X 10,000)= 0.5km X 0.5km X 1km
500 m
1,000 m
1Tbit
Burji KhalifaDubai, UAE(Year 2010)
828 m
Indian TowerMumbai, India(Year 2016)
700 m
700 m
Pingan IntenationalFinance Center
Shanghai, China(Year 2016)
15
Old Vacuum Tube:100W
1Tbit = 1012bitPower = 0.05kWX1012=50 TW
Nuclear Power Generator1MkW=1BW We need 50,000 Nuclear Power Plant for
just one 128 GB memory
In Japan we have only 54 Nuclear Power Generator
Last summer Tokyo Electric Power Company (TEPCO) can
supply only 55BW.
We need 1000 TEPCO just one 128 GB memory
Imagine how many memories are used in the world! 16
So progress of integrated circuits is extremely
important for power saving
17
Brain: Integrated Circuits
Hands, Legs:Power device
Stomach:PV device
Ear, Eye:Sensor
Mouth:RF/Opto device
18
19
Near future smart-society has to treat huge data.
Demand to high-performance and low power CMOS become much more stronger.
20
Semiconductor Device Market will grow 5 times in 12 years, even
though, it is very matured market!!
Gartner: By K. Kim, CSTIC 2012
300B USD
2011
1,500B USD
2025
2. Current status of Si-CMOS device technologies
21
Downsizing
Important for
Decreasing cost, power
Increasing performance
22
23
(1970) 10 μm 8 μm 6 μm 4 μm 3 μm 2 μm 1.2 μm
0.8 μm 0.5 μm 0.35 μm 0.25 μm 180 nm 130 nm
90 nm 65 nm 45 nm 32 nm (28 nm ) 22 nm(2012)
Feature Size / Technology Node
From 1970 to 2013 (This year)
18 generationsLine width: 1/450
Area: 1/200,000
43 years 1 generation2.5 years
Line width: 1/1.43 = 0.70
Area: 1/2 = 0.5
Gate oxide
Gate metal
Source Drain
1V0V0V
Substrate 0V DepletionRegion (DL)by Drain Bias
1V
0V 0V
tox and Vdd have to be decreased for better channel potential control IOFF Suppression
0V < Vdep<1V
0V
0V < Vdep<1VChannel
0V
0V
0V0V
0.5V
Large IOFF
Region governed By drain bias
Region governed by gate bias
tOX, Vdd thinning
DL touch with SRegion (DL)
Large IOFF
No tox. Vddthinning
Vdd
Vdd
24
Problem for downsizing
(Electron current)
LLgate gate and tand toxox(EOT) scaling trend(EOT) scaling trendA. Toriumi (Tokyo Univ), IEDM 2006, Short Course
t ox(
(
25
0 0.2 0.4 0.6 0.8 1.0
Drain Voltage (V)
0.2
0.4
0.6
0.8
1.0
Dra
in C
urre
nt (m
A)
Vg= 0.4V
Vg= 0.6V
Vg= 0.8V
Vg= 1.0V
Vg= 0.2V
Vg= 0 V
L/W = 5/20µm
T = 300K
Nsub = 3×1016cm-3
0
20
40
60
80
100
120
140
0 0.5 1 1.5 2 2.5
EOT = 0.40nm
L/W = 5/20µm
T = 300K
Nsub = 3×1016cm-3
Eeff [MV/cm]El
ectr
on M
obili
ty [c
m2 /V
sec]
EOT=0.40nm
Our Work at TIT: HighOur Work at TIT: High--k k
26
Tunnelingdistance
3 nm
What would be the limit of downsizing!
Source DrainChannel
27
Ene
rgy
or P
oten
tial
for E
lect
ron
Direct‐tunnelcurrent
28
Vg
Id
Vth (Threshold Voltage)
Vg=0V
SubthreshouldLeakage Current
Subtheshold leakage current of MOSFET
Subthreshold CurrentIs OK at Single Tr. level
But not OKFor Billions of Trs.
ONOFF
Ion
Ioff
Subthresholdregion
29
Vg (V)1
0.3 V
0.5 V 1.0 V
Ion
Ioff
Id (A/µm)
10-7
10-5
10-11
10-9
Vd
Vth
0.15 V
0 0.5
Subthreshold leakage current will limit the downsizing
Electron EnergyBoltzmann statics
Exp (qV/kT)
30Subthreshold Leakage (A/µm)
Ope
ratio
n Fr
eque
ncy
(a.u
.)
e)
100
10
1
Source: 2007 ITRS Winter Public Conf.
The limit is deferent depending on application
How far can we go for production?
10µm 8µm 6µm 4µm 3µm 2µm 1.2µm 0.8µm 0.5µm
0.35µm 0.25µm 180nm 130nm 90nm 65nm 45nm 32nm
(28nm) 22nm 16nm 11.5 nm 8nm 5.5nm? 4nm? 2.9 nm?
Past 0.7 times per 2.5 years
Now Future
・At least 4,5 generations to 8 ~ 5 nm
31
Intermediatenode
Direct-tunnelSubthreshold
Drain bias induced
Limit depending on applications
Fundamentallimit
1V0V
0V
S
0V
0V <V<1V
1V0V
0V
0V
0VS D
G
G
G
Extremely Thin SOI
Planar Extremely Thin SOI
32
Si
SiO2
Extremely thin Si
Drain bias induced depletion
1V0V
0V
S
0V
0V <V<1V
1V0V
0V
0V
0VS D
G
G
G
Suppression of subthreshold leakage by surrounding gate structure
Planar Multi gate
33
Si fin or nanowire
Drain bias induced depletion
Planar Fin Nanowire
Source DrainGate
Wdep
1
Leakage current
S D
Planar FETFin FET Nanowire FET
Because of off-leakage control,1V
0V
0V0V
0VS
D
GG
34
Fin Tri-gate(Variation)
Ω-gate All-around
G G G
G
GNanowire structures in a wide meaning
35
G
Tri-gate
Our work at TIT: Our work at TIT: ΩΩ--gate Si Nanowiregate Si NanowireS. Sato et al., pp.361, ESSDERC2010 (Tokyo Tech.)
19 nm
12 nm
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
-1.5 -1.0 -0.5 0.0 0.5 1.010-12
Gate Voltage (V)
pFET nFET
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
Dra
in C
urre
nt (A
)
Vd=-50mV
Vd=-1V
Vd=50mV
Vd=1V
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
-1.5 -1.0 -0.5 0.0 0.5 1.010-12
Gate Voltage (V)
pFET nFET
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
10-3
Dra
in C
urre
nt (A
)
Vd=-50mV
Vd=-1V
Vd=50mV
Vd=1V
0 0.5 1 1.5 2ION (mA/µm)
Lg=65nm
0 0.5 1 1.5 2ION (mA/µm)
Lg=65nm
Lg=65nm
Poly-Si
SiO2
SiNSiN
SiO2
NW
・Conventional CMOS process
・High drive current
(1.32 mA/µm @ IOFF=117 nA/µm)
・DIBL of 62mV/V and SS of 70mV/dec for nFET 36
More Moore to More More MooreMore Moore to More More Moore
65nm 45nm 32nm
Technology node
M. Bohr, pp.1, IEDM2011 (Intel)P. Packan, pp.659, IEDM2009 (Intel)C. Auth et al., pp.131, VLSI2012 (Intel)T. B. Hook, pp.115, IEDM2011 (IBM)S. Bangsaruntip et al., pp.297, IEDM2009 (IBM)
Lg 35nm Lg 30nm
(Fin,Tri, Nanowire)
22nm 15nm, 11nm, 8nm, 5nm, 3nm
Alternative (III-V/Ge) Channel FinFET
Emerging Devices
Tri-Gate
Now Future
Si channelSi
Others
(ETSOI)Planar
Si is still main stream for future !! ET: Extremely Thin28nm
HighHigh--k gate dielectricsk gate dielectrics
Continued research and development
SiO2 IL (Interfacial Layer) is used at Si interface to realize good mobility
Technology for direct contact of high-k and Si is necessary
Remote SiO2-IL scavengingHfO2 (IBM)
EOT=0.52 nm
Si
La-silicate
MG
Direct contact with La-silicate (Tokyo.Tech)
T. Ando, et al., p.423, IEDM2009, (IBM) T. Kawanago, et al., T-ED, vol. 59, no. 2, p. 269, 2012 (Tokyo Tech.)
K. Mistry, et al., p.247, IEDM 2007, (Intel)
TiN
HfO2
Si
SiO2
EOT=0.9nmHfO2/SiO2(IBM)
T.C. Chen, et al., p.8, VLSI 2009, (IBM)
Hf-based oxides
45nmEOT:1nm
32nmEOT:0.95nm
22nmEOT:0.9nm
15nm, 11nm, 8nm, 5nm, 3nm,
K. Kakushima, et al., p.8, IWDTF 2008, (Tokyo Tech.)
EOT=0.37nm EOT=0.40nm EOT=0.48nm
0.48 → 0.37nm Increase of Id at 30%38
[a] C. Auth et al., pp.131, VLSI2012 (Intel).[b] K. Mistry et al., pp.247, IEDM2007 (Intel).[c] H.-J. Cho et al., pp.350, IEDM2011 (Samsung).[d] S. Saitoh et al., pp.11, VLSI2012 (Toshiba).[e] S. Bangsaruntip et al., pp.297, IEDM2009 (IBM).
[f] T. Yamashita et al., pp.14, VLSI2011 (IBM).[g] A. Khakifirooz et al., pp.117, VLSI2012 (IBM).
IIONON and Iand IOFFOFF benchmarkbenchmark
[h] G. Bidal et al., pp.240, VLSI2009 (STMicroelectronics).[i] S. Sato et al., pp.361, ESSDERC2010 (Tokyo Tech.)[j] K. Cheng et al., pp.419, IEDM2012 (IBM)
Metal gate can eliminate the poly-Si depletion.Inversion CET = Tinv ≈ EOT + 0.4nm with metal gate electrode
Metal
Cmetal
Poly-Si(1020cm-3)
K. Natori, et al., (Tsukuba Univ) SSDM 2005, p.286
CMetal(EOT: 0.1 nm)
Depletion
Cmetal is finite because of quantum effect. In other words electron is not a point charge
located at the interface but distributed charge.
(EOT: 0.3 nm)
Combination of high-k and metal gate is important
67
R. Hauser, IEDM Short Course, 1999Hubbard and Schlom, J Mater Res 11 2757 (1996)
Gas or liquidat 1000 K
H
Radio activeHe
Li BeB C N O F Ne
① Na Mg Al Si P S Cl Ar
② ① ① ① ① ① ① ① ① ① ① K Ca Sc Ti V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr ① ① ① ① ① ① ① ① ① ① Rh Sr Y Zr Nb Mo Tc Ru Rb Pd Ag Cd In Sn Sb Te I Xe ③ ① ① ① ① ① ① ① Cs Ba
HfTa W Re Os Ir Pt Au Hg Tl Pb Bi Po At Rn
Fr Ra Rf Ha Sg Ns Hs Mt
La Ce Pr Nd Pm Sm Eu Gd Tb Dy Ho Er TmYb Lu Ac Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No Lr
Candidates
Na Al Si P S Cl Ar
② ① ① ① ① ① ① ① ① ① K Sc Ti V Cr Mn Fc Co Ni Cu Zn Ga Ge As Se Br Kr ① ① ① ① ① ① ①
Ac Th Pa U Np Pu Am Cm Bk Cf Es Fm Md No Lr
②
③
Unstable at Si interfaceSi + MOX M + SiO2①
Si + MOX MSiX + SiO2
Si + MOX M + MSiXOY
Choice of High-k elements for oxide
HfO2 based dielectrics are selected as the
first generation materials, because of
their merit in1) band-offset,
2) dielectric constant3) thermal stability
La2O3 based dielectrics are
thought to be the next generation materials, which may not need a
thicker interfacial layer
68
Si-sub.
Metal
SiO2-IL
High-kSmall interfacial state
density at high-k/Si
Oxygen diffusion control for prevention of EOT increase
and oxygen vacancy formation in high-k
Thinning or removal of SiO2-IL for small EOT
Flat metal/high-k interface for better
mobility
O
Workfunction engineering for Vth control
Interface dipole control for Vth tuning
Suppression of oxygen vacancy
formation
Control of interface reaction and Si diffusion to high-k
Oxygen concentration control for prevention of EOT
increase and oxygen vacancy formation in high-k
Suppression of metal diffusion
Endurance for high temperature process
Remove contaminationintroduced by CVD
Reliability: PBTI, NBTI, TDDB
Suppression of gate leakage current
Suppression of FLP
69
Issues in high-k/metal gate stack
0 10 20 30 40 50Dielectric Constant
4
2
0
-2
-4
-6
SiO2
Ban
d D
isco
ntin
uity
[eV]
Si
XPS measurement by Prof. T. Hattori, INFOS 2003
Conduction band offset vs. Dielectric Constant
Band offset
Oxide
Leakage Current by Tunneling
70
SiO2-ILHfSix (k~4)
VO
IO
IOVO
VO
IOIO
VOHfO2
Si substrate SiO2-IL(k~4)
LaSix
VO
IOVO
IO
VO
IOLa2O3silicate
La-rich Si-rich
Si substrate
High PO2Low PO2 High PO2Low PO2
HfO2 case La2O3 case
Direct contact can be achieved with La2O3 by forming silicate at interfaceControl of oxygen partial pressure is the key for processing.
Our approach
K. Kakushima, et al., VLSI2010, p.69
Direct high-k/Si by silicate reaction
SiO2-ILHfSix (k~4)
VO
IO
IOVO
VO
IOIO
VOHfO2
Si substrate SiO2-IL(k~4)
LaSix
VO
IOVO
IO
VO
IOLa2O3silicate
La-rich Si-rich
Si substrate
High PO2Low PO2 High PO2Low PO2
SiO2 IL formation
Si substrate
silicate formation
Si substrate
HfO2 case La2O3 case
Direct contact can be achieved with La2O3 by forming silicate at interfaceControl of oxygen partial pressusre is the key for processing.
Our approach
K. Kakushima, et al., VLSI2010, p.69
Direct high-k/Si by silicate reaction
1837184018431846Binding energy (eV)
Inte
nsity
(a.u
)
Si sub.
Hf SilicateSiO2
500 oC
1837184018431846Binding energy (eV)
Inte
nsity
(a.u
)
Si sub.
Hf SilicateSiO2
500 oC
SiOx-IL
HfO2
W
1 nm
k=4
k=16
SiOx-IL growth at HfO2/Si Interface
HfO2 + Si + O2→ HfO2 + Si + 2O*→HfO2+SiO2
Phase separator
SiOx-IL is formed after annealingOxygen control is required for optimizing the reaction
Oxygen supplied from W gate electrode
XPS Si1s spectrum
D.J.Lichtenwalner, Tans. ECS 11, 319
TEM image500 oC 30min
H. Shimizu, JJAP, 44, pp. 6131
La-Silicate Reaction at La2O3/Si
La2O3
La-silicate
W
500 oC, 30 min
1 nm
k=8~14
k=23
1837184018431846Binding energy (eV)
Inte
nsity
(a.u
)
as depo.
300 oC
La-silicate
Si sub.
500 oC
1837184018431846Binding energy (eV)
Inte
nsity
(a.u
)
as depo.
300 oC
La-silicate
Si sub.
500 oC
La2O3 + Si + nO2→ La2SiO5, La2Si2O7,
La9.33Si6O26, La10(SiO4)6O3, etc.La2O3 can achieve direct contact of high-k/Si
XPS Si1s spectra TEM image
Direct contact high-k/Si is possible
5m
Robot
Flash Lamp
ALDRTAEntrance
Sputterfor MG
EB Deposition for HK5m
Cluster tool for HKMG Stack
75
Cluster Chambers for HKMG Gate Stack
Flash Lamp Anneal
EB Deposition: HK Sputter: MG
ALD: HK
Robot
RTA
Entrance
76
Substrate
Moving Mask
SourceElectron Beam
Flux
Deposited thin film
77
78
79
L=0.5~100µm (8 kinds)W=10, 20, 50, 100µm(4 kinds)
30 different Trs
26 c
hips
1cm
1cm
1cm×1cm
p-Si
S Dn+ Sn+SiO2
80
Shutter movement
Chip
Si Si SiSi
Metal Metal Metal Metal
Thin Thick
high-k
15cm
0.0E+00
5.0E-04
1.0E-03
1.5E-03
2.0E-03
2.5E-03
3.0E-03
3.5E-03
0 0.2 0.4 0.6 0.8 1
Vg=0VVg=0.2VVg=0.4VVg=0.6VVg=0.8VVg=1.0VVg=1.2V
0 0.2 0.4 0.6 0.8 1
Vg=0VVg=0.2VVg=0.4VVg=0.6VVg=0.8VVg=1.0VVg=1.2V
0 0.2 0.4 0.6 0.8 1
Vg=0VVg=0.2VVg=0.4VVg=0.6VVg=0.8VVg=1.0VVg=1.2VI d
A fairly nice La-silicate/Si interface can be obtained with high temperature annealing. (800oC)
However, high-temperature anneal is necessary for the good interfacial property
83
① silicate-reaction-formedfresh interface
metal
Si sub.
metal
Si sub.
La2O3 La-silicateSi Si
Fresh interface with silicate reaction
J. S. Jur, et al., Appl. Phys. Lett., Vol. 87, No. 10, (2007) p. 102908
② stress relaxation at interface by glass type structure of La
silicate.
La atomLa-O-Si bonding
Si sub.
SiO4tetrahedron network
FGA800oC is necessary to reduce the interfacial stress
S. D. Kosowsky, et al., Appl. Phys. Lett., Vol. 70, No. 23, (1997) pp. 3119
Physical mechanisms for small DitPhysical mechanisms for small Dit
84
No interfacial layer can be confirmed with Si/TiN/W
MIPSW TiN/W
Kav ~ 8 Kav ~ 12 Kav ~ 16
Si 2nm2nm2nm
HK
MG
La2O3Si/TiN/W
La2O3/silicate/n-Si CV
-0.5-1.0-1.5 0.0 0.5Gate voltage (V)
3
2
1
0
Cap
acita
nce
dens
ity (µ
F/cm
2 )
W/La2O3(4nm)/n-Si600oC, 30min
∆Vfb
Cfb
1MHz
1kHz
85
0.0E+00
5.0E-07
1.0E-06
1.5E-06
2.0E-06
2.5E-06
3.0E-06
1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07
Gp/ω
(F/c
m2 )
0.0
0.5
1.0
2.0
2.5
(×10-6)3.0
ω (rad/s)
1.5
10 103 104 105 106 107102
400
500
600
Dit, Dslow(FG anneal)
Dit
, Dsl
ow(c
m-2
/eV
)
1014
1013
1012
1011
Annealing temperature (oC)as 200 400 600 800 1000
Dit
Dslow
Dit
Dslow
86
Annealing temperature (oC)
10-11
σ it,
σ slo
w(c
m2 )
10-12
10-13
10-14
10-15
∆Vfb
(V)
-0.1
-0.2
-0.3as 200 400 600 800 1000
0.0
Dslow=2.8x1013cm-2/eV
∆Vfb=CLa2O3/qDslow
⎟⎠⎞
⎜⎝⎛−=
λσσ silicate
slowtexp0 (λ=0.8nm)
Slow trap state
σslow
σit
La2O3
silicate (tsilicate)
Dit
DslowVg
Ef
n-Si
CLa2O3
It is important to change the La2O3 to La-silicate completely
87
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
600 700 800 900 1000As depo
~ ~
Annealing temperature (oC)
EOT
(nm
)
Annealed for 2 sLa2O3(3.5 nm)
W(60 nm)
TiN/W(12 nm)
TiN/W(6 nm)
TiN(45nm)/W(6nm)
00.5
11.5
22.5
33.5
44.5
-1 -0.5 0 0.5
Vg (V)
Cg
(uF/
cm2 )
Experiment
Cvc fittingTheory
EOT=0.55nm
TaN/(45nm)/W(3nm)900oC, 30min
EOT=0.55nm
88
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.5 0.55 0.6 0.65 0.7
Flat
-ban
d vo
ltage
(V)
EOT(nm)
TaN(45nm)/W(3nm)
900oC, 30min
Qfix=1×1011 cm-2
Fixed Charge density: 1×1011 cm-2
89
0
20
40
60
80
100
120
140
160
180
0 0.5 1 1.5 2
EOT = 0.53nm
L/W = 20/20µm
T = 300K
Nsub = 3×1016cm-3
Eeff [MV/cm]
Elec
tron
Mob
ility
[cm
2 /Vse
c]Si-sub
SiO2S D
Si-sub
Si-sub
La2O3W AlTaN/ 熱処理
151cm2/VsEeff=1MV/cm150cm2/Vs
0 0.2 0.4 0.6 0.8 1.0
Drain Voltage (V)
5010
015
020
025
0
Dra
in C
urre
nt (µ
A)
Vg= 0.4V
Vg= 0.6V
Vg= 0.8V
Vg= 1.0V
Vg= 0.2VVg= 0 V
L/W = 20/20µm
T = 300K
Nsub = 3×1016cm-3
300
EOT = 0.53nm
EOT=0.53nm
90
10-5
10-4
10-3
10-2
10-1
100
101
103
104
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Gate voltage (V)
Gat
e cu
rrent
(A/c
m2 )
102
ITRSの要求値
x1/100
Wg/Lg=20/20µmEOT=0.55nm
TaN/W/LaSiOx/nFET
91
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
0.3 0.4 0.5 0.6 0.7 0.8
ITRS requirement
J gat
1 V
(A/c
m2 )
EOT (nm)
Benchmark of LaBenchmark of La--silicate dielectricssilicate dielectrics
T. Ando, et al., (IBM) IEDM 2009, p.423
0
50
100
150
200
250
300
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1EOT (nm)
Mob
ility
(cm
2 /Vse
c)
at 1 MV/cm
Open square : Hf-based oxides
Solid circle: Our data
Our data: La-silicate gate oxide
La-silicate gate oxide
L.-Å. Ragnarsson, et al., (IMEC) Microelectron. Eng, vol. 88, no. 7, pp. 1317–1322, 2011.
92
Gate Leakage current Effective Mobility
Si benchmark (nMOSFET)Si benchmark (nMOSFET)
93
EOT Mobility Vth SS DIBLGate stack Ref.
0.45nmTiN/Cap/HfO2 115cm2/Vs
(at 1x1013cm-2)IMEC
MEE20110.3V
(Lg=10um)
0.52nmTiN/Cap/HfO2 110cm2/Vs
(at 1x1013cm-2)IBM
VLSI2011~0.4V
(Lg=24nm) 90mV/dec 147mV/V
0.59nmMetal/HfO2 130cm2/Vs
(at 1MV/cm)0.45V
(Lg=1um) 75mV/decSematechVLSI2009
0.65nmMetal/Hf-basedSamsungVLSI2011
0.3~0.4V(Lg=~30nm) 90mV/dec 100mV/V
0.95nmMetal/Hf-basedIntel
IEDM2009~0.3V
(Lg=30nm) 100mV/dec ~200mV/V
0.62nmW/La-silicateTokyo Tech.T-ED2012
-0.08V(Lg=10um) ~70mV/dec
155cm2/Vs (at 1MV/cm)
0.55nmTiN/Cap/HfO2 140cm2/Vs
(at 1MV/cm)IBM
VLSI2009
substrate
①La gas feed
②Ar purge ③H2O feed
④Ar purge
Laligand H
O
substrate substrate substrate
1 cycle
La
C 3H7
3
L a
C 3H7
3
L a
C 3H7
3
CLaN
NH
C3H7
C3H7
La(iPrCp)3 La(FAMD)3
Precursor (ligand)
ALD is indispensable from the manufacturing viewpoint- precise control of film thickness and good uniformity
K. Ozawa, et al., (Tokyo Tech. and AIST) Ext. Abstr. the 16th Workshop on Gate Stack Technology and Physics., 2011, p.107.
94
ALD of La2O3
Advantages of metal S/D- atomically abrupt junction- low parasitic resistance- reduced channel dopantconcentrationIssues in metal S/D- two different φB for p/n-ch FETs- underlap/overlap to the gate- narrow process temperature window
L. Hutin, pp.45, IEDM2009 (CEA-LETI)
S D
BOX
Dopant Segregationlayer
Si
Metal S/D is considered for alternativechannel material such as InGaAs and Ge
S.-H. Kim, IEDM (2010) 596
Ni is used both onInGaAs and Ge to
form alloy.
K. Ikeda, VLSI (2012) 165
Metal S/DMetal S/D
95
4. Alternative channel devices
96
Ge,IIIGe,III--V bulk properties V bulk properties
S. Takagi., IEDM2011, Short course (Tokyo Uni)97
Metal S/D InGaAs‐OILch= 55nm, EOT 3.5nmVDS=0.5V(Tokyo Uni.)[e]
Ge GAA Lg= 300nm, dielectric: GeO2(7nm)-HfO2(10nm)VD= -0.8V (ASTAR Singapore)[h]
Ge FinFETLg=4.5 mm,
Dielectric: SiON, VDS=‐1V(Stanford Uni.)[g]
GOI Tri‐gateLg: 65nm. EOT 3.0nm
VD=‐1V (AIST Tsukuba)[f]
Si‐bulk 45nmIntel VDD=1V
I OFF(A/µm)
ION (mA/µm)
nMOS pMOS
ION (mA/µm)[a] J. J. Gu et al., pp.769, IEDM2011 (Purdue).[b] M. Radosavljevic et al., pp.765, IEDM201(Intel).[c] H. –C. Chin et al., EDL 32, 2 (2011) (NUS)[d] K. Tomioka et al., pp.773, IEDM2011 (Hokkaido Uni).
[f] K. Ikeda et al., pp.165, VLSI2012 (AIST, Tsukuba).
[g] J. Feng et al., IEEE EDL 28(2007)637 (Stanford Uni)[h] J. Peng et al., pp.931, IEDM2009 (ASTAR Singapore)[i] S. Hsu et al., pp.825, IEDM2011 (NNDL Taiwan)
[e] S. H. Kim et al., pp.177, VLSI2012 (Tokyo Uni)
Si‐bulk 45nmIntel VDD=1V[k]
Si‐FinFET 32nmIntel VDD=0.8V [10]
Si‐FinFET 32nmIntel VDD=0.8V [j]
[j] C. Auth et al., pp.131, VLSI2012 (Intel).[k] K. Mistry et al., pp.247, IEDM2007 (Intel).
Si‐FinFET 22nmIntel VDD=0.8V [j]
Si‐FinFET 22nmIntel VDD=0.8V [j]
ION/IOFF Benchmark of Ge pMOSFET
99
Planar(metal S/D, Strain, Buffer…)
FinFET Tri‐gateGate‐all‐around
MOSFETNanowire
material InGaAs Ge InGaSn InGaAs Ge InGaAs Ge InGaAs Ge InGaAs(multishell)
Ge
Dieletric/EOT
Al2O3/ 3.5 nm
7.6 Ao
HfO2+ Al2O3+GeO2
5nm ALDAl2O3
5nm ALD Al2O3
SiON 1.2 nm5.5 nm(Al2O3+GeO2)
10nm‐ALD Al2O3
HfO2:11nm
HfAlO14.8 nm
3.0 nm(ALD Al2O3)
Mobility ‐ ~600(cm2/Vs)
e: 200h: 400
~700(µS/µm)
‐ ‐ ‐ 701(µS/µm)
‐ ~500(µS/µm)
~850(cm2/Vs)
Lch (nm) 55W/L=
30/5 µm50 µm 100 4.5 µm 60 183 50 200 200 65
DIBL(mV/V)
84 ‐ ‐ 180 ‐ ~50 ‐ 210 ‐ ‐ ‐
SS(mV/dec)
105 ‐61pMOS33nMOS
145 750 90 130 150 160 ‐ ‐
ION(µA/µm)
278(VD=0.5V)
3(VD=‐0.2V)
4 (n,p)(VD=0.5V)
‐ 10(VD=0.5V)
400(VD=0.5V)
235(VD=‐1V)
180(VD=0.5V)
604(VD=‐0.5V)
100(VD=0.5V)
731(VD=‐1V)
ResearchGroup
Tokyo UniVLSI 2012
Tokyo UniVLSI 2012
Stanford Uni VLSI 2012
Purdue Uni IEDM 2009
Stanford Uni ELD 2007
IntelIEDM 2011
NNDL Taiwan
IEDM 2011
Purdue Uni IEDM 2011
ASTARSingapore IEDM 2009
Hokkaido Uni, IEDM
2011
AIST Tsukuba VLSI 2012
150K
120K
(cm2/Vs)
Ns: 5e12
III-V/Ge benchmark for various structures
100
ION at LG = 50 µm pMOS: 4 µA/µmnMOS: 3.8 µA/µm
Achieving both N‐ and P‐type MOSFETon a single channel is possible
electron/hole mobility > 4000/900cm2/Vs was gained in a single channel material
In‐content of 20‐40% improves perfomance
Z. Yuan et al., pp.185, VLSI2012 (Stanford Uni)
InGaSb as channel material (stanford)
Electron MobilityHole Mobility
AlGaSb creates barrierfor both electrons and holes
SiSi
InGaSbInGaSb
101
Metal S/D and InAs buffer layer are usedas performance boosters.DIBL=84 mV/V and SS=105 mV/V was shown for Lch = 55 nm when In‐content washigher.
S. H. Kim et al., pp.177, VLSI2012 (Tokyo Uni)
Metal S/D InGaAs MOSFET (Tokyo Uni)
102
SS: nMOS: 90 (mV/decade)pMOS: 190 (mV/decade)
Si2H6 plasma passivation is employedwhich creates Si layer at interface.
Common gate stack (gate metal and dielectric) were used for both p‐ and n‐type
High intrinsic peak GM,Sat=of ~465 μS/μm at VDS=-1.1 V was achieved for LG=250 nm.
X. Gong, et al. (National Uni of Singapore), VLSI2012, p.99.
K. Banerjee, UC Santa Barbara, G-COE PICE International Symposium on Silicon Nano Devices in 2030
Carbon nanotube and GrapheneCarbon nanotube and Graphene
SWCNT : single wall carbon nanotubeGNR : graphene nano ribbon
Carbon materials for FET applications ・ an ultra-thin body for aggressive channel length scaling・ excellent intrinsic transport properties similar to carbon nanotubes・ pattern the desired device structures
Read/write are enabled by using ferromagnetic electrodes and Spin-polarized current
Lg = 1µm
Spin transfer Torque Switching MOSFETSpin transfer Torque Switching MOSFET
127
Advantage Issues
TFETLower Vdd
Lower IOFF
Integrationhigher ION
CNT FETHigher transport velocity
Lg scaling
High density and alignment, reproducibility,
integration
Graphene FETRF application
Large area manufacturingNOT a direct replacement
for Silicon logic
MEMS Extremely low leakage Ultra-low digital logic
EnduranceSlow speed, scalability
Junctionless FET CMOS process compatibility
Worse gate control in short-channel
Spin FETLow power, suitable for
memory (nonvolatile info storage)
Low efficiency of spin injection
Summary of Emerging Technology pro/consSummary of Emerging Technology pro/cons
128
Conclusions
129
ConclusionsConclusions
HKMG: Continuous innovation has enabled EOT scaling to 9 Ao, however, new material could be needed for further EOT scaling.
New device structures (FinFET, Tri-gate) are replacing conventionalPlanar CMOS
Same performance at lower supply voltage
The combination of III-V channel materials with a multi-gate structure appears to be a promising direction.(Higher performance in lower operating voltage)
Recent advances in new channel material shows promising device performances but still far to cacth up Si-CMOS.
Device demonstration on emerging technologies (such as Tunnel FET, Junctionless FET, Carbon-based FET..) is increasing, But more time is needed for implementation of these technologies in future generation devices as mature technologies.