Functionally Linear Decomposition and Synthesis (FLDS) of Logic Circuits for FPGAs @Tomasz S. Czajkowski and Stephen D. Brown ,IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 12, DECEMBER 2008 Vishesh Kalra EE800 11089943
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Functionally Linear Decomposition and Synthesis (FLDS) of Logic Circuits for FPGAs
Functionally Linear Decomposition and Synthesis (FLDS) of Logic Circuits for FPGAs. Vishesh Kalra EE800 11089943. @Tomasz S. Czajkowski and Stephen D. Brown , IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 12, DECEMBER 2008. Earlier Method’s. - PowerPoint PPT Presentation
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Functionally Linear Decomposition and Synthesis (FLDS) of Logic Circuits for FPGAs
@Tomasz S. Czajkowski and Stephen D. Brown ,IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,
VOL. 27, NO. 12, DECEMBER 2008
Vishesh KalraEE800
11089943
Earlier Method’s
• Transforms >Logic function->Different Domains->Analysis• Binary Decision Diagrams(BDD)• Linear(OR/XOR) and Non Linear(AND/OR/NOT)• More Recently Davio and Shanon’s for XOR based
Decomposition
Introduction
• XOR based Logic Synthesis Approach. Methods >Gaussian Elimination >Binary Decision Diagrams to represent Logic functions
Concept of Linearity
• Concept of Linearity >F(x)=∑Gi(y)*Hi(x-y)
>X,Y are set of Variables(Y≤X). > ∑ represents XOR gate. >F is weighted sum of functions of Gi(Basis), where weighting factors are
determined by Hi(Selector).• This retains ability to synthesize original function
• Next Step-Try Express entire truth table as combination of these two vectors(Basis Vectors)
• Expressing each Column as h1iG1 (XOR)h2iG2
• To find h1i and h2i we solve linear equation
of the form Ax=B;
• A=[G1 G2] ,x=[h1i h2i]T , B=one of the other columns
Synthesis Continued
By inspection,h1i=1,h2i=1
Synthesis Results
• Next Step-To find Selector Functions that will identify the columns in which given Basis Vector appears.
• We look at the columns for which h1=1, i.e.
ab=01 and ab=11,• Selector Function for G1,i.e. H1=b and G2,i.e.
H2=a;
• Result=f=G1H1(XOR)G2H2= bc (xor) ad;
Multi Output Synthesis
f
g
abcd
e
f
g
f=(a+b)d (xor) abc
Ripple Carry Adder
Performance Considerations
• Some Problems with the above mentioned of merging Truth tables.
>Storing a Truth Table in memory will become complex for more than 20 variables.(Increase in memory)Another Solution Proposed – Gaussian-Jordan
Elimination instead of Gaussian Elimination.
Another Efficient Approach
FPGA Considerations
• Size Of LUT, used by an FPGA.
INPUT KEY(SIZE OF LUT)
HASH TABLE
Check if LUT is created or it’s compliment
Y
Instead of adding New LUT, wire or inverter is added thereby saving Area
N
Modifying FLDS for Reducing Area• We can Replace XOR gate by Or gate if
>Product of a pair of Basis Function or their respective selector functions is zero.
>Then XOR gate use to sum Basis-Selector Products can be replaced by an OR gate.
• 3 BASIS Functions i.e. G1=c , G2=D , G3=1, and it is found that selector functions for G1 and G2 are complements of each other and their product is 0.
• Therefore Unnecessary to add them using XOR.
Experiments
• Technique was tested on a set of 99 MCNC benchmarks, mapping each design into a network of four input LUT’s.
• On the 25 of the benchmarks (classified as XOR based Logic circuits), approach provides significant area savings.
Results-XOR Based Logic Circuits
• FLDS VS BDS-PGA >XOR based logic functions can be significantly reduced in size and logic depth 18.8% and 14.5% respectively• FLDS VS ABC >25.3% in area and 7.7% in depth.
Results-NON-XOR Based Logic Circuits
• FLDS VS ABC >ABC produces circuits with 6.2% lower area results and 16.5 lower depth.
Future Work Proposed by Authors
• Both Altera and Xilinx FPGA’s contain Carry chains to implement Fast Ripple Carry Adders.
• These Adders contain XOR gates outside LUT’s.
• It is possible to utilize these XOR gate outside LUT Network to further reduce area taken by logic function.