Version 1.1 FUJITSU SEMICONDUCTOR DATA SHEET 16-Bit Original Microcontroller CMOS F 2 MC-16LX MB90920 Series MB90F927/V920 ■ DESCRIPTIONS The FUJITSU MB90920 Series is a 16-bit general purpose high-capacity microcontroller designed for vehicle meter control applications etc. The instruction set retains the same AT architecture as the FUJITSU original F 2 MC-8L and F 2 MC-16L series, with further refinements including high-level language instructions, expanded addressing mode, enhanced (signed) multipler-divider computation and bit processing. In addition, a 32-bit accumulator is built in to enable long word processing. ■ FEATURES • Clock Built-in PLL clock frequency multiplication circuit. Selection of machine clocks (PLL clocks) is allowed among frequency division by 2 on oscillation clock and multiplication of 1 to 4 times of oscillation clock(for 4MHz oscillation clock, 4Hz to 16MHz). Operation by sub-clock(up to 50KHz : 100KHz oscillation clock divided by 2). (Continued) ■ PACKAGES Plastic QFP, 100-pin Plastic LQFP, 100-pin (FPT-100P-M06) (FPT-100P-M05) ˚
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FUJITSU SEMICONDUCTOR DATA SHEET · 2007-04-12 · FUJITSU SEMICONDUCTOR Version 1.1 DATA SHEET 16-Bit Original Microcontroller CMOS F2MC-16LX MB90920 Series MB90F927/V920 DESCRIPTIONS
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Version 1.1FUJITSU SEMICONDUCTORDATA SHEET
16-Bit Original MicrocontrollerCMOS
F2MC-16LX MB90920 SeriesMB90F927/V920
DESCRIPTIONSThe FUJITSU MB90920 Series is a 16-bit general purpose high-capacity microcontroller designed for vehiclemeter control applications etc.
The instruction set retains the same AT architecture as the FUJITSU original F2MC-8L and F2MC-16L series, withfurther refinements including high-level language instructions, expanded addressing mode, enhanced (signed)multipler-divider computation and bit processing.
In addition, a 32-bit accumulator is built in to enable long word processing.
FEATURES• Clock
Built-in PLL clock frequency multiplication circuit.Selection of machine clocks (PLL clocks) is allowed among frequency division by 2 on oscillation clock andmultiplication of 1 to 4 times of oscillation clock(for 4MHz oscillation clock, 4Hz to 16MHz).Operation by sub-clock(up to 50KHz : 100KHz oscillation clock divided by 2).
(Continued) PACKAGES
Plastic QFP, 100-pin Plastic LQFP, 100-pin
(FPT-100P-M06) (FPT-100P-M05)
1 30
31
50
14.00±0.20(.551±.008)
17.90±0.40(.705±.016)
INDEX
0.65(.026) 0.32±0.05(.013±.002)
M0.13(.005)0.17±0.06
(.007±.002)
0.10(.004)
Details of "A" part
(.035±.006)0.88±0.15
(.031±.008)0.80±0.20
0.25(.010)3.00
+0.35–0.20+.014–.008.118
(Mounting height)0~8˚
*
MB90920 Series
2
• 16-bit input capture (4 channels) Detects rising, falling, or both edges.16-bit capture register × 4Pin input edge detection latches the 16-bit free-run timer counter value, and generates an interrupt request.
• Real Time Watch timer (main clock) Operates directly from oscillator clock.Compensates for oscillator deviationRead/write enabled second/minute/hour/date registerSignal interrupt
• Delay interruptGenerates interrupt for task switching.Interruptions to CPU can be generated/deleted by software setting.
• External interrupts (8 channels) 8-channel independent operationInterrupt source setting available : “L” to “H” edge/ “H” to “L” edge/ “L” level/ “H” level.
• A/D converter10-bit or 8-bit resolution × 8 channels (input multiplexed) Conversion time : 2.6µs (at fCP = 16 MHz) External trigger startup available (P50/INT0/ADTG) Internal timer startup available (16-bit reload timer 1)
• UART(LIN/SCI) (2 channels) Equipped with full duplex double bufferClock-asynchronous or clock-synchronous serial transmission is available
• SIO (1 channels)Cock synchronized data transmission.LSB-first or MSB-first data transmission selection are available.
• CAN interface Conforms to CAN specifications version 2.0 Part A and B.Automatic resend in case of error.Automatic transfer in response to remote frame.16 prioritized message buffers for data and messages for data and IDMultiple message supportReceiving filter has flexible configuration : All bit compare/all bit mask/two partial bit masksSupports up to 1 MbpsCAN WAKEUP function (connects RX internally to INT0)
• LCD controller/driver (32 segment x 4 common) Segment driver and command driver with direct LCD panel (display) drive capability
• Low voltage/Program Looping detect resetAutomatic reset when low voltage is detectedProgram Looping detection function
(Continued)
MB90920 Series
(Continued)• Stepping motor controller (4 channels)
High current output for all channels × 4Synchronized 8/10-bit PWM for all channels × 2
• Sound generator 8-bit PWM signal mixed with tone frequency from 8-bit reload counter.PWM frequencies : 62.5 kHz, 31.2 kHz, 15.6 kHz, 7.8kHz (at fCP = 16MHz) Tone frequencies : 1/2 PWM frequency, divided by (reload frequency +1)
• Capable of changing input voltage for portAutomotive/CMOS-Schmitt (initial level is Automotive in single-chip mode)
• Flash memory security functionProtect the content of FLASH memory (FLASH memory device only)
• Clock supervisor functionMain clock or sub-clock is monitored independently, generates reset and set the detection flag when the clocksource under monitoring is stopped.
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MB90920 Series
4
PRODUCT LINEUP• MB90920 Series
Part number
Parameter
MB90F927 MB90V920
Configuration Flash ROM model Evaluation model
CPU F2MC-16LX CPU
Clock 2 systems / 1system (Select by option)
System clockOn-chip PLL clock multiplier type ( × 1, × 2, × 3, × 4, 1/2 when PLL stopped) Minimum instruction execution time 62.5 ns (with 4 MHz oscillation clock PLL × 4)
HANDLING DEVICESPrecautions for Handling Semiconductor Devices
• Strictly observe maximum rated voltages (prevent latchup)
When CMOS integrated circuit devices are subjected to applied voltages higher than VCC at input and outputpins other than medium- and high-withstand voltage pins, or to voltages lower than VSS, or when voltages inexcess of rated levels are applied between VCC and VSS, a phenomenon known as latchup can occur. In a latchupcondition, supply current can increase dramatically and may destroy semiconductor elements. In using semi-conductor devices, always take sufficient care to avoid exceeding maximum ratings.
Also care must be taken when power to analog systems is switched on or off, to ensure that the analog powersupply (AVCC, AVRH) , analog input and dedicated power supply for the high current output buffer pins (DVCC)do not exceed the digital power supply (VCC) .
Once the digital power supply (VCC) is switched on, the analog power (AVCC,AVRH) and dedicated power supplyfor the high current output buffer pins (DVCC) may be turned on in any sequence.
• Stable supply voltage
Even within the warranted operating range of VCC supply voltage, sudden fluctuations in supply voltage cancause abnormal operation. The recommended stability for ripple fluctuations (P-P values) at commercial fre-quencies (50 Hz to 60 Hz) should be within 10% of the standard VCC value, and voltage fluctuations that occurduring switching of power supplies etc. should be limited to transient fluctuation rates of 0.1 V/ms or less.
• Power-on procedures
In order to prevent abnormal operation of the internal built-in step-down circuits, voltage rise time during power-on should be attained within 50 µs (0.2 V to 2.7 V) .
• Treatment of unused pins
If unused input pins are left open, they may cause abnormal operation or latchup which may lead to permanentdamage to the semiconductor. Any such pins should be pulled up or pulled down through resistance of at least2 kΩ.
Any unused input/output pins should be left open in output status, or if found set to input status, they should betreated in the same way as input pins.
Any unused output pins should be left open.
• Treatment of A/D converter power supply pins
Even if the A/D converter is not used, pins should be connected so that AVCC = VCC, and AVSS = AVRH = VSS.
• Use of external clock signals
Even when an external clock is used, a stabilization period is required following a power-on reset or releasefrom sub clock mode or stop mode. Also, when an external clock is used it should drive only the X0 pin and theX1 pin should be left open, as shown in Figure 3.
X0
X1OPEN
MB90920 Series
Sample external clock connection
MB90920 Series
• Power supply pins
Devices are designed to prevent problems such as latchup when multiple VCC and VSS supply pins are used, byproviding internal connections between pins having the same potential. However, in order to reduce unwantedradiation, and to prevent abnormal operation of strobe signals due to rise in ground level, and to maintain totaloutput current ratings, all such pins should always be connected externally to power supplies and ground.
As shown in figure below, all VCC power supply pins must have the same potential. All VSS power supply pinsshould be handled in the same way. If there are multiple VCC or VSS systems, the device will not operate properlyeven within the warranted operating range.
In addition, care must be given to connecting the VCC and VSS pins of this device to a current source with as littleimpedance as possible. It is recommended that a bypass capacitor of 1.0 µF be connected between VCC andVSS as close to the pins as possible.
• Proper sequence of A/D converter power supply analog input
A/D converter power (AVCC, AVRH) and analog input (AN0-AN7) must be applied after the digital power supply(VCC) is switched on. When power is shut off, the A/D converter power supply and analog input must be cut offbefore the digital power supply is switched on (VCC) . In both power-on and shut-off, care should be taken thatAVRH does not exceed AVCC. Even when pins which double as analog input pins are used as input ports, besure that the input voltage does not exceed AVCC. (There is no problem if analog power supplies and digitalpower supplies are turned off and on at the same time.)
• Handling the power supply for high-current output buffer pins (DVCC, DVSS)
Always apply power to high-current output buffer pins (DVCC, DVSS) after the digital power supply (VCC) is turnedon. Also when switching power off, always shut off the power supply to the high-current output buffer pins (DVCC,DVSS) before switching off the digital power supply (VCC) . (There will be no problem if high-current output bufferpins and digital power supplies are turned off and on at the same time.)
Even when high-current output buffer pins are used as general purpose ports, the power for high current outputbuffer pins (DVCC, DVSS) should be applied to these pins.
• Pull-up/pull-down resistance
The MB90920 series does not support internal pull-up/pull-down resistance. If necessary, use external compo-nents.
VCC
VCCVCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
Power supply input pins (VCC/VSS)
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MB90920 Series
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• Precautions for when not using a sub clock signal.
If the X0A and X1A pins are not connected to an oscillator, apply pull-down treatment to the X0A pin and leavethe X1A pin open.
• Notes on during operation of PLL clock mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit evenwhen there is no external oscillator or external clock input is stopped. Performance of this operation, however,cannot be guaranteed.
Note : To select models without the ROM mirror function, see the “ROM Mirror Function Selection Module.” The image of the ROM data in the FF bank appears at the top of the 00 bank, in order to enable efficient use of small C compiler models. The lower 16-bit address for the FF bank will be assigned to the same address, so that tables in ROM can be referenced without declaring a “far” indication with the pointer. For example when accessing the address 00C000H, the actual access is to address FFC000H in ROM. Here the FF bank ROM area exceeds 48 KB, so that it is not possible to see the entire area in the 00 bank image. Therefore because the ROM data from FF4000H to FFFFFFH will appear in the image from 004000H to 00FFFFH, it is recommended that the ROM data table be stored in the area from FF4000H to FFFFFFH.
000000H
0000C0H
000100H
Address #2
Address #1
003900H
004000H
010000H
FFFFFFH
Single chip mode (with ROM mirror function)
Peripheral area
ROM area (FF bank image)
Register
ROM area
RAM area
Peripheral area
: Internal access memory
: Access prohibited
Parts No. Address #1 Address #2
MB90F927 FF0000H 001100H
MB90V920 FE0000H 001900H
MB90920 Series
I/O MAP• Other than CAN Interface
(Continued)
Address Register name Symbol Read/write Peripheral function Initial value
00H Port 0 data register PDR0 R/W Port 0 XXXX XXXX
01H Port 1 data register PDR1 R/W Port 1 - - XXXXXX
02H Port 2 data register PDR2 R/W Port 2 XXXXX X - -
03H Port 3 data register PDR3 R/W Port 3 XXXX XXXX
04H Port 4 data register PDR4 R/W Port 4 XXXX XXXX
05H Port 5 data register PDR5 R/W Port 5 XXXX XXXX
06H Port 6 data register PDR6 R/W Port 6 XXXX XXXX
07H Port 7 data register PDR7 R/W Port 7 XXXX XXXX
08H Port 8 data register PDR8 R/W Port 8 XXXX XXXX
09H Port 9 data register PDR9 R/W Port 9 - - - - - -XX
0AH to 0FH
(Disabled)
10H Port 0 direction register DDR0 R/W Port 0 0 0 0 0 0 0 0 0
11H Port 1 direction register DDR1 R/W Port 1 - - 0 0 0 0 0 0
12H Port 2 direction register DDR2 R/W Port 2 0 0 0 0 0 0 - -∗1
13H Port 3 direction register DDR3 R/W Port 3 0 0 0 0 0 0 0 0∗1
14H Port 4 direction register DDR4 R/W Port 4 0 0 0 0 0 0 0 0
15H Port 5 direction register DDR5 R/W Port 5 0 0 0 0 0 0 0 0
16H Port 6 direction register DDR6 R/W Port 6 0 0 0 0 0 0 0 0
17H Port 7 direction register DDR7 R/W Port 7 0 0 0 0 0 0 0 0
18H Port 8 direction register DDR8 R/W Port 8 0 0 0 0 0 0 0 0
19H Port 9 direction register DDR9 R/W Port 9 - - - - - - 0 0
1AH Analog input enable ADER R/W Port 6, A/D 1 1 1 1 1 1 1 1
1BH to 1FH
(Disabled)
20H A/D control status register lower ADCSL R/W
A/D converter
0 0 0 0 0 0 0 0
21H A/D control status register higher ADCSH R/W 0 0 0 0 0 0 0 0
• Addresses in the area 0000H to 00FFH are reserved for the principal functions of the MCU. Read accessattempts to reserved areas will result in an “X” value. Also, write access to reserved areas is prohibited.
Note:
*1: P22/SEG0~P27/SEG5 and P30/SEG6~P35/SEG11 initially will be LCD segments output as LCD outputcontrol register LOCR1 (58H) is “11111111” initially. To use DDR2 and DDR3 to control the port input/output,please set LOCR1 to “00000000” to disable the LCD segment output first.
3C00H to 3CFFH
Area reserved for CAN interface 0
3D00H to 3DFFH
(Disabled)
3E00H to 3EFFH
(Disabled)
Address Register name Symbol Read/write Peripheral function Initial value
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MB90920 Series
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• I/O Map for CAN Interface
(Continued)
Address Register name Symbol Read/write Initial value
: Compatible, with EI2OS stop function : Compatible : Compatible when interrupt sources sharing ICR are not in use
× : Not compatible
*1 : • Peripheral functions sharing the ICR register have the same interrupt level. • If peripheral functions sharing the ICR register are using expanded intelligent I/O services, one or the other
cannot be used.• When peripheral functions are sharing the ICR register and one specifies expanded intelligent I/O services,
the interrupt from the other function cannot be used.
*2 : Priority applies when interrupts of the same level are generated.
*3 : SIO and CAN1 will share IRQ3 in EVA chip.
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MB90920 Series
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PERIPHERAL FUNCTIONS1. I/O Ports
The I/O ports function is to send data from the CPU to be output from I/O pins and load input signals at the I/Opins into the CPU, according to the port data register (PDR) . Port input/output at I/O pins can be controlled inbit units by the port direction register (DDR) as required. The following list shows each of the functions as wellas the shared peripheral function for each port.
• Port 0 : General purpose I/O port, shared with peripheral functions (external interrupt/UART/PPG/LCD) • Port 1 : General purpose I/O port, shared with peripheral functions (PPG/reload timer/clock timer/ICU) • Port 2 : General purpose I/O port, shared with peripheral functions (LCD)• Port 3 : General purpose I/O port, shared with peripheral functions (LCD) • Port 4 : General purpose I/O port, shared with peripheral functions (LCD) • Port 5 : General purpose I/O port, shared with peripheral functions (External interrupt/CAN/SG/SIO) • Port 6 : General purpose I/O port, shared with peripheral functions (A/D converter) • Port 7 : General purpose I/O port, shared with peripheral functions (Stepping motor controller) • Port 8 : General purpose I/O port, shared with peripheral functions (Stepping motor controller) • Port 9 : General purpose I/O port, shared with peripheral functions (LCD, Sub-Clock input)
(1) List of Functions
(Continued)
Port Pin name Inputformat
Output for-mat Function
Port 0P00/SIN0/INT4/SEG24 to P07/PPG1/SEG31
CMOS (hysteresis)
(Automotive level*1)
CMOS
General purpose I/O port
Peripheral function
Port 1P10/PPG2 to P15/IN0
General purpose I/O port
Peripheral function
Port 2P22/SEG0 to P27/SEG5
General purpose I/O port
Peripheral function
Port 3P30/SEG6 to P37/SEG13
General purpose I/O port
Peripheral function
Port 4P40/SEG14 to P47/SEG21
General purpose I/O port
Peripheral function
Port 5P50/INT0 to P57/SGA
General purpose I/O port
Peripheral function
Port 6P60/AN0 to P67/AN7
AnalogCMOS
(hysteresis) (Automotive level*1)
General purpose I/O port
Peripheral function
Port 7P70/PWM1P0 to P77/PWM2M1
CMOS (hysteresis)
(Automotive level*1)
General purpose I/O port
Peripheral function
Port 8P80/PWM1P2 to P87/PWM2M3
General purpose I/O port
Peripheral function
Port 9P90/SEG22 to P93/X1A
General purpose I/O port
Peripheral function
MB90920 Series
(Continued)
*1: Range of input voltage.For ratings see “3. DC Characteristics” in “ ELECTRICAL CHARACTERISTICS”.
Note : Port 6 also functions as an analog input pin. When using this port as a general purpose port, always write “0” to the corresponding analog input enable register (ADER) bit. The ADER bit is initialized to “1” at reset.
Peripheral function inputPeripheral function output
Peripheral function output enabledPDR (Port data register)
DDR (Port direction register)
Inte
rnal
dat
a bu
s
PDR read
DDR read
Output latch
Directionlatch
PDR write
DDR write
Pin
Standby control (SPL = 1)or LCD output enabled
ADER
Port 6
PDR (Port data register)
DDR (Port direction register)
Analog input
RDR read
PDR writeInte
rnal
dat
a bu
s
Output latch
Pin
Directionlatch
DDR write
DDR readStandby control (SPL = 1)
MB90920 Series
2. Watchdog Timer/Time Base Timer/Watch Timer
The watchdog timer, timer base timer, and watch timer have the following circuit configuration.
• Watchdog timer : Watchdog counter, control register, watchdog reset circuit• Time base timer : 18-bit timer, interval interrupt control circuit• Watch timer : 15-bit timer, interval interrupt control circuit
(1) Watchdog timer function
The watchdog timer is composed of a 2-bit watchdog counter that uses the carry signal from the 18-bit timebase timer or 15-bit watch timer as a clock source, plus a control register and watchdog reset control circuit.
After startup, this function will reset the CPU if not cleared within a given time.
(2) Time base timer function
The time base timer is an 18-bit free-run counter (time base counter) synchronized with the internal count clock(base oscillator divided by 2) , with an interval timer function providing a selection of four interval times. Otherfunctions include a timer output for an oscillator stabilization wait time and clock feed to the watchdog timer orother operating clocks. Note that the time base timer uses the main clock regardless of the setting of the MCSbit or SCS bit in the CKSCR register.
(3) Watch timer function
The watch timer provides functions including a clock source for the watchdog timer, a sub clock base oscillatorstabilization wait timer, and an interval timer to generate an interrupt at fixed intervals. Note that the watch timeruses the sub clock regardless of the setting of the MCS bit or SCS bit in the CKSCR register.
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MB90920 Series
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• Block Diagram
TBTC
PONR
WRST
ERST
SRST
TBC0
TBR
TBIE
TBOF
TBC1
WT1
WT0
WTE
WTC
WDCS
SCE
WTC2
WTC0
WTR
WTIE
WTOF
WDTC
WDTC
AND
CLROF
CLR
211
213
216
218
TBTRES
28
29
210
211
212
213
214
216
WTRES
211 213 216 218
210 213 214 216
Q RS
ANDQ R
S
AND
Q RS
Main base oscillatordivided by 2
Selector
Clock input
Time base timer
Time baseinterrupt
Selector
Selector
2-bitcounter
Watchdog resetgenerator circuit To WDGRST
internal resetgenerator circuit
F2 M
C-1
6LX
bus
Power-on reset, sub-clock stop
SGW
Watch timer
Clock input
Clock interruptSub base oscillator divided by 4
From power-on generator
RST pin
From RST bit in STBYCregister
to
MB90920 Series
3. Input Capture
This circuit is composed of a 16-bit free-run timer and four 16-bit input capture circuits.
(1) Input capture ( × 4)
The input capture circuits consist of four independent external input pins and corresponding capture registersand control registers. When the specified edge of the external signal input (at the input pin) is detected, the valueof the 16-bit free-run timer is saved in the capture register, and at the same time an interrupt can also begenerated.• The valid edge (rising edge, falling edge, both edges) of the external signal can be selected.• The four input capture circuits can operate independently.• The interrupt can be generated from the valid edge of the external input signal.
(2) 16-bit free-run timer ( × 1)
The 16-bit free-run timer is composed of a 16-bit up-counter, control register, 16-bit compare register, andprescaler. The output values from this counter are used as the base time for the input capture circuits.• The counter clock operation can be selected from 8 options. The eight internal clock settings are φ, φ/2, φ/4,
φ/8, φ/16, φ/32, φ/64, φ/128 where φ represents the machine clock cycle.• Interrupts can be generated from overflow events, or from compare match events with the compare register.
(Compare match operation requires a mode setting.) • The counter value can be initialized to “0000H” by a reset, soft clear, or a compare match with the compare
The 16-bit reload timer can either count down in synchronization with three types of internal clock signals ininternal clock mode, or count down at the detection of the designated edge of an external signal. The user mayselect either function. This timer defines a transition from 0000H to FFFFH as an underflow event. Thus anunderflow occurs when counting from the value [Reload register setting + 1].
A selection of two counter operating modes are available. In reload mode, the counter is reset to the count valueand continues counting after an underflow, and in one-shot mode the count stops after an underflow. The countercan generate an interrupt when an underflow occurs, and is compatible with the expanded intelligent I/O services(EI2OS) .
(1) 16-bit Reload timer operating modes
(2) Internal clock mode
One of three input clocks is selected as the count clock, and can be used in one of the following operations.• Soft trigger operation
When “1” is written to the TRG bit in the timer control status register (TMCSR0/1) , the count operationstarts.Trigger input at the TRG bit is normally valid with an external trigger input, as well as an external gateinput.
• External trigger operationCount operation starts when a selected edge (rising, falling, both edges) is input at the TIN0/1 pin.
• External gate input operationCounting continues as long as the selected signal level (“L” or “H”) is input at the TIN0/1 pin.
(3) Event count mode (External clock mode)
In this mode a down count event occurs when a selected valid edge (rising, falling, both edges) is input at theTIN0/1 pin. This function can also be used as an interval timer when an external clock with a fixed period is used.
(4) Counter operation• Reload mode
In down count operation, when an underflow event (transition from “0000H” to “FFFFH”) occurs, the set countvalue is reloaded and count operation continues. The function can be used as an interval timer by generatingan interrupt request at each underflow event. Also, a toggle waveform that inverts at each underflow can beoutput from the TOT0/1 pin.
φ : Machine clock cycle. Figures in ( ) are values at machine clock frequency 16 MHz.
External clock 23/φ or greater (0.5 µs) 0.5 µs or greater
MB90920 Series
(5) One-shot mode
In down count operation, the count stops when an underflow event (transition from “0000H” to “FFFFH”) occurs.This function can generate an interrupt at each underflow. While the counter is operating, a rectangular waveform indicating that the count is in progress can be output form the TOT0 and TOT1 pins.
(6) Block diagram
UF
CLK
CLK
3
3 2
EN
CSL1 CSL0 OUTEOUTL RELD INTE UF CNTE TRGWOD2 WOD1 WOD0
P12/TIN0 *1
<P07/TIN1>
TMRLR0 *1
<TMRLR1>
TMR0 *1
<TMR1>
P11/TOT0 *1
<P06/TOT1>
Internal data bus
16-bit reload register
Reloadcontrol circuit
Reload signal
16-bit timer register (down counter)
Wait signalValid clockdecision circuit
Gate inputPrescaler
Machineclock Φ
To UART 0,1*1
<To A/D converter>
PinsOutput signal
generatorcircuitInverted
Clockselector
External clock
Inputcontrolcircuit
Pins
Function selection
Selectsignal
Operationcontrolcircuit
Interruptrequest signal#17 (11H)*2
<#28 (1CH)>
Timer control status register (TNGSR0)*1
<TNGSR1>
*1: Channel 0 and channel 1. Figures in < > are for channel 1.*2: Interrupt number
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MB90920 Series
44
5. Real Time Watch Timer
The real time watch timer is composed of a real time watch timer control register, sub second data register,second/minute/hour data registers, 1/2 clock divider, 21-bit prescaler and second/minute/hour counters. Be-cause the MCU oscillation frequency operates on a given real time watch timer operation, a 4 MHz frequencyis assumed. The real time watch timer operates as a real world timer and provides real world time information.
• Block diagram
INTE1 INT1
OEOE
WOT
IRQ#30
INTE2
STUPDT
INT2 INTE3 INT3 INT4 INT4
Main oscillator clock
1/2 clockdivider
22-bitSub-second counter
Sub secondregister
Secondcounter
Minutecounter
Hourcounter
6-bit 6-bit 5-bit
Second Interrupt
Daycounter
5-bit
INT5 INT5
1/2 clockdivider
22-bit
Second/minute/hour/day register
INT0 INT0
0.5-second InterruptMinute Interrupt
Hour InterruptDay Interrupt
MonthInterrupt
MB90920 Series
6. PPG Timer
The PPG timer consists of a prescaler, one 16-bit down-counter, 16-bit data register with buffer for period setting,and 16-bit compare register with buffer for duty setting, plus pin control circuits.
The timer can output pulses synchronized with an externally input soft trigger. The period and duty of the outputpulse can be adjusted by rewriting the values in the two 16-bit registers.
(1) PWM function
Programmable to output a pulse, synchronized with a trigger.
Can also be used as a D/A converter with an external circuit.
(2) One-shot function
Detects the edge of a trigger input, and outputs a single pulse.
(3) Pin control• Set to “1” at a duty match (priority) .• Reset to “0” at a counter borrow event• Has a fixed output mode to output a simple all “L” ( or “H”) signal.• Polarity can be specified
(4) 16-bit down counter• Select from four types of counter operation clocks. Four internal clocks (φ, φ/4, φ/16, φ/64) φ : Machine clock
cycles.• The counter value can be initialized to “FFFFH” at a reset or counter borrow event.
(5) Interrupt requests• Timer startup• Counter borrow event (period match) • Duty match event• Counter borrow event (period match) or duty match event
(6) Multiple channels can be set to start up at an external trigger, or to restart during operation.
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MB90920 Series
46
(7) Block diagram
1/1
1/4
1/16
1/64
CK
P05/SCK1/TRG
CMP
S Q
R
PCSR PDUT
Prescaler
Load
PSCT16-bit down counter
Start Borrow
PPG mask
Machine clock PPGoutput
Inversion bitEnable
Trigger inputInterrupt IRQ#25, 27, 29
Edge detection
Soft trigger
Interruptselection
MB90920 Series
7. Delayed Interrupt Generator Module
The delayed interrupt generator module is a module that generates interrupts for task switching. This modulemakes it possible to use software to generate/cancel interrupt requests to the F2MC-16LX CPU.
• Block diagram
F2MC-16LX bus
Delayed interrupt source generate/delete decoder
Source latch
47
MB90920 Series
48
8. DTP/External Interrupt Circuit
The DTP (Data transfer peripheral) /external interrupt circuit is located between an externally connected periph-eral device and the F2MC-16LX CPU and sends interrupt requests or data transfer requests generated from theperipheral device to the CPU, thereby generating external interrupt requests or starting the expanded intelligentI/O services (EI2OS) .
(1) DTP/external interrupt function
The DTP/external interrupt function uses a signal input from the DTP/external interrupt pin as a startup source.And it is accepted by the CPU by the same procedure as a normal hardware interrupt, and can generate anexternal interrupt or start the expanded intelligent I/O service (EI2OS) .
When the interrupt is accepted by the CPU, if the corresponding expanded intelligent I/O service (EI2OS) isprohibited the interrupt operates as an external interrupt function and branches to an interrupt routine. If theEI2OS is permitted the interrupt functions as a DTP function, using EI2OS for automatic data transfer, thenbranching to an interrupt routine after the completion of the specified number of data transfers.
ICR : Interrupt control register
Items External interrupt DTP function
Input pins 8 pins (P50/INT0/ADTG to P53/INT3, P00/SIN0/INT4/SEG24 to P03/INT7/SEG27)
Interrupt sources
Request level setting register (ELVR) sets the detection level, or selected edge for each pin
The 8/10-bit A/D converter has functions for using RC sequential comparator conversion format to convert analoginput voltage into 10-bit or 8-bit digital values. The input signal is selected from 8-channel analog input pins, andthe conversion start can be selected from three types : by software, 16-bit reload timer 1 or a trigger input froman external signal pin.
(1) 8/10-bit A/D converter functions
The A/D converter takes analog voltage signals (input voltage) input at analog input pins, and converts these todigital values, providing the following features.• Minimum conversion time is 1.9 µs (including sampling time) .• Minimum sampling time is 0.5 µs.• The conversion method is an RC sequential conversion in comparison with a sample hold circuit.• Either 10-bit or 8-bit resolution can be selected.• The analog input pin can select from 8 channels by a program setting.• At completion of A/D conversion, an interrupt request can be generated, or EI2OS can be started.• Because the conversion data protection function operates in an interrupt enabled state, no data is lost even
in continuous conversion.• The conversion start source may be selected from : software, 16-bit reload timer 1 (rising edge) , or external
trigger input (falling edge) .
Three conversion modes are available
Conversion mode Single conversion operation Scan conversion operation
Single conversion modeConverts the specified channel (1 channel only) one time, then stops.
Converts multiple consecutive channels (up to 8 channels may be specified) one time, then stops.
Continuous conversion mode
Converts the specified channel (1 channel only) repeatedly.
Converts multiple consecutive channels (up to 8 channels may be specified) repeatedly.
Stop conversion modeConverts the specified channel (1 channel only) one time, then pauses, waits until the next start is applied.
Converts multiple consecutive channels (up to 8 channels may be specified) , however pauses after conversion of each channel, waits until the next start is applied.
MB90920 Series
(2) Block diagram
AVCCAVRH
AN0AN1AN2AN3AN4AN5AN6AN7
MPX
ADCRH, L
ADCSH, L
P50/ADTG
AVSS
D/A converterIn
put c
ircui
t
Sequential comparatorregister
Comparator
Sample & hold circuit
F2M
C-1
6LX
bus
A/D data register
Dec
oder
A/D control status register, high
A/D control status register, low
Timer start16-bit reload timer 1
Trigger start Operating clock
Prescaler
Setting register, high
Analog input enable register
Setting register, low
φ
ADSRH, L
51
MB90920 Series
52
10. UART (LIN-SCI)
The UART is a general purpose serial data communication interface for synchronous communication, or asyn-chronous (start-stop synchronized) communication with external devices. Functions include normal bi-directionalfunctions, as well as master/slave type communication functions (multi-processor mode : master side onlysupported) , and special features for LIN-bus systems.
(1) UART Functions
The UART is a general purpose serial data communication interface for sending and receiving of serial datawith other CPU’s or peripheral devices, and provides the following functions.
Items Functions
Data buffer • Full duplex double buffer
Serial input• Perform oversampling 5 times and determine the received value by majority
decision of sampling time (asynchronous mode only)
Transfer modes• Clock synchronous (selecting start/stop synchronous or start/stop bit) • Clock asynchronous (start-stop can be used)
Baud rate• Dedicated baud-arte generator (The baud rate is consisted of 15-bit reload
counter.)• An external clock can be inputted and also be adjusted by reload counter.
Data length• 7-bit (other than synchronous or LIN mode) • 8-bit
Signal type • NRZ (Non return to zero)
Start bit timing • Synchronization to the falling edge of the start bit in the asynchronous mode
Detection of receiver error• Framing errors• Overrun errors• Parity errors (not enabled in multiprocessor mode)
• Transmit interrupt (transmit data empty) • Interrupt request to ICU (LIN Synch field detection: LSYN)• Both the transmission and reception support EI2OS
Master/slave typecommunication function (multi-processor mode)
• 1 (master) -to-n (slave) communication enabled (only master side supported) .
Synchronous mode • Master of slave funciton
Pin access • Capable of reading the state of serial I/O pin directly
LIN bus option
• Master device operation• Slave device operation• LIN Synch break detection• LIN Synch break generation• Detection of start/stop edges in LIN Synch field connected to input capture 0
and 1
Synchronous serial clock• Synchronous serial clock can be continously outputted to SCK pin for synchro-
nous communication with start/stop bits.
Clock delay option • Special synchronous clock mode for delaying clock (useful to SPI)
MB90920 Series
Note : The UART in clock synchronous transfer does not add start bits or stop bits, but transfers data only.
: Setting not available*1 : “+” indicates an address/data selection bit (A/D) for communication control.*2 : In receiving only one stop bit is detected.
Operating modeData length Synchronization/
AsynchronousStop bit length
Data bit formatNo parity Parity
0 Normal mode 7 or 8-bits Asynchronous 1-bit or 2-bit *2 LSB first
The CAN controller is a self-contained module within a 16-bit microcomputer (F2MC-16LX) . The CAN (controllerarea network) controller is the standard protocol for serial transmissions among automotive controllers and iswidely used in the industry.
(1) CAN controller features
The CAN controller has the following features.• Conforms to CAN specifications version 2.0 A and B.
Supports sending and receiving in standard frame and expanded frame format.• Supports data frame sending by means of remote frame receiving.• 16 sending/receiving message buffers
29-bit ID and 8-byte dataMulti-level message buffer configuration
• Supports full bit compare, full bit mask as well as partial bet mask filtering.Provides two receiving mask registers for either standard frame or expanded frame format.
• Bit speed programmable from 10 KB/s to 1 MB/s (at machine clock 16MHz) • CAN WAKE UP function
55
MB90920 Series
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(2) Block diagram
BTR
PSCPRPHRSJTOE
NS1,0NTNIE
HALTRSTS
CSR
RTEC
BVALR
TREQR
TCANR
TRTRR
RFWTR
TCR
TIER
RCR
RIER
RRTRR
ROVRR
AMSR
AMR0
AMR1
LEIR
IDR0 ~ 15,DLCR0 ~ 15,DTR0 ~ 15,
RAM
01
RBFX, TBFX, RDLC, TDLC, IDSEL
RBFX
IDSEL
TBFX
TBFX
PH1
RXFRMER
ACKER
BITER
ARBLOST
STFERRDLC
CRCER
TDLC
TDLC RDLC IDSEL
ARBLOST TXBITER, STFER,CRCER, FRMER,ACKER
SYNC, TSEG1, TSEG2
F2MC-16LX busTQ (operating clock)
Machineclock
Prescaler 1-to-64frequency divider
Bit timing generator
Node status changeinterrupt generator
Node statuschange interrupt
Busstate
machine
IDLE, SUSPND, TX, RX, ERR,
OVRLD
Errorcontrol
Send/receivesequencer
TBFxclear Send buffer
decision Datacounter
Receivingfilter
control
Errorframe
generator
Overloadframe
generator
Outputdriver
Send shiftregister
Stuffing
TBFx, set, clear CRCgenerator
ACKgeneratorSending completed
interrupt generator
Sendingcompletedinterrupt
RBFx, set CRC generatorerror checkReceiving completed
interrupt generator
Receivingcompletedinterrupt
RBFx, TBFx, set clearReceiving
shift register Destuffing/stuffing
error checkRBFxset
Arbitrationcheck
Bit errorcheckReceiving
filterReceiving bufferx
decision Acknowledge errorcheck
Form errorcheck
Inputlatch
RAM addressgenerator
MB90920 Series
12. LCD Controller/Driver
The LCD controller/driver has a built-in 16 × 8-bit display data memory, and controls the LCD display by meansof four common outputs and 32 segment outputs. A selection of three duty outputs are available. This block candrive an LCD (liquid crystal display) panel directly.
(1) LCD controller/driver functions
The LCD controller/driver provides functions for directly displaying the contents of display data memory (displayRAM) on the LCD panel by means of segment output and common output.• LCD drive voltage divider resistance is built-in. External divider resistance can also be connected.• Up to 4 common outputs (COM0 to COM3) and 32 segment outputs (SEG0 to SEG31) can be used.• 16-byte display data memory (display RAM) is built-in.• The duty can be selected at 1/2, 1/3, 1/4 (limited by bias setting) .• Drives the LCD directly.
: Recommended mode × : Use prohibited
Note : When the SEG0 to SEG31 pins have been selected as general purpose ports by the LCRH, LOCR0, LOCR1 setting, they cannot be used for segment output.
The Low voltage detection reset circuit is a function that monitors power supply voltage in order to detect whena voltage drops below a given voltage level. When a low voltage condition is detected, an internal reset signalis generated.
The Program Looping detection reset circuit is a count clock with a 20-bit counter that generates an internalreset signal if not cleared within a given time after startup.
(1) Low voltage detection reset circuit
When a low voltage condition is detected, the low voltage detection flag (LVRC : LVRF) is set to “1” and aninternal reset signal is output.
Because the low voltage detection circuit continues to operate even in stop mode, detection of a low voltagecondition generates an internal reset and releases stop mode.
During an internal RAM write cycle, an internal reset is generated after the completion of writing. During theoutput of this internal reset, the reset output from the low voltage detection circuit is suppressed.
(2) Program Looping detection reset circuit
The Program Looping detection reset circuit is a counter that prevents program looping. The counter startsautomatically after a power-on reset, and must be continually cleared within a given time. If the given time intervalelapses and the counter has not been cleared, a cause such as infinite program looping is assumed and aninternal reset signal is generated. The internal reset generated form the Program Looping detection circuit hasa width of 5 machine cycles.
* : This value assumes an oscillation clock waveform of 4 MHz.During recovery from standby mode the detection period is the maximum interval plus 20 µs.
This circuit does not operate in modes where CPU operation is stopped.
The Program Looping detection reset circuit counter is cleared under any of the following conditions.
1. Writing “0” to the LVRC register CL bit
2. Internal reset
3. Main oscillation clock stop
4. Transition to sleep mode
5. Transition to time base timer mode or clock mode
Low voltage/CPU operation detection reset control register (LVRC)
Internal data bus
ReservedReservedReservedReserved
MB90920 Series
14. Stepping Motor Controller
The stepping motor controller is composed of two PWM pulse generators, four motor drivers and selector logiccircuits.
The four motor drivers have a high output drive capacity and can be directly connected to the four ends of twomotor coils. They are designed to operate together with the PWM pulse generators and selector logic circuitsto control motor rotation. A synchronization mechanism assures synchronization of the two PWM pulse gener-ators.
• Block diagram
P1 P0
SC
OE1
OE2
PWM1Pn
PWM2Pn
PWM1Mn
PWM2MnCE
CK
EN
CK
ENPWM
PWM
BS n : 0 ~ 3
Machine clock
Prescaler
Output enable
PWM1 pulse generator Selector
PWM1 compare register PWM1 selector register
PWM2 pulse generator
Output enable
Selector
Load
PWM2 compare register PWM2 select register
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MB90920 Series
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15. Sound Generator
The sound generator is composed of a sound control register, frequency data register, amplitude data register,decrement grade register, tone count register, PWM pulse generator, frequency counter, decrement counter,and tone pulse counter.
• Block diagram
S1 S0
TONE OE2
INTE INT ST
1/d
DEC
OE1
COEN
PWM
CI
DEC
CICOEN
CICOEN
COEN
DEN
Q
SGA
SGO
IRQ#34
OE1
OE2
Clock input
Prescaler 8-bit PWMpulse generator
Frequencycounter
Toggleflip-flop
ReloadReload
Amplitude dataregister
Frequency dataregister
Decrementcounter
Decrement graderegister
Blend
Tone pulsecounter
Tone countregister
MB90920 Series
16. Serial I/O interface
The serial I/O interface is a serial I/O interface with an 8-bit channel configuration that is used to transfer databy clock synchronization.
Features of the serial I/O interface :• Converts 8-bit parallel data to serial and outputs the serial data, converts input serial data to parallel and
stores the data• The shift clock can be selected from five internal clocks and one external clock• Generated interrupt at end of serial data transfer if the serial I/O interrupt request is enabled• The data shift direction (transfer direction) can be selected as either LSB first or MSB first• The serial I/O can control input and output of the shift clock and can output the internal shift clock
SDR (Serial data register)
SO
Control circuit Shift clock counter
(MSB first) D0 to D7Select transfer directionD7 to D0 (LSB first)
SMD1SMD2 SMD0 SIE SIR BUSY STOP STRT MODE BDS SOE SCOE
SCLK
SI
Read
Write
Internal clock
IRQ # 14
Internal data bus
Initial value
012
Internal data bus
63
MB90920 Series
64
17. Clock Supervisor
The clock supervisor checks the oscillation of the main clock or sub-clock. When the main clock or sub-clockstops due to some breakdowns (20µs to 80µs: when the main clock is used, 160µs to 640µs: when the subclock is used), the control circuit of the clock supervisor switches the clock source to build-in CR oscillation clock,sets the detection flag, and generates reset.
Main clock and sub-clock monitor function can be enabled or disabled independently.
The clock monitor function will be disabled automatically once the device changes to stop mode, and will beenabled automatically if the monitor funciton is enabled before the stop mode.
• Block diagram
1/2
Internal bus
Clock Supervisor control register (CSVCR)
Control circuit Internal reset
Internal main clock
Internal sub clock
Main clock selector
Sub clock selector
Sub clock supervisor
Main clock supervisor
CR oscillation circuit
Enable
DetectionEnable
EnableDetection
Sub selection
Main selection
CR oscillation clock
Main clock
Sub clock
MB90920 Series
18. Address Match Detect Function
If the address setting is the same as the address detection register, an INT9 instruction is executed. Theintegrated address match detection function can be implemented by processing the INT9 interrupt serviceroutine.
Two address registers are used, each with its own compare enable bit. When there is a match between theaddress register and program counter, and the compare enable bit is set to “1” , the INT9 instruction is forciblyexecuted by the CPU.
• Block diagram
Address latch
Com
pare
Address detection register
Enable bit
F2MC-16LXCPU core
F2MC-16LX bus
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MB90920 Series
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19. ROM Mirror Function Select Module
The ROM mirror function select module uses a select register setting to enable the contents of ROM allocatedto the FF bank to be viewed in the 00 bank.
• Block diagram
ROM
F2MC-16LX bus
ROM mirror function select register
Address area
FF bank 00 bank
MB90920 Series
ELECTRICAL CHARACTERISTICS1. Absolute Maximum Ratings
*1 : The parameter is based on VSS = AVSS = DVSS = 0.0 V.
*2 : AVCC, AVRH and DVCC shall never exceed VCC.Also, AVRH shall never exceed AVCC.
*3 : The maximum current to/from and input is limited by some means with extenal components, the ICLAMP rating supersedes the VI rating.
*4 : Maximum output current is defined as the peak value of the current of any one of the corresponding pins.
*5 : Average output current is defined as the value of the average current flowing over 100 ms at any one of the corresponding pins. The “average value” can be calculated from the formula of “operating current” times “operating factor”.
(Continued)
Parameter SymbolRating
Unit RemarksMin Max
Power supply voltage*1
VCC VSS − 0.3 VSS + 6.0 V
AVCC VSS − 0.3 VSS + 6.0 V AVCC = VCC*2
AVRH VSS − 0.3 VSS + 6.0 V AVCC ≥ AVRH*2
DVCC VSS − 0.3 VSS + 6.0 V DVCC = VCC*2
Input voltage*1 VI VSS − 0.3 VCC + 0.3 V *3
Output voltage*1 VO VSS − 0.3 VCC + 0.3 V
Maximum clamp current ICLAMP − 400 + 400 µA *7
Total maximum clamp current Σ| ICLAMP | 4 mA *7
“L”level maximum output current*4
IOL1 15 mA Other than P70 to P77, and P80 to P87
IOL2 40 mA P70 to 77, P80 to87
“L”level average output current*5
IOLAV1 4 mA Other than P70 to P77, and P80 to P87
IOLAV2 30 mA P70 to 77, P80 to 87
“L”level maximum total output current
ΣIOL1 100 mA Other than P70 to P77, and P80 to P87
ΣIOL2 330 mA P70 to 77, P80 to 87
“L”level average total output current
ΣIOLAV1 50 mA Other than P70 to P77, and P80 to P87
ΣIOLAV2 250 mA P70 to 77, P80 to 87
“H”level maximum output current
IOH1*4 − 15 mA Other than P70 to P77, and P80 to P87
IOH2*4 − 40 mA P70 to 77, P80 to 87
“H”level average output current
IOHAV1*5 − 4 mA Other than P70 to P77, and P80 to P87
IOHAV2*5 − 30 mA P70 to 77, P80 to 87
“H”level maximum total output current
ΣIOH1 − 100 mA Other than P70 to P77, and P80 to P87
ΣIOH2 − 330 mA P70 to 77, and P80 to 87
“H”level average total output current
ΣIOHAV1*6 − 50 mA Other than P70 to P77, and P80 to P87
ΣIOHAV2*6 − 250 mA P70 to 77, P80 to 87
Power consumption PD 500 mW
Operating temperature TA −40 +105 °C
Storage temperature TSTG −55 +150 °C
67
MB90920 Series
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(Continued)
*6 : Average total output current is defined as the value of the average current flowing over 100 ms at all of the corresponding pins. The “average value” can be calculated from the formula of “operating current” times “ operating factor”.
*7 : • Applicable to pins : P10 to P15, P50 to P57, P70 to P77, P80 to P87• Use within recommended operating conditions.• Use at DC voltage (current) .• The +B signal should always be applied with a limiting resistance placed between the +B signal and the
microcontroller.• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affectother devices.
• Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supplyis provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and theresulting supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.• Note that analog system input/output pins (LCD drive pins, comparator input pins, etc.) cannot accept +B
signal input.• Sample recommended circuits :
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
* : For smoothing capacitor Cs connections, see the illustration below.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of thesemiconductor device. All of the device’s electrical characteristics are warranted when the device isoperated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operationoutside these ranges may adversely affect reliability and could result in device failure.No warranty is made with respect to uses, operating conditions, or combinations not represented onthe data sheet. Users considering application outside the listed conditions are advised to contact theirFUJITSU representatives beforehand.
Parameter SymbolValue
Unit RemarksMin Max
Power supplyvoltage
VCC
AVCC
DVCC
3.7 5.5 V (MB90F927) Low voltage detection reset starts to work when power supply voltage is 4.0 V ± 0.3 V.
4.3 5.5 VHolding stop operation status (MB90F927)
Smoothing capacitor*
CS 0.1 1.0 µFUse a ceramic capacitor or other capacitor of equivalent frequency characteristics. A bypass capacitor on the VCC pin should have a capacitance greater than Cs.
Operatingtemperature
TA −40 +105 °C
C
CSVSS DVSS AVSS
• C pin connection
69
MB90920 Series
70
3. DC Characteristics (VCC = 5.0 V±10%, VSS = DVSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
*3 : Supply current values assume external clock feed from the X1 pin and X1A pin. Users must be aware that supply current levels differ depending on whether an external clock or oscillator is used.
*4 : Defined as maximum variation in VOH2/VOL2 with all channel 0 PWM1P0/PWM1M0/PWM2P0/PWM2M0 simul-taneously ON. Similarly for other channels.
Parameter Symbol Pin name ConditionsValue
Unit RemarksMin Typ Max
Large current output drive capacity variation 1
∆VOH2
PWM1Pn, PWM1Mn, PWM2Pn, PWM2Mn, n = 0 to 3
VCC = 4.5 V IOH = 30.0 mA VOH2 maximum variation
0 90 mV *4
Large current output drive capacity variation 2
∆VOL2
PWM1Pn, PWM1Mn, PWM2Pn, PWM2Mn, n = 0 to 3
VCC = 4.5 V IOH = 30.0 mA VOL2 maximum variation
0 90 mV *4
LCD internal dividerresistance
RLCD
V0 to V1, V1 to V2, V2 to V3
50 100 200 kΩ
COM0 to COM3output imped-ance
RVCOMCOMn (n = 0 to 3)
2.5 kΩ
SEG0 to SEG31output imped-ance
RVSEGSEGn (n = 00 to 31)
15 kΩ
LCD leakagecurrent
ILCDC
V0 to V3COMm (m = 0 to 3) SEGn (n = 00 to 31)
− 5.0 + 5.0 µA
MB90920 Series
4. AC Characteristics
(1) Clock timing (VCC = 5.0 V±10%, VSS = DVSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter Symbol Pin name Condi-tions
ValueUnit Remarks
Min Typ Max
Base oscillation clock frequency
FC X0, X1
4 12 MHz 1/2 when PLL stops.
4 12 MHz PLL x 1
4 8 MHz PLL x 2
4 5.33 MHz PLL x 3
4 4 MHz PLL x 4
FLC X0A, X1A 32.768 kHz
Base oscillation clock cycle time
tCYL X0, X1 250 ns
tLCYL X0A, X1A 30.5 µ s
Input clock pulse width
PWH, PWL X0 10 nsUse duty ratio of 40 to 60% as a guideline
PWLH, PWLL X0A 15.2 µ s
Input clockrise, fall time
tcr, tcf X0, X0A 5 nsWith external clock signal
Input operating clock frequency
FCP 2 16 MHzUsing main clock, PLL clock
FLCP 8.192 kHz Using sub clock
Input operating clock cycle time
tCP 62.5 — 500 nsUsing main clock, PLL clock
tLCP 122.1 µ s Using sub clock
X0
tcf tcr
0.8 VCC
0.2 VCC
PWL
tCYL
PWH
X0A
tLCYL
tcf tcr
0.8 VCC
0.2 VCC
PWLH PWLL
• X0 clock timing
• X0A clock timing
73
MB90920 Series
74
• Range of warranted operation
The MB90F927enters reset mode at supply voltage below 4 V ± 0.3 V.
1642
5.5
3.7
Relation between internal operating clock frequency and supply voltage
MB90F927guaranteed operation range
Sup
ply
volta
ge V
CC (
V)
Guaranteed PLL operation range
Internal clock frequency fCP (MHz)
4.0
Guaranteed A/D Converteroperation range
168
16
8
Guaranteed oscillation frequency range
Inte
rnal
clo
ckfc
p (M
Hz)
External clock Fc (MHz)
12
2
4
4 12
x 1/2(PLL off)
x 1
x 2 x 4 x3
MB90920 Series
AC ratings are defined for the following measurement reference voltage values:
0.8 VCC
0.5 VCC
2.4 V
0.8 V
• Input signal waveform
Hysteresis input pin
• Output signal waveform
Output pin
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MB90920 Series
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(2) Reset input (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
*: Oscillator oscillation time is the time to reach 90% amplitude. For a crystal oscillator, this is a few to several hundred ms; for a FAR/ceramic oscillator, this is several hundred ms to a few ms, and for an external clock this is 100 µs.
Note : tCP : See “ (1) Clock input timing”.
Parameter Symbol Pin name ConditionsValue
Unit RemarksMin Max
Reset input time tRSTL RST
16 tCP ns In normal operation
Oscillator oscillation time* + 16 tCP
ms
In stop mode,sub clock mode,sub sleep mode, watch mode
RST
0.5 VCC
tRSTL
0.5 VCC
• Under normal operation
RST
X0
16 tcp
tRSTL
0.5 Vcc 0.5 Vcc
Internaloperationclock
Internalreset
90 % ofamplitude
Oscillatoroscillation time
Oscillator stabilization wait time
Execution of the instruction
• In stop mode, sub clock mode, sub sleep mode, watch mode
MB90920 Series
(3) Power-on reset, power on conditions (VSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter Symbol Pin name Conditions
ValueUnit Remarks
Min Max
Power supply rise time tR
VCC
0.05 30 ms
Power supply start voltage VOFF 0.2 V
Power supply attained voltage VON 2.7 V
Power supply cutoff time tOFF 50 ms For repeat operation
VCC
0 V
VCC
VSS
5.0 V
tR
tOFF
2.7 V
0.2 V 0.2 V0.2 V
Extreme variations in voltage supply may activate a power-on reset. As the illustration below shows, when varying supply voltage during operation the use of a smoothvoltage rise with suppressed fluctuation is recommended. Also in this situation, the PLL clock on thedevice should not be used, however it is permissible to use the PLL clock during a voltage drop of1V/s or less.
3.0 V
RAM data hold
A rise slope of 50 mV orless is recommended
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MB90920 Series
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(4) UART0, UART1 and SIO timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Notes : • AC ratings are for CLK synchronous mode.• CL is load capacitance connected to pin during testing.• tCP : See “ (1) Clock timing”.
SCK fall to SOT delay time tSLOVSCK0, SCK1, SCKSOT0, SOT1, SO
150 ns
Valid SIN to SCK rise tIVSH SCK0, SCK1, SCKSIN0, SIN1, SI
60 ns
SCK rise to valid SIN hold time tSHIX 60 ns
• Internal shift clock mode
• External shift clock mode
SCK
SOT
SIN
tSCYC
tSLOV
tIVSH tSHIX
0.8 V 0.8 V
2.4 V
2.4 V
0.8 V
0.8 VCC
0.5 VCC
0.8 VCC
0.5 VCC
SCK
SOT
SIN
tSLSH tSHSL
tSLOV
tIVSH tSHIX
0.5 VCC 0.5 VCC
0.8 VCC 0.8 VCC
2.4 V
0.8 V
0.8 VCC
0.5 VCC
0.8 VCC
0.5 VCC
MB90920 Series
(5) Timer input timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Note : tCP : See “ (1) Clock timing”.
(6) Trigger input timing (VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Note : tCP : See “ (1) Clock timing”.
Parameter Symbol Pin name ConditionsValue
Unit RemarksMin Max
Input pulse widthtTIWH
tTIWL
TIN0, TIN1, IN0, IN1, IN2, IN3,
4 tCP ns
Parameter Symbol Pin name ConditionsValue
Unit RemarksMin Max
Input pulse widthtTRGH, tTRGL
INT0 to INT7 5 tCP ns Under normal operation
1 µ s In stop mode
TIN0 ∼ TIN1IN0 ∼ IN3
0.8 VCC 0.8 VCC
0.5 VCC 0.5 VCC
tTIWH tTIWL
• Timer input timing
INT0 ∼ INT7 0.8 VCC 0.8 VCC
0.5 VCC 0.5 VCC
tTRGH tTRGL
• Trigger input timing
79
MB90920 Series
80
(7) Low voltage detection (VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter Symbol Pin name ConditionsValue
Unit RemarksMin Typ Max
Detection voltage VDL VCC 3.7 4.0 4.3 VDuring voltage drop
Hysteresis width VHYS VCC 0.1 VDuring voltage rise
Power supply voltage fluctuation ratio
dV/dt VCC − 0.1 0.02 V/µs
Detection delay time td 35 µs
VHYS
dV
dt
Vni
td
VCC
td
Internal reset
MB90920 Series
5. A/D Conversion Block
(1) Electrical Characteristics (VCC = AVCC = 5.0 V±10%, 3.0V ≤ AVRH-AVss,VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
*1 : Defined as supply current (when VCC = AVCC = AVRH = 5.0 V) with A/D converter not operating, and CPU in stop mode.
Parameter Symbol Pin nameValue
Unit RemarksMin Typ Max
Resolution 10 bit
Total error ± 3.0 LSB
Non-linear error ± 2.5 LSB
Differential linear error ± 1.9 LSB
Zero transition voltage VOT AN0 to AN7AVSS
− 1.5 LSBAVSS
+ 0.5 LSBAVSS
+ 2.5 LSBV 1 LSB =
(AVRH − AVSS) / 1024Full scale transition
voltageVFST AN0 to AN7
AVRH − 3.5 LSB
AVRH − 1.5 LSB
AVRH + 0.5 LSB
V
Sampling time tSMP 1.4
16,500 µs4.5V ≤ AVcc ≤ 5.5V
2.0 4.0V ≤ AVcc ≤ 4.5V
Compare time tCMP 0.5
µ s4.5V ≤ AVcc ≤ 5.5V
1.2 4.0V ≤ AVcc ≤ 4.5V
Analog portinput current
IAIN AN0 to AN7 -0.3 +0.3 µA
Analog input voltage VAIN AN0 to AN7 AVss AVRH V
Reference voltage AVRH AVRH AVss+2.7 AVCC V
Power supply currentIA
AVCC 3.5 7.5 mA
IAH 5 µA *1
Reference voltage feed current
IR AVRH 600 900 µA VAVRH = 5.0 V
IRH AVRH 5 µA *1
Inter-channel variation — AN0 to AN7 4 LSB
81
MB90920 Series
82
• Notes of the external impedance of the analog input and its sampling time • A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting A/D conversion presicion.
(Continued) • To satisfy the A/D conversion precision standard, consider the relationship between the external impedance
and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value.
• If the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
• About errorsAs |AVRH| becomes smaller, values of relative errors grow larger.
100
90
80
70
60
50
40
30
20
10
00 5 10 15 20 25 30 35
MB90F927
MB90V92520
18
16
14
12
10
8
6
4
2
00 1 2 3 4 5 6 87
MB90F927
MB90V925
(External impedance = 0 kΩ to 100 kΩ)
Ext
erna
l im
ped
ance
[kΩ
]
Minimum sampling time [µs]
(External impedance = 0 kΩ to 20 kΩ)
Ext
erna
l im
peda
nce
[kΩ
] Minimum sampling time [µs]
• The relationship between the external impedance and minimum sampling time
20
18
16
14
12
10
8
6
4
2
00 1 2 3 4 5 6 87
MB90F927
MB90V925
(External impedance = 0 kΩ to 20 kΩ)
Ext
erna
l im
peda
nce
[kΩ
]
Minimum sampling time [µs]
100
90
80
70
60
50
40
30
20
10
00 5 10 15 20 25 30 35
MB90F927
MB90V925
(External impedance = 0 kΩ to 100 kΩ)
Ext
erna
l im
peda
nce
[kΩ
]
Minimum sampling time [µs]
• At 4.5V ≤ AVcc ≤ 5.5V
• At 4.0V ≤ AVcc ≤ 4.5V
83
MB90920 Series
(2) Definition of terms
Resolution : Analog changes that are identifiable with the A/D converter.
Linearity error : The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “000000 0001”) with the full-scale transition point (“11 1111 1110” ↔ “11 1111 1111”) from actualconversion characteristics.
Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from thetheoretical value.
Total error : The total error is defined as a difference between the actual value and the theoretical value,which includes zero-transition error/full-scale transition error and linearity error.
(Continued)
(Continued)
Total error
Actual conversion value
Analog input
Total error for digital output N = VNT − 1 LSB × (N − 1) + 0.5 LSB
1 LSB[LSB]
1 LSB = (Theoretical value) AVRH − AVss1024
[V]
VOT (Theoretical value) = AVss + 0.5 LSB [V]
VFST (Theoretical value) = AVRH − 1.5 LSB [V]
VNT : Voltage at a transition of digital output from (N - 1) to N
Actual conversion value
Theoreticalcharacteristics
(Measured value)
Dig
ital o
utpu
t
AVRss AVRH
3FF3FE3FD
004
003
002
001
0.5 LSB
VNT
1 LSB x (N - 1) + 0.5 LSB
0.5 LSB
Linearity error Differential linearity error
MB90920 Series
85
(Continued)
Plastic LQFP, 100-pin (FPT-100P-M05)
Note 1) * : These dimensions do not include resin protrusion.Note 2) Pins width and pins thickness include plating thickness.Note 3) Pins width do not include tie bar cutting remainder.
Dimensions in mm (inches) Note : The values in parentheses are reference values.
C 2003 FUJITSU LIMITED F100007S-c-4-6
14.00±0.10(.551±.004)SQ
16.00±0.20(.630±.008)SQ
1 25
26
51
76 50
75
100
0.50(.020) 0.20±0.05(.008±.002)
M0.08(.003)0.145±0.055
(.0057±.0022)
0.08(.003)
"A"
INDEX.059 –.004
+.008–0.10+0.20
1.50(Mounting height)
0˚~8˚
0.50±0.20(.020±.008)0.60±0.15
(.024±.006)
0.25(.010)
0.10±0.10(.004±.004)
Details of "A" part
(Stand off)
*
MB90920 Series
FUJITSU LIMITEDFor further information please contact:
FUJITSU MICROELECTRONICS AMERICA, INC.1250 E. Arques Avenue, M/S 333Sunnyvale, CA 94088-3470, U.S.A.Tel: +1-408-737-5600Fax: +1-408-737-5999http://www.fma.fujitsu.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbHAm Siebenstein 6-10,D-63303 Dreieich-Buchschlag,GermanyTel: +49-6103-690-0Fax: +49-6103-690-122http://www.fme.fujitsu.com/
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