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FUJITSU MICROELECTRONICSDATA SHEET DS07-13716-3E
16-bit Proprietary MicrocontrollerCMOS
F2MC-16LX MB90440G Series
MB90443G/F443G/V440G DESCRIPTION
The MB90440G series with FULL-CAN and FLASH ROM is a line of general-purpose, Fujitsu Microelectronics16-bit microcontrollers specially designed for automotive and industrial applications. Its main features are threeon board CAN Interfaces (generic type) , which conform to V2.0 Part A and Part B, supporting very flexiblemessage buffering. Thus, more functions than a normal full CAN approach is available.
While inheriting the AT architecture of the F2MC* family, the instruction set for the F2MC-16LX CPU core incorpo-rates additional instructions for high-level languages, supports extended addressing modes, and contains en-hanced multiplication and division instructions as well as a substantial collection of improved bit manipulationinstructions. In addition, the MB90440G series has as on-chip 32-bit accumulator, which enables processing oflong-word data.
The peripheral resources integrated in the MB90440G series include; an 8/10-bit A/D converter, UARTs (SCI) ,I/O extended serial interface, 8/16-bit PPG timer, input/output timer (input capture (ICU) , output compare (OCU) ) .
* : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
• Enhanced interrupt function : 8 priority levels programmable and 34 causes
• Automatic data transmission function independent of CPU operation
Extended intelligent I/O service function (EI2OS)
• Internal ROM size and type
FLASH ROM : 128 Kbytes Internal RAM size : 6 Kbyte and 14 Kbyte (evaluation chip)
• FLASH ROM
Supports automatic programming function, Embedded Algorithm Writing command/erase command/erase suspend and resume command Algorithms completion flag Hardwire reset vector to show the fixed boot code sector Can be erased by each sector Sector protection by external programming voltage
500 K/1 M/2 Mbps (synchronous) at System clock = 16 MHz
UART1 (SCI)
Full duplex double bufferAsynchronized (start/stop bits synchronized) and CLK-synchronous communicationBaud rate : 601 bps to 250 kbps (asynchronous)
31.25 kbps to 2 Mbps (synchronous)
Serial IO
Transfer can be started from MSB or LSBSupports internal clock synchronized transfer and external clock synchronized transferSupports positive-edge and negative-edge clock synchronizationBaud rate : 31.25 K/62.5 K/125 K/500 K/1 M/2 Mbps at System clock = 16 MHz
8/10 bitA/D Converter
10-bit or 8-bit resolution8 input channelsConversion time : 6.12 µs (per one channel)
16-bit Reload Timer (2 channels)
Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = System clock frequency) Supports External Event Count function
16-bit Free-run Timer
Signals an interrupt during overflowSupports Timer Clear during a match with Output Compare (Channel 0) Operation clock freq. : fsys/22, fsys/24, fsys/26, fsys/28 (fsys = System clock freq.)
16-bit Output Compare (4 channels)
Signals an interrupt during a match with 16-bit Free-run TimerFour 16-bit compare registersA pair of compare registers can be used to generate an output signal
Supports 8-bit and 16-bit operation modesEight 8-bit reload countersEight 8-bit reload registers for L pulse widthEight 8-bit reload registers for H pulse widthA pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler plus 8-bit reload counter4 output pinsOperation clock frequency. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 µs@fosc = 4 MHz (fsys = System clock frequency, fosc = Oscillation clock frequency)
CAN Interface
3 channels :
Conforms to CAN Specification Version 2.0 Part A and BAutomatic re-transmission in case of errorAutomatic transmission responding to Remote FrameSupports prioritized 16 message buffers for data and IDFlexible configuration of acceptance filtering : Full bit compare / Full bit mask / Two partial bit masksSupports up to 1 Mbps
External Interrupt (8 channels)
Can be programmed edge detection or level detection
External bus interfaceThe external access used selective 8-bit bus or 16-bit bus is available. (External bus mode)
I/O PortsVirtually all external pins can be used as general purpose I/OAll push-pull outputs and schmitt trigger inputsBit-wise programmable as input/output or peripheral signal
32 kHz Subclock Sub-clock for low power operation
FlashMemory
Supports automatic programming, Embedded AlgorithmWrite/Erase/Erase-Suspend/Resume commandsA flag indicating completion of the algorithmNumber of erase cycles : 10,000 timesData retention time : 10 yearsBoot block configurationErase can be performed on each blockBlock protection with external programming voltage
General I/O port with programmable pullup. This function is en-abled in the single-chip mode.
AD00 to AD07I/O pins for 8 lower bits of the external address/data bus. This func-tion is enabled when the external bus is enabled.
93 to 100
P10 to P17
H
General I/O port with programmable pullup. This function is en-abled in the single-chip mode.
AD08 to AD15I/O pins for 8 higher bits of the external address/data bus. This func-tion is enabled when the external bus is enabled.
1 to 8
P20 to P27
H
General I/O port with programmable pullup. This function is en-abled in the single-chip mode.
A16 to A23I/O pins of 8 bits for A16 to A23 ot the external address bus. This function is enabled when the external bus is enabled.
9
P30
H
General I/O port with programmable pullup. This function is en-abled in the single-chip mode.
ALEAddress latch enable output pin. This function is enabled when the external bus is enabled.
10
P31
H
General I/O port with programmable pullup. This function is en-abled in the single-chip mode.
RDRead strobe output pin for the data bus. This function is enabled when the external bus is enabled.
12
P32
H
General I/O port with programmable pullup. This function is en-abled in the single-chip mode or when the WR/WRL pin output is disabled.
WRL Write strobe output pin for the data bus. This function is enabled when the external bus is in enable mode and the WR/WRL pin out-put is enabled. WRL is used as a write-strobe output pin for 8 lower bits of the data bus in 16-bit access while WR is used as a write-strobe output pin for 8 bits of the data bus in 8-bit access.
WR
13
P33
H
General I/O port with programmable pullup. This function is en-abled in the single-chip mode or external bus 8-bit mode or when WRH pin output is disabled.
WRH
Write strobe output pin for the 8 higher bits of the data bus. This function is enabled when the external bus is enabled, when the ex-ternal bus 16-bit mode is selected, and when the WRH output pin is enabled.
DS07-13716-3E 7
MB90440G Series
(Continued)
Pin No. Pin name Circuit type Function
14
P34
H
General I/O port with programmable pullup. This function is enabled in the single-chip mode or when hold function is disabled.
HRQHold request input pin. This function is enabled when the external bus is in enable mode and the hold function is enabled.
15
P35
H
General I/O port with programmable pullup. This function is enabled in the single-chip mode or when hold function is disabled.
HAKHold acknowledge output pin. This function is enabled when the ex-ternal bus is in enable mode and the hold function is enabled.
16
P36
H
General I/O port with programmable pullup. This function is enabled in the single-chip mode or when the external ready function is dis-abled.
RDYReady input pin. This function is enabled when the external bus is in enable mode and the external ready function is enabled.
17
P37
H
General I/O port with programmable pullup. This function is enabled in the single-chip mode or when CLK output is disabled.
CLKCLK output pin. This function is enabled when the external bus is in enable mode and CLK output is enabled.
18
P40
G
General I/O port. This function is enabled when serial data output of UART0 is disabled.
SOT0Serial data output pin for UART0. This function is enabled when UART0 enables serial data output.
19
P41
G
General I/O port. This function is enabled when clock output of UART0 is disabled.
SCK0Serial clock I/O pin for UART0. This function is enabled when UART0 enables serial clock output.
20
P42
G
General I/O port. This function is always enabled.
SIN0Serial data input pin for UART0. Set the corresponding DDR regis-ter to input if this function is used.
21
P43
G
General I/O port. This function is always enabled.
SIN1Serial data input pin for UART1. Set the corresponding DDR regis-ter to input if this function is used.
22
P44
G
General I/O port. This function is enabled when serial clock output of UART1 is disabled.
SCK1Serial clock I/O pin for UART1. This function is enabled when UART1 enables serial clock output.
24
P45
G
General I/O port. This function is enabled when serial data output of UART1 is disabled.
SOT1Serial data output pin for UART1. This function is enabled when UART1 enables serial data output.
8 DS07-13716-3E
MB90440G Series
(Continued)
Pin No. Pin name Circuit type Function
25
P46
G
General I/O port. This function is enabled when the extended serial I/O interface disables serial data output.
SOT2Serial data output pin for the extended serial I/O interface. This function is enabled when the extended serial I/O interface enables serial data output.
26
P47
G
General I/O port. This function is enabled when the extended serial I/O interface disables serial clock output.
SCK2Serial clock I/O pin for the extended serial I/O interface. This func-tion is enabled when the extended serial I/O interface enables seri-al clock output.
28
P50
D
General I/O port. This function is always enabled.
SIN2Serial data input pin for the extended serial I/O interface. Set the corresponidng DDR register to input if this function is used.
29 to 32
P51 to P54
D
General I/O ports. This function is always enabled.
INT4 to INT7External interrupt request input pins for INT4 to INT7. Set the cor-responding DDR register to input if this function is used.
33
P55
D
General I/O port. This function is always enabled.
ADTGExternal trigger input pin for the 8/10-bit A/D converter. Set the cor-responding DDR register to input if this function is used.
38 to 41
P60 to P63
E
General I/O ports. The function is enabled when the analog input enable register specifies port.
AN0 to AN3Analog input pins for the 8/10-bit A/D converter. This function is en-abled when the analog input enable register specifies A/D.
43 to 46
P64 to P67
E
General I/O ports. The function is enabled when the analog input enable register specifies port.
AN4 to AN7Analog input pins for the 8/10-bit A/D converter. This function is en-abled when the analog input enable register specifies A/D.
47
P56
D
General I/O port. This function is always enabled.
TIN0Event input pin for the 16-bit reload timers 0. Set the corresponding DDR register to input if this function is used.
48
P57
D
General I/O port. This function is enabled when the 16-bit reload timers 0 disables output.
TOT0Output pin for the 16-bit reload timers 0. This function is enabled when the 16-bit reload timers 0 enables output.
53 to 58
P70 to P75
D
General I/O ports. This function is always enabled.
IN0 to IN5Trigger input pins for input captures ICU0 to ICU5. Set the corre-sponding DDR register to input if this function is used.
DS07-13716-3E 9
MB90440G Series
(Continued)
Pin No. Pin name Circuit type Function
59 to 60
P76 to P77
D
General I/O ports. This function is enabled when the OCU disables output.
OUT2 to OUT3Event output pins for output compares OCU2 and OCU3. This function is enabled when the OCU enables output.
IN6 to IN7Trigger input pins for input captures ICU6 and ICU7. Set the corre-sponiding DDR register to input and prohibit the OCU output if this function is used.
61 to 64
P80 to P83
D
General I/O ports. This function is enabled when 8/16-bit PPG timer disables waveform output.
PPG0 to PPG3Output pins for 8/16-bit PPG timer. This function is enabled when 8/16-bit PPG timer enables waveform output.
65 to 66
P84 to P85
D
General I/O ports. This function is enabled when the OCU disables output.
OUT0 to OUT1Event output pins for output compares OCU0 and OCU1. This func-tion is enabled when the OCU enables output.
67
P86
D
General I/O port. This function is always enabled.
TIN1Input pin for the 16-bit reload timers 1. Set the corresponding DDR register to input if this function is used.
68
P87
D
General I/O port. This function is enabled when the 16-bit reload timers 0 disables output.
TOT1Output pin for the 16-bit reload timers 1. This function is enabled when the reload timers 1 enables output.
69 to 70
P90 to P91
D
General I/O ports. This function is always enabled.
INT0 to INT1External interrupt request input pins for INT0 to INT3. Set the cor-responding DDR register to input if this function is used.
71
P92
D
General I/O port. This function is enabled when CAN2 disables out-put.
TX2TX output pin for CAN2. This function is enabled when CAN2 en-ables output.
72
P93
D
General I/O port. This function is always enabled.
RX2RX input pin for CAN2 interface. When the CAN function is used, output from the other functions must be stopped.
73
P94
D
General I/O port. This function is enabled when CAN0 disables out-put.
TX0TX output pin for CAN0. This function is enabled when CAN0 en-ables output.
74
P95
D
General I/O port. This function is always enabled.
INT2External interrupt request input pin for INT2. Set the corresponding DDR register to input if this function is used.
RX0RX input pin for CAN0 interface. When the CAN function is used, output from the other functions must be stopped.
10 DS07-13716-3E
MB90440G Series
(Continued)
INPUT LEVELSThe input level of ports P00 to P37 can be selected to be either TTL- or CMOS - level. The initial setting is TTL- level. These settings are global for all P00 to P37, it is not possible to set different levels to each port.
The input level of ports P40 to PA0 can be selected to be either CMOS- or AUTOMOTIVE - level. The initialsetting is CMOS - level. This settings can be done for each port individually.
Pin No. Pin name Circuit type Function
75
P96
D
General I/O port. This function is enabled when CAN1 disables out-put.
TX1TX output pin for CAN1. This function is enabled when CAN1 en-ables output.
76
P97
D
General I/O port. This function is always enabled.
RX1RX input pin for CAN1 interface. When the CAN function is used, output from the other functions must be stopped.
78
PA0
D
General I/O port. This function is always enabled.
INT3External interrupt request input pin for INT2. Set the corresponding DDR register to input if this function is used.
34 AVCC Power supplyPower supply pin for the A/D Converter. This power supply must be turned on or off while a voltage higher than or equal to AVCC is ap-plied to VCC.
37 AVSS Power supply Dedicated ground pin for the A/D Converter
35 AVRH Power supplyExternal reference voltage pin for the A/D Converter. This power supply must be turned on or off while a voltage higher than or equal to AVRH is applied to AVCC.
36 AVRL Power supply External reference voltage pin for the A/D Converter
49 to 50
MD0 to MD1
CInput pins for specifying the operating mode. The pins must be di-rectly connected to VCC or Vss.
51 MD2 FInput pin for specifying the operating mode. The pin must be directly connected to VCC or Vss.
27 C ⎯ This is the power supply stabilization capacitor pin. It should be con-nected externally to an 0.1 µF ceramic capacitor.
(See “ INPUT LEVELS”.) • Programmable pullup resistor :
50 kΩ approx.
CMOS HYS
P-ch
CNTL
N-ch
R
TTLT
R
VCC
VCC
14 DS07-13716-3E
MB90440G Series
HANDLING DEVICES1. Preventing Latch-up
CMOS IC chips may suffer latch-up under the following conditions : (1) A voltage higher than VCC or lower than VSS is applied to an input or output pin. (2) A voltage higher than the rated voltage is applied to between VCC and Vss. (3) The AVCC power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causing thermal damage to the device.Always take sufficient precautions in using semiconductor devices to avoid this possibility.Also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital power-supply voltage(VCC) when the analog system power-supply is turned on and off.
2. Handling Unused Input Pins
Do not leave unused input pins open, as doing so may cause misoperation of the device or latch-up leading topermanent damage. Unused input pins should be pulled up or pulled down through at least 2 kΩ resistance.Unused I/O pins may be left open in output state, but if such pins are in input state they should be handled inthe same way as input pins.
3. Use of the External Clock
To use the external clock, drive only the X0 pin and leave the X1 pin open.A diagram of how to use an external clock is shown below.
4. Precautions for when not using a Sub Clock Signal
If the X0A and X1A pins are not connected to an oscillator, apply pull-down treatment to the X0A pin and leavethe X1A pin open.
5. Power Supply Pins (VCC/VSS)
In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device toavoid abnormal operations including latch-up. However, connect the pins external power and ground lines tolower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused by the rise inthe ground level, and to conform to the total current rating.Make sure to connect VCC and VSS pins via lowest impedance to power lines. It is recommended to provide a bypass capacitor of around 0.1 µF between VCC and VSS pins near the device.
X0
X1open
MB90440G Series
VCC
VCCVCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
MB90440GSeries
DS07-13716-3E 15
MB90440G Series
6. Pull-up/down resistors
The MB90440G Series does not support internal pull-up/down resistors (except pull-up resistors of port 0 toport 3) . Use external components needed.
7. Crystal Oscillator Circuit
Noises around X0 or X1 pins may cause abnormal operations. Make sure to provide bypass capacitors via theshortest distances from X0 and X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and makesure, to the utmost effort, that lines of oscillation circuits do not cross the lines of other circuits.It is highly recommended to provide a printed circuit board artwork surrounding X0 and X1 pins with a groundarea for stabilizing the operation.
8. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D and D/A converters power supply (AVCC, AVRH, AVRL) and analog inputs (AN0to AN7) after turning on the digital power supply (VCC) .Turn off the digital power after turning off the A/D converter supply and analog inputs. In this case, make surethat AVRH does not exceed AVCC (turning on/off the analog and digital power supplies simultaneously is accept-able) .
9. Connection of Unused Pins of A/D Converter
Connect unused pins of A/D and D/A converters to AVCC = VCC, AVSS = AVRH = VSS.
10. N.C. Pin
The N.C. (internally connected) pin must be opened for use.
11. Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50µs or more (0.2 V to 2.7 V) .
12. Initialization
In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers,please turn on the power again.
13. Using REALOS
The use of (EI2OS) is not possible with the REALOS real time operation system.
14. Caution on Operations during PLL Clock Mode
If the PLL clock mode is selected in the microcontroller, it may attempt to continue the operation using the free-running frequency of the automatic oscillating circuit in the PLL circuitly even if the oscillator is out of place orthe clock input is stopped. Performance of this operation, however, cannot be guaranteed.
Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler effective. Since the low-order 16 bits are the same address, the table in ROM can be referenced without using the far specification in the pointer declaration.For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.The ROM area in bank FF exceeds 48 Kbytes, and its entire image cannot be shown in bank 00.The image between FF4000H and FFFFFFH is visible in bank 00, while the image between FF4000H and FFFFFFH is visible only in bank FF. Thus, it is recommended that the ROM data table be stored in the area of FF4000H and FFFFFFH .
ROM (FC bank)
External Access
External Access
ROM (Image ofFF bank)
Peripheral
RAM 14 K
Peripheral
ROM correction
FFFFFFH
FF0000H
FEFFFFH
FE0000H
FDFFFFH
FD0000H
FCFFFFH
FC0000H
00FFFFH
004000H
003FFFH
003900H
0038FFH
001FF5H
000100H
001FF0H
0000BFH
000000H
ROM (FF bank)
ROM (FE bank)
ROM (FD bank)
External Access
ROM (Image ofFF bank)
Peripheral
RAM 6 K
External Access
External Access
Peripheral
FFFFFFH
FF0000H
FEFFFFH
FE0000H
00FFFFH
004000H
003FFFH
003900H
002000H
0018FFH
000100H
0000BFH
000000H
ROM (FF bank)
ROM (FE bank)
MB90V440G MB90F443G/ MB90443G (under development)
18 DS07-13716-3E
MB90440G Series
I/O MAP
(Continued)
Address Register Abbreviation Read/Write
Resource name Initial value
00H Port 0 data register PDR0 R/W Port 0 XXXXXXXXB
01H Port 1 data register PDR1 R/W Port 1 XXXXXXXXB
02H Port 2 data register PDR2 R/W Port 2 XXXXXXXXB
03H Port 3 data register PDR3 R/W Port 3 XXXXXXXXB
04H Port 4 data register PDR4 R/W Port 4 XXXXXXXXB
05H Port 5 data register PDR5 R/W Port 5 XXXXXXXXB
06H Port 6 data register PDR6 R/W Port 6 XXXXXXXXB
07H Port 7 data register PDR7 R/W Port 7 XXXXXXXXB
08H Port 8 data register PDR8 R/W Port 8 XXXXXXXXB
09H Port 9 data register PDR9 R/W Port 9 XXXXXXXXB
0AH Port A data register PDRA R/W Port A _______XB
0BH Port input levels select register PILR R/W Ports 00000000B
B1H Interrupt control register 01 ICR01 R/W 00000111B
B2H Interrupt control register 02 ICR02 R/W 00000111B
B3H Interrupt control register 03 ICR03 R/W 00000111B
B4H Interrupt control register 04 ICR04 R/W 00000111B
B5H Interrupt control register 05 ICR05 R/W 00000111B
B6H Interrupt control register 06 ICR06 R/W 00000111B
B7H Interrupt control register 07 ICR07 R/W 00000111B
B8H Interrupt control register 08 ICR08 R/W 00000111B
B9H Interrupt control register 09 ICR09 R/W 00000111B
BAH Interrupt control register 10 ICR10 R/W 00000111B
BBH Interrupt control register 11 ICR11 R/W 00000111B
BCH Interrupt control register 12 ICR12 R/W 00000111B
BDH Interrupt control register 13 ICR13 R/W 00000111B
BEH Interrupt control register 14 ICR14 R/W 00000111B
BFH Interrupt control register 15 ICR15 R/W 00000111B
C0H to FFH External
22 DS07-13716-3E
MB90440G Series
(Continued)
(Continued)
Address Register Abbreviation Read/Write Resource name Initial value
1FF0H
Program address detection register 0 PADR0
R/W
Address matchdetection function
XXXXXXXXB
1FF1H R/W XXXXXXXXB
1FF2H R/W XXXXXXXXB
1FF3H
Program address detection register 1 PADR1
R/W XXXXXXXXB
1FF4H R/W XXXXXXXXB
1FF5H R/W XXXXXXXXB
Address Register Abbreviation Read/Write Resource name Initial value
3900H Reload register L PRLL0 R/W16-bit programable
pulse generator 0/1
XXXXXXXXB
3901H Reload register H PRLH0 R/W XXXXXXXXB
3902H Reload register L PRLL1 R/W XXXXXXXXB
3903H Reload register H PRLH1 R/W XXXXXXXXB
3904H Reload register L PRLL2 R/W16-bit programable
pulse generator 2/3
XXXXXXXXB
3905H Reload register H PRLH2 R/W XXXXXXXXB
3906H Reload register L PRLL3 R/W XXXXXXXXB
3907H Reload register H PRLH3 R/W XXXXXXXXB
3908H Reload register L PRLL4 R/W16-bit programable
pulse generator 4/5
XXXXXXXXB
3909H Reload register H PRLH4 R/W XXXXXXXXB
390AH Reload register L PRLL5 R/W XXXXXXXXB
390BH Reload register H PRLH5 R/W XXXXXXXXB
390CH Reload register L PRLL6 R/W16-bit programable
pulse generator 6/7
XXXXXXXXB
390DH Reload register H PRLH6 R/W XXXXXXXXB
390EH Reload register L PRLL7 R/W XXXXXXXXB
390FH Reload register H PRLH7 R/W XXXXXXXXB
3910H to 3917H
Reserved
3918H Input capture register 0 IPCP0 R
Input captue 0/1
XXXXXXXXB
3919H Input capture register 0 IPCP0 R XXXXXXXXB
391AH Input capture register 1 IPCP1 R XXXXXXXXB
391BH Input capture register 1 IPCP1 R XXXXXXXXB
391CH Input capture register 2 IPCP2 R
Input captue 2/3
XXXXXXXXB
391DH Input capture register 2 IPCP2 R XXXXXXXXB
391EH Input capture register 3 IPCP3 R XXXXXXXXB
391FH Input capture register 3 IPCP3 R XXXXXXXXB
DS07-13716-3E 23
MB90440G Series
(Continued)
• Meaning of abbreviations used for reading and writing
• Explanation of initial values
Note : Addresses in the range 0000H to 00FFH, which are not listed in the table, are reserved for the primary functions of the MCU. A read access to these reserved addresses results reading “X” and any write access should not be performed.
Address Register Abbreviation Read/Write Resource name Initial value
R/W : Read and Write enabledR : Read onlyW : Write only
0 : The bit is initialized to 0.1 : The bit is initialized to 1.X : The initial value of the bit is undefined._ : The bit is not used. Its initial value is undefined.
24 DS07-13716-3E
MB90440G Series
CAN CONTROLLERThe MB90440G series contains three generic CAN controllers (CAN0, CAN1, CAN2) .
The CAN controller has the following features : • Conforms to CAN Specification Version 2.0 Part A and B
- Supports transmission/reception in standard frame and extended frame formats• Supports transmission of data frames by receiving remote frames• 16 transmission/reception message buffers
- 29-bit ID and 8-byte data- Multi-level message buffer configuration
• Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each messagebuffer as ID acceptance mask- Two acceptance mask registers in either standard frame format or extended frame formats
• Bit rate programmable from 10 Kbps to 1 Mbps (when input clock is at 16 MHz)
Changed the interrupt cause name of the interrupt vector number #19. Input/output timer → 16-bit free-run timer
MB90440G Series
(Continued)
Notes : • N/A : The interrupt request flag is not cleared by the EI2OS interrupt clear signal.• For a peripheral module with two interrupt causes for a single interrupt number, both interrupt request flags are cleared by the EI2OS interrupt clear signal.
• At the end of EI2OS, the EI2OS clear signal will be asserted for all the interrupt flags assigned to the same interrupt number. If one interrupt flag starts the EI2OS and in the meantime another interrupt flag is set by hardware event, the later event is lost because the flag is cleared by the EI2OS clear signal caused by the first event. So it is recommended not to use the EI2OS for this interrupt number.
• If EI2OS is enabled, EI2OS is initiated when one of the two interrupt signals in the same interrupt control register (ICR) is asserted. This means that different interrupt causes share the same EI2OS descriptor which should be unique for each interrupt cause. For this reason, when one interrupt cause uses the EI2OS, the other interrupt should be disabled.
*1 : The interrupt request flag is cleared by the EI2OS interrupt clear signal.*2 : The interrupt request flag is cleared by the EI2OS interrupt clear signal. A stop request is available.
DS07-13716-3E 33
MB90440G Series
ELECTRICAL CHARACTERISTICS1. Absolute Maximum Ratings
(VSS = AVSS = 0.0 V)
*1 : AVCC, AVRH, and AVRL shall never exceed VCC. AVRH, AVRL shall never exceed AVCC. Also, AVRL shall never exceed AVRH.
*2 : VI and VO shall never exceed VCC + 0.3 V. VI shall never exceed the specified ratings. However if the maximum current to/ from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating.
*3 : Maximum output current specifies the peak value of the corresponding pin.
*4 : The average output current specifies the average current of corresponding pins within 100 ms. (operation current × operation rate = average value)
*5 : The total average output current specifies the average current of all corresponding pins within 100 ms. (operation current × operation rate = average value)
*6 : • Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67,P70 to P77, P80 to P87, P90 to P97, PA0
• Use within recommended operating conditions.• Use at DC voltage (current) .
“L” level total maximum output current ΣIOL ⎯ 100 mA
“L” level total average output current ΣIOLAV ⎯ 50 mA *5
“H” level maximum output current IOH ⎯ −15 mA *3
“H” level average output current IOHAV ⎯ −4 mA *4
“H” level total maximum output current ΣIOH ⎯ −100 mA
“H” level total average output current ΣIOHAV ⎯ −50 mA *5
Power consumption PD
⎯ 500 mW MB90F443G
⎯ 400 mWMB90F443G (underdevelopment)
Operating temperature TA −40 + 105 °C
Storage temperature Tstg −55 + 150 °C
34 DS07-13716-3E
MB90440G Series
(Continued)
• The +B signal should always be applied with a limiting resistance placed between the +B signal and the microcontroller.
• The value of the limiting resistance should be set so that +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B inputpotential may pass through the protective diode and increase the potential at the VCC pin, and this may affectother devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.• Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input
pins, etc.) cannot accept +B signal input.• Sample recommended circuits.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
* : Use a ceramic capacitor or capacitor of better AC characteristics. Capacitor at the VCC should be greater than this capacitor.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure.No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand.
Parameter SymbolValue
Unit RemarksMin Typ Max
Power supply voltageVCC, AVCC
4.5 5.0 5.5 V Under normal operation
3.0 ⎯ 5.5 VRetains status at the time of opera-tion stop
Smoothing capacitor CS 0.022 0.1 1.0 µF *
Operating temperature TA −40 ⎯ +105 °C
C
CS
• C pin connection circuit
36 DS07-13716-3E
MB90440G Series
3. DC Characteristics (VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
(Continued)
Parameter Symbol Pin ConditionValue
Unit RemarksMin Typ Max
Input H voltage
VIHSCMOS Hysteresis input pin
⎯ 0.8 VCC ⎯ VCC + 0.3
V
VIHAAUTOMOTIVE input pin
⎯ 0.8 VCC ⎯ ⎯ V
VIH TTL input pin ⎯ 2.0 ⎯ ⎯ V
VIHM MD input pin ⎯ VCC − 0.3
⎯ VCC + 0.3
V
Input L voltage
VILSCMOS Hysteresis input pin
⎯ VSS − 0.3
⎯ 0.2 VCC V
VILAAUTOMOTIVE input pin
⎯ ⎯ ⎯ 0.5 VCC V
VIL TTL input pin ⎯ ⎯ ⎯ 0.8 V
VILM MD input pin ⎯ VSS − 0.3
⎯ VSS + 0.3
V
Output H voltage VOH All output pinsVCC = 4.5 V, IOH = −4.0 mA
VCC − 0.5
⎯ ⎯ V
Output L voltage VOL All output pinsVCC = 4.5 V, IOL = 4.0 mA
⎯ ⎯ 0.4 V
Input leak current IIL ⎯ VCC = 5.5 V, VSS < VI < VCC
−5 ⎯ + 5 µA
DS07-13716-3E 37
MB90440G Series
(Continued) (VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
* : The power supply current is measured with an external clock.
Parameter Symbol Pin ConditionValue
Unit RemarksMin Typ Max
Power supply current*
ICC
VCC
VCC = 5.0 VInternal frequency : 16 MHz, At normal operating
⎯ 45 60 mA
VCC = 5.0 VInternal frequency : 16 MHz, At flash programming / erasing
⎯ 50 70 mA
ICCS
VCC = 5.0 VInternal frequency : 16 MHz, At sleep
⎯ 13 22 mA
ICCL
VCC = 5.0 VInternal frequency : 8 kHz, At sub operationTA = + 25 °C
⎯ 50 100 µAMB90443G (under devel-opment)
⎯ 300 500 µA MB90F443G
ICCLS
VCC = 5.0 VInternal frequency : 8 kHz, At sub sleepTA = + 25 °C
⎯ 15 40 µA
ICCT
VCC = 5.0 VInternal frequency : 8 kHz, At watch modeTA = + 25 °C
⎯ 7 25 µA
ICTS
VCC = 5.0 V Internal frequency : 2 MHz, At timer base timer modeTA = + 25 °C
⎯ 600 1200 µA
ICCH At stop mode, TA = + 25 °C ⎯ 5 20 µA
Input capacity CIN
Other than AVCC, AVSS,
AVRH, AVRL, C, VCC, VSS
⎯ ⎯ 10 15 pF
Pull-upresistance
RUP
P00 to P07, P10 to P17, P20 to P27, P30 to P37,
RST
⎯ 25 50 100 kΩ
Pull-downresistance
RDOWN MD2 ⎯ 25 50 100 kΩ
38 DS07-13716-3E
MB90440G Series
4. AC Characteristics
(1) Clock Timing (VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
* : When selecting the PLL clock, the range of clock frequency is limitted. Use this product within range as mentioned in "• Guaranteed PLL operation range : Relationship between oscillation frequency and internal operating clock frequency".
Parameter Symbol PinValue
Unit RemarksMin Typ Max
Clock frequencyfC X0, X1
3 ⎯ 16 MHz Not multiplied
8 ⎯ 16 MHz PLL multiplied by 1*
4 ⎯ 8 MHz PLL multiplied by 2*
3 ⎯ 5.33 MHz PLL multiplied by 3*
3 ⎯ 4 MHz PLL multiplied by 4*
fCL X0A, X1A ⎯ 32.768 ⎯ kHz
Clock cycle timetCYL X0, X1 62.5 ⎯ 333 ns
tLCYL X0A, X1A ⎯ 30.5 ⎯ µs
Input clock pulse widthPWH, PWL X0 10 ⎯ ⎯ ns Duty ratio is about 30%
to 70%.PWLH, PWLL X0A ⎯ 15.2 ⎯ µs
Input clock rise and fall time
tCR, tCF X0 ⎯ ⎯ 5 nsWhen using external clock
Internal operating clock frequency
fCP ⎯ 1.5 ⎯ 16 MHz When using main clock
fLCP ⎯ ⎯ 8.192 ⎯ kHz When using sub-clock
Internal operating clock cycle time
tCP ⎯ 62.5 ⎯ 666 ns When using main clock
tLCP ⎯ ⎯ 122.1 ⎯ µs When using sub-clock
X0
tCYL
tCF tCR
0.8 VCC
0.2 VCC
PWH PWL
X0A
tLCYL
tCF tCR
0.8 VCC
0.2 VCC
PWLH PWLL
• Clock Timing
DS07-13716-3E 39
Changed the "(1) Clock Timing". Added the limitation when PLL is used for the clock frequency.
MB90440G Series
The AC ratings are measured for the following measurement reference voltages.
5.5
4.5
81.5 16
Guaranteed operation range
Pow
er s
uppl
y vo
ltage
VC
C (
V)
Internal clock fCP (MHz)
Guaranteed PLL operation range
16
12
89
4
3 4 8 16
Not multiplied
×4 ×3 ×2 ×1
Inte
rnal
clo
ck fC
P (
MH
z)
Oscillation frequency fC (MHz)
• Guaranteed PLL operation range
Relationship between internal operation clock frequency and power supply voltage
Relationship between oscillation frequency and internal operating clock frequency
0.8 VCC
0.2 VCC
2.4 V
0.8 V
2.0 V
0.8 V
0.8 VCC
0.5 VCC
CMOS Hysteresis Input Pin Output Pin
TTL Input Pin
AUTOMOTIVE Input Pin
• Input signal waveform • Output signal waveform
40 DS07-13716-3E
MB90440G Series
(2) Clock Output Timing (VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter Symbol Pin ConditionValue
Unit RemarksMin Max
Cycle time tCYCCLK VCC = 5 V ± 10%
62.5 ⎯ ns
CLK ↑ → CLK ↓ tCHCL 20 ⎯ ns
CLK
tCYC
2.4 V 2.4 V
0.8 V
tCHCL
DS07-13716-3E 41
MB90440G Series
(3) Reset Input Timing and Hardware Stand-by Input Timing (VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Note: • Oscillator oscillation time is the time that amplitude reached 90%. For a crystal oscillator, the oscillation time is between several ms to tens of ms; for a ceramic oscillator, the oscillation time is between
hundreds of µs to several ms, and for an external clock the oscillation time is 0 ms.• Any reset can not fully initialize the Flash Memory if it is performing the automatic algorithm.
Parameter Symbol PinValue
Unit RemarksMin Max
Reset input time tRSTL RST
16 tCP ⎯ ns Under normal operation
Oscillation time of oscillator + 100 µs + 16 tCP
⎯ ⎯
In stop mode, watch mode, sub-clock mode, sub-sleep mode
RST
0.2 VCC
tRSTL
0.2 VCC
tRSTL
0.2 VCC 0.2 VCC
RST
X0
90% ofamplitude
Instruction execution
Oscillation setting time
Oscillatoroscillation time
Internal operationclock
Internal reset
• In stop mode :
• Under normal operation :
100 µs + 16 tCP
42 DS07-13716-3E
MB90440G Series
(4) Power-on Reset (VCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
* : VCC must be kept lower than 0.2 V before power-on.
Note : The above values are used for causing a power-on reset.Some registers in the device are initialized only upon a power-on reset. To initialize these registers, turn the power supply on using the above values.
Parameter Symbol Pin ConditionValue
Unit RemarksMin Max
Power supply rising time tR VCC⎯
0.05 30 ms *
Power supply cut-off time tOFF VCC 50 ⎯ ms Due to repeated operations
VCC
VCC
VSS
3 V
tR
tOFF
2.7 V
0.2 V 0.2 V0.2 V
RAM data Hold
Sudden changes in the power supply voltage may cause a power on reset. We recommend to raise the voltage smoothly to suppress fluctuation during operation, as shown in the figure below. Perform while not using the PLL clock. However, if voltage drops are within 1 V/s, you can operate while using the PLL clock.
We recommend rising speed of the supply voltage at 50 mV/ms or slower
DS07-13716-3E 43
MB90440G Series
(5) Bus Timing (Read) (VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter Symbol PinValue
Unit RemarksMin Max
ALE pulse width tLHLL ALE tCP / 2 − 20 ⎯ ns
Valid address → ALE ↓ time tAVLLALE, A16 to A23,
AD00 to AD15tCP / 2 − 20 ⎯ ns
ALE ↓ → Address valid time tLLAXALE,
AD00 to AD15tCP / 2 − 15 ⎯ ns
Valid address → RD ↓ time tAVRL
A16 to A23, AD00 to AD15,
RDtCP − 15 ⎯ ns
Valid address → Valid data input
tAVDVA16 to A23,
AD00 to AD15⎯ 5 tCP / 2 − 60 ns
RD pulse width tRLRH RD 3 tCP / 2 − 20 ⎯ ns
RD ↓ → Valid data input tRLDVRD,
AD00 to AD15⎯ 3 tCP / 2 − 60 ns
RD ↑ → Data hold time tRHDXRD,
AD00 to AD150 ⎯ ns
RD ↑ → ALE ↑ time tRHLH RD, ALE tCP / 2 − 15 ⎯ ns
RD ↑ → Address valid time tRHAX RD, A16 to A23 tCP / 2 − 10 ⎯ ns
Valid address → CLK ↑ time tAVCH
A16 to A23, AD00 to AD15,
CLKtCP / 2 − 20 ⎯ ns
RD ↓ → CLK ↑ time tRLCH RD, CLK tCP / 2 − 20 ⎯ ns
ALE ↓ → RD ↓ time tLLRL ALE, RD tCP / 2 − 15 ⎯ ns
44 DS07-13716-3E
Changed the symbol tRHLH of (5) Bus Timing (Read). RD ↓ → RD ↑
MB90440G Series
0.8 V
0.8 V
2.4 V
2.4 V
2.4 V
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.2 VCC
0.8 VCC
CLK
ALE
RD
A23 to A16
AD15 to AD00
tRHLH
tAVRL
tAVLL tLLAX
tLHLL
tRLRH
tRHAX
tRHDX
tRLCH
2.4 V
2.4 V
0.8 V
tAVCH
0.2 VCC
0.8 VCC
tAVDVtRLDV
2.4 V
tLLRL
Address Read data
• Bus Timing (Read)
DS07-13716-3E 45
MB90440G Series
(6) Bus Timing (Write) (VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter Symbol PinValue
Unit RemarksMin Max
Valid address → WR ↓ time tAVWL
A16 to A23, AD00 to AD15,
WRtCP − 15 ⎯ ns
WR pulse width tWLWH WR 3 tCP / 2 − 20 ⎯ ns
Valid data output → WR ↑ time tDVWHAD00 to AD15,
WR3 tCP / 2 − 20 ⎯ ns
WR ↑ → Data hold time tWHDXAD00 to AD15,
WR20 ⎯ ns
WR ↑ → Address valid time tWHAX A16 to A23, WR tCP / 2 − 10 ⎯ ns
WR ↑ → ALE ↑ time tWHLH WR, ALE tCP / 2 − 15 ⎯ ns
WR ↓ → CLK ↑ time tWLCH WR, CLK tCP / 2 − 20 ⎯ ns
0.8 V
0.8 V
2.4 V
2.4 V
2.4 V
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
CLK
ALE
WR (WRL, WRH)
A23 to A16
AD15 to AD00
tWHL
tAVWL tWLWH
tWHAX
tWHDX
tWLC
tDVWH
Address Write data
• Bus Timing (Write)
46 DS07-13716-3E
MB90440G Series
(7) Ready Input Timing (VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +105 °C)
Note : If the RDY setup time is insufficient, use the auto-ready function.
Parameter Symbol PinValue
Unit RemarksMin Max
RDY setup time tRYHS RDY 45 ⎯ ns
RDY hold time tRYHH RDY 0 ⎯ ns
tRYHS tRYHH
2.4 V
0.8 VCC
0.2 VCC
0.8 VCC
CLK
ALE
RD/WR
RDYno WAIT is used.
RDYWhen WAIT is used(1 cycle).
• Ready Input Timing
DS07-13716-3E 47
MB90440G Series
(8) Hold Timing (VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +105 °C)
Note : More than 1 machine cycle is needed before HAK changes after HRQ pin is fetched.
Parameter Symbol PinValue
Unit RemarksMin Max
Pin floating → HAK ↓ time tXHAL HAK 30 tCP ns
HAK ↑ → Pin valid time tHAHV HAK tCP 2 tCP ns
HAK
tXHAL tHAHV
2.4 V
0.8 V
2.4 V
2.4 V
0.8 V
0.8 V
Each pinHigh impedance
• Hold Timing
48 DS07-13716-3E
MB90440G Series
(9) UART0/1, Serial I/O Timing (VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +105 °C)
Notes : • AC ratings in CLK synchronous mode. • CL is load capacitance value connected to pins when testing.
Parameter Symbol Pin ConditionValue
Unit RemarksMin Max
Serial clock cycle time tSCYCSCK0 to SCK2
An output pin of internal sift clock modeCL = 80 pF + 1 TTL.
4 tCP ⎯ ns
SCK ↓ → SOT delay time tSLOV
SCK0 to SCK2, SOT0 to SOT2
–80 +80 ns
Valid SIN → SCK ↑ tIVSH
SCK0 to SCK2, SIN0 to SIN2
100 ⎯ ns
SCK ↑ → valid SIN hold time tSHIX
SCK0 to SCK2, SIN0 to SIN2
60 ⎯ ns
Serial clock “H” pulse width tSHSLSCK0 to SCK2
An output pin of external sift clock modeCL = 80 pF + 1 TTL.
4 tCP ⎯ ns
Serial clock “L” pulse width tSLSHSCK0 to SCK2
4 tCP ⎯ ns
SCK ↓ → SOT delay time tSLOV
SCK0 to SCK2, SOT0 to SOT2
⎯ 150 ns
Valid SIN → SCK ↑ tIVSH
SCK0 to SCK2, SIN0 to SIN2
60 ⎯ ns
SCK ↑ → valid SIN hold time tSHIX
SCK0 to SCK2, SIN0 to SIN2
60 ⎯ ns
DS07-13716-3E 49
Changed the value of serial clock cycle time. Min : 8tCP → 4tCP
MB90440G Series
SCK
SOT
SIN
tSCYC
tSLOV
tIVSH tSHIX
0.8 V 0.8 V
2.4 V
2.4 V
0.8 V
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
• Internal Shift Clock Mode
SCK
SOT
SIN
tSLSH tSHSL
tSLOV
tIVSH tSHIX
0.2 VCC 0.2 VCC
0.8 VCC 0.8 VCC
2.4 V
0.8 V
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
• External Shift Clock Mode
50 DS07-13716-3E
MB90440G Series
(10) Timer Related Resource Input Timing (VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter Symbol Pin ConditionValue
Unit RemarksMin Max
Input pulse widthtTIWH TIN0, TIN1
⎯ 4 tCP ⎯ nstTIWL IN0 to IN7
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
tTIWH tTIWL
TIN0, TIN1IN0 to IN7
• Timer Input Timing
DS07-13716-3E 51
MB90440G Series
(11) Timer Related Resource Output Timing (VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +105 °C)
(12) Trigger Input Timing (VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter Symbol Pin ConditionValue
Unit RemarksMin Max
CLK ↑ → TOUT transition time
tTOTOT0 to TOT1, PPG0 to PPG3
⎯ 30 ⎯ ns
Parameter Symbol Pin ConditionValue
Unit RemarksMin Max
Input pulse widthtTRGH
tTRGL
INT0 to INT7, ADTG
⎯5 tCP ⎯ ns normal operation
1 ⎯ µs stop mode
2.4 V
tTO
2.4 V
0.8 V
CLK
TOUT
• Timer Output Timing
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
tTRGH tTRGL
INT0 to INT7ADTG
• Trigger Input Timing
52 DS07-13716-3E
MB90440G Series
5. A/D Converter• Electrical Characteristics
(VCC = AVCC = 5.0 V ± 10%, VSS = AVSS = 0.0 V, 3.0 V ≤ AVRH − AVRL, TA = −40 °C to +105 °C)
* : Specifies the power supply current (VCC = AVCC = AVRH = 5.0 V) when the A/D converter is inactive and the CPU has been stopped.
Parameter Symbol PinValue
Unit RemarksMin Typ Max
Resolution ⎯ ⎯ ⎯ ⎯ 10 bit
Total error ⎯ ⎯ ⎯ ⎯ ±5.0 LSB
Nonlinearity error ⎯ ⎯ ⎯ ⎯ ±2.5 LSB
Differential linearity error ⎯ ⎯ ⎯ ⎯ ±1.9 LSB
Zero transition voltage VOTAN0 to
AN7AVRL − 3.5 LSB
AVRL + 0.5 LSB
AVRL + 4.5 LSB
V 1 LSB = (AVRH − AVRL) / 1024 [V]Full scale transition voltage VFST
AN0 to AN7
AVRH − 6.5 LSB
AVRH –1.5 LSB
AVRH + 1.5 LSB
V
Compare time ⎯ ⎯ 66 tCP ⎯ ⎯ ns Machine clock of 16 MHzSampling time ⎯ ⎯ 32 tCP ⎯ ⎯ ns
Analog port input current IAINAN0 to
AN7⎯ ⎯ 10 µA
Analog input voltage VAINAN0 to
AN7AVRL ⎯ AVRH V
Reference voltage
⎯ AVRHAVRL + 2.7 LSB
⎯ AVCC V
⎯ AVRL 0 ⎯ AVRH − 2.7 LSB
V
Power supply currentIA AVCC ⎯ 2 6 mA
IAH AVCC ⎯ ⎯ 5 µA *
Reference voltage supply current
IR AVRH ⎯ 0.9 1.3 mA
IRH AVRH ⎯ ⎯ 5 µA *
Offset between channels ⎯ AN0 to AN7
⎯ ⎯ 4 LSB
DS07-13716-3E 53
MB90440G Series
• A/D Converter Glossary
(Continued)
Resolution : Analog changes that are identifiable with the A/D converter
Linearity error : The deviation of the straight line connecting the zero transition point ( “00 0000 0000” to “00 0000 0001” ) with the full-scale transition point ( “11 1111 1110” to “11 1111 1111” ) from actual conversion characteristics.
Differential linearity error
: The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value.
Total error : The difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error, and linearity error.
3FF
3FE
3FD
004
003
002
001
AVRL AVRH
VNT
1.5 LSB
0.5 LSB
1 LSB × (N − 1) + 0.5 LSB
Actual conversioncharacteristics
(measured value)
Actual conversioncharacteristics
Theoretical characteristics
Dig
ital o
utpu
t
Analog input
Total error
Total error of digital output N = VNT − 1 LSB x (N − 1) + 0.5 LSB
1 LSB[LSB]
1 LSB = (theoretical value) AVRH − AVRL1024
[V]
VOT (theoretical value) = AVRL + 0.5 LSB [V]
VFST (theoretical value) = AVRH − 1.5 LSB [V]
VNT : The voltage at a transition of digital output from (N − 1) to N.
54 DS07-13716-3E
MB90440G Series
(Continued)
3FF
3FE
3FD
004
003
002
001
AVRL AVRH AVRL AVRH
N + 1
N
N − 1
N − 2
VNT
VOT (measured value)
VFST
1 LSB × (N − 1) + VOT
Actual conversioncharacteristics
(measuredvalue)
(measuredvalue)
Actual conversioncharacteristics
Theoretical characteristics
Actual conversioncharacteristics
Actual conversioncharacteristics
Theoretical characteristics
Dig
ital o
utpu
t
Dig
ital o
utpu
t
Analog inputAnalog input
VNT (measured value)
V (N + 1) T
(measuredvalue)
Linearity error Differential linearity error
Linearity error of digital output N = VNT − 1 LSB × (N − 1) + VOT
1 LSB[LSB]
Differential linearity error of digital output N = V (N+1) T − VNT
1 LSB−1 LSB [LSB]
VFST − VOT
1022 [V]1 LSB =
VOT : Voltage at transition of digital output 000H to 001H.VFST : Voltage at transition of digital output 3FEH to 3FFH.
DS07-13716-3E 55
MB90440G Series
• Notes on Using A/D Converter
Select the output impedance value for the external circuit of analog input according to the following conditions : Output impedance values of the external circuit of about 5 kΩ or lower are recommended.If external capacitors are used, a capacitance of several thousand times the internal capacitor value is recom-mended in order to minimize the effect of voltage distribution between the external and internal capacitor.
Note: If the output impedance of the external circuit is too high, the sampling time for analog voltages may not besufficient (sampling period = 2.00 µs @ machine clock of 16 MHz) . The output impedance of the external circuit can be set to approx. 15kΩ or lower , when the sampling period is set to 4.00 µs.
• About ErrorThe smaller the absolute value of | AVRH − AVRL | is, the greater the relative error is.
Note 1) * : These dimensions do not include resin protrusion.Note 2) Pins width and pins thickness include plating thickness.Note 3) Pins width do not include tie bar cutting remainder.
60 DS07-13716-3E
MB90440G Series
MAIN CHANGES IN THIS EDITION
The vertical lines marked in the left side of the page show the changes.
Page Section Change Results
4 PRODUCT LINEUP Changed the resource name.
16-bit I/O Timer → 16-bit Free-run Timer
6 PIN ASSIGNMENT Changed the pin name.
35-pin : AVR + → AVRH36-pin : AVR - → AVRL
17 BLOCK DIAGRAM Changed the resource name.
16-bit I/O Timer → 16-bit Free-run Timer
32 INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Changed the interrupt cause name of the interrupt vector number #19.Input/output timer → 16-bit free-run timer
39 ELECTRICAL CHARACTERISTICS4. AC Characteristics
Changed the "(1) Clock Timing".Added the limitation when PLL is used for the clock frequency.
44Changed the symbol tRHLH of (5) Bus Timing (Read).RD ↓ → RD ↑
49 ELECTRICAL CHARACTERISTICS4. AC Characteristics(9) UART0/1, Serial I/O Timing
Changed the value of serial clock cycle time. Min : 8tCP → 4tCP
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