Front-End electronics for Future Linear Collider calorimeters FJPPL meeting @ KEK C. de La Taille N. Seguin_Moreau IN2P3/LAL Orsay On behalf of the CALICE collaboration http::/www.lal.in2p3.fr/technique/se/flc Slides from JC Brient, S. Blin, C. Jauffret, J. Fleury, G. Martin- Chassard, L. Raux, F. Sefkov
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Front-End electronics for Future Linear Collider calorimeters FJPPL meeting @ KEK C. de La Taille N. Seguin_Moreau IN2P3/LAL Orsay On behalf of the CALICE.
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Front-End electronics for Future Linear Collider
calorimeters
FJPPL meeting @ KEK
C. de La TailleN. Seguin_MoreauIN2P3/LAL Orsay
On behalf of the CALICE collaboration http::/www.lal.in2p3.fr/technique/se/flc
Slides from JC Brient, S. Blin, C. Jauffret, J. Fleury, G. Martin-Chassard, L. Raux, F. Sefkov
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 2
Orsay Micro-Electronics Group
A strong team of 9 ASIC designers… = 20% of in2p3 designers = 60% of department research engineers A team with critical mass Expertise in low noise, low power high level
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 4
ATLAS : LAr e.m. calorimeter
200 000 channels
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 5
Readout ASIC for multi-anode Photomultiplier (Hamamatsu)
OPERA_ROC (2002)32 channelsVariable gain preampAutotrigger on ¼ p.e.BiCMOS 0.8µ3 000 chips
64 ch front-end board (BERN)
ASIC production for OPERA target tracker
(S. Blin, T. Caceres, CdLT, G. Martin, L. Raux)
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 6
« Imaging calorimetry » at ILC
Particle flow algorithm Reconstruct each particle individually Bring jet resolution down to 30%/√E Measure charged particles in tracker Measure photons in ECAL Measure hadrons in ECAL and HCAL Minimize confusion term
Calorimeter design High granularity : typ < 1 cm2
High segmentation : ~30 layers Moderate energy resolution (10%/√E) ECAL : Silicon-Tungsten HCAL : analog vs digital
CALICE collaboration « a high granularity calorimeter
optimized for particle flow algorithm 190 phys./eng., 9 countries, 3
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 7
ILC Challenges for electronics
Requirements for electronics Large dynamic range (15 bits) Auto-trigger on ½ MIP On chip zero suppress Front-end embedded in detector Ultra-low power : ( « 100µW/ch) 108 channels Compactness
« Tracker electronics with calorimetric performance »
ATLAS LAr FEB 128ch 400*500mm 1 W/chFLC_PHY3 18ch 10*10mm 5mW/ch ILC : 100µW/ch
W layer
Si pads
ASIC
Ultra-low POWERis the
KEY issue
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 8
CALICE physics prototype(s)
1 m3 prototype for physics tests Goal : study particle flow algorithm Check modelization of hadronic
showers
3 calorimeters to go to testbeam ECAL : W-Si 24X0 20x20 cm2
AHCAL : Tiles + fibers + SiPMs DHCAL : RPCs or GEMS Already 104 to 4 105 channels ! Run at DESY (05), CERN (06), FNAL
(07)
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 9
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 29
EUDET module FEE : main issues
Mixed signal issues Digital activity with sensistive
analog front-end
Pulsed power issues Electronics stability Thermal effects To be tested in beam a.s.a.p.
No external components Reduce PCB thickness to <
800µm Internal supplies decoupling
FE chip (1mm)Wafer (400µm)PCB (600µm)
Tungsten (1 mm)
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 30
Evolution of PCBs
FLC_FEV1
FLC_FEV2
ILC_FEV3
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 31
ECAL Front-End ASIC
PowerCycling
Auto-trigger on ½ MIP
Internal ADC
Readout integration is the key element of compact detector Keep small Moliere radius for good shower separation Many features have never been used before e.g. power cycling (ON 2ms OFF
200 ms)
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 32
EUDET DHCAL RPC ASIC
Move towards ILC specs Power pulsing Data internally saved during bunch train Data transferred to DAQ during inter-bunch
Chip based on MAROC will be submitted in sep 06
Close
to M
AROC chip
64 chan
nels f
or m
ulti-a
node
PM
C h a n n e l 0
C h a n n e l 1
C h a n n e l 2
C h a n n e l 3
C h a n n e l 6 2
C h a n n e l 6 3
T h r e sh o ld 0
T h r e sh o ld 1
T h r e sh o ld 2
T h r e sh o ld 3
T h r e sh o ld 6 2
T h r e sh o ld 6 3
>
B unc h c ro s s ing ID
Dig
ital m
emor
y[ 6
4 bi t s
(da
t a)
+ 12
bi ts
(B
CID
)]*d
e pht
mem
ory write
D a ta o u t
an a lo g u e f r o n t- en d
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 33
MAROC : 64 ch MAPMT chip for ATLAS lumi
Characteristics 64 PMT channels input (50-100 Ω) Variable gain current conveyor (0-2)
6 bits : 2, 1, 1/2, 1/4, 1/8, 1/16
64 discriminator outputs (GTL) 100% sensitivity to 1/3 photoelectron
(50fC). Counting rate up to 2 MHz Common threshold loaded by internal
10bit DAC 1 multiplexed charge output with variable
shaping 20-200ns and Track & Hold. Dynamic range : 11 bits (2fC - 5 pC) Crosstalk < 1%
Technology : AMS SiGe 0.35µm Submitted 13 june 05 Area 12 mm2
Dissipation 130 mW @ VDD=3.5V
Can be accomodated to DHCAL Adding power pulsing and digital readout
Synoptic diagramm of MAROC1
Hold signal
Variable
GainPream
p.
VariableSlow
Shaper
S&H
BipolarFast Shaper
64 Trigger outputs
Gain correction6 bits/channel
discriminator
threshold10 bits DAC
Multiplexed charge output
64 PM inputs
10 bit DAC
Chip On Board
3*3 cm2
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 34
MAROC Efficiency curves
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 35
HaRDROC architecture Full power pulsing Digital memory: Data saved during bunch train. Only one serial output Store all channels and BCID for every hit. Depth = 128 bits Data format : 128(depth)*[2bit*64ch+32bit(bcid)+8bit(Header] = 20kbits Sequential readout @ 100 MHz : 20k* 10 ns = 200 µs (read up to 1000
chips/inter bunch)
64 INPUTS
1 OUTPUTTransfered to DAQ during Inter-bunch
Hold: Ext signal or OR output
Variable Gain
Preamp.
VariableSlow Shaper
20-100 ns
S&H
BipolarFast Shaper
Gain correction
64*6bitsG=0 to 4
2 discri thresholds (2*10 bits)
2 DACs10 bits
Latch
Latch
Vth1 -
Vth0 -
-Vth1 -Vth0
OR
trig1<0>
trig1<63>
trig0<0>
trig0<63>
MultiplexedAnalog charge
output
trig1<63>
trig1<0>
WR
SRAM
128*
160
32 bit counter BCID
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 36
HaRDROC layout 64 inputs, 1 data output Vss of the analog, mix and digital part separated 180 pads
64 Analog
Channels
Digital memory
Control signals and power supplies
Control signals and power supplies
Dual DAC
Bandgap
Discris
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 37
Digital architecture towards 2nd generation DAQ
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 38
Inter chip communication
Open collector common control and data line
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 39
Acquisition mode
Store upto 128 events in RAM Stop acquisition when ram_full signal asserted
Common collector bus for ram_full signal
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 40
Readout mode
Token ring mechanism initiated by DAQ Possibility to bypass a chip by slow control
One data line activated by each chip sequentially Readout rate few MHz to minimize power dissipation With 500 pF bus capacitance, power dissipation is ~10uW/chip i=CdV/dt = 1 mA => 1 mW for up to 100 chips on bus Readout time max (ram full) 10kbit * 1 µs = 10 ms/chip
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 41
EUDET ECAL ASIC
72 channels Scales with the 4 factor reduction in pad size and is compatible with
physics prototype
Detector DC coupling Prepares the case the on-detector MMIC HV capacitance is not
affordable Provides leakage current monitoring, up to 1 µA/Ch
Auto-trigger If one channel is hit during a bunch crossing, then the whole chip is
recorded with a time tag (BCID) The auto trigger activates the T&H
Analogue pipeline, ADC & digital registers 8-depth analog pipeline to store « in bunch » events Wilkinson 12 bit 100MHz ADC On chip storage, inter-bunch data outputting
Digital data output Daisy chained with redundancy : one output for 40 ASICs Common architecture for ECAL and HCAL
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 42
Present status on noise & power cycling
FLC_TECH1 : moving into SiGe 0.35µ 30 µW in pulsed mode ENC = 1000 e- @ Cd=27pF (MIP=40 000e-) NOISE WELL BELOW MIP First demonstration of power cycling : Target power of 100 µW/channel
appears within reach : to be validated in testbeam in 2006 with FLC PHY4 ASIC
FLC shaping
Detector capacitance
Autotrigger
ON
signal
Ready for pulse
RFCF
20 µs
POWER CYCLING MEASUREMENTNOISE MEASUREMENT
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 43
General block scheme
Ch. 0
Ch. 1
Analog channel Analog mem.
72-channelWilkinson
ADC
Analog channel Analog mem.
Ch. 71 Analog channel Analog mem.
Bunch crossing 24 bit counterTime
digital mem.
Eventbuilder
Memorypointer
Triggercontrol
MainMemory
SRAM
Commodule
EC
AL
SLA
B
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 44
One channel
20M
1M 200ns
G=10
G=1
200ns
Analog Memory
Depth = 5
Analog Memory
Depth = 5
G=100G=5
12 bits
ADC
Gain selection
0=>6pF
3-bit threshold adjustment
10-bit DAC
Common to the 72
Channels
T100ns
DAC output
Q
HOLD
Preamp
Ampli
Slow Shaper
Slow Shaper
Fast Shaper
Time measurement
Charge measurement
3pF
Calibration input
input
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 45
Time considerations
time
Time between two trains: 200ms (5 Hz)
Time between two bunch crossing: 337 ns Train length 2820 bunch X
(950 us)
Acquisition
1ms (.5%)
A/D conv..5ms (.25%)
DAQ.5ms (.25%)
1% duty cycle
IDLE MODE
99% duty cycle
199ms (99%)
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 46
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 48
Digital part Store all channels and BCID for every hit. Depth ~8 bits Event size : 8(depth)*[16bit*72ch+16bit(bcid)] = 9344 bits Sequential readout : 9344*10ns = 100 µs : open collector
level
Register 16bits
OR
16 bit counter BCID
Register 16bits
DiscriCH 0
DiscriCH 71
Register 16*16 bit BCID
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 50
Prospective for A-HCAL SiPM Chip
Similar developments for AHCAL Chip fully dedicated to SiPMs developped after ECAL chip Internal DAC for SiPM gain adjustment (5V range) Auto-trigger (fast shaper + Discriminator) Internal TDC, 1 ns step Internal 12 bit ADC Power pulsing
T&Hx1
Variable gain Preamplifier
Discri
TDC
12-bit ADC
8 bit DAC (0-5V)
in
Fast Shaper
Shaper tp~30-40ns
Auto-trigger
12-bit DAC
Threshold
Capacitance for AC
coupling
…
Analogue Memory
Charge Ouput
Time Ouput
29 sep 2006 C. de La Taille front-end electronics for ILC calorimeters. FJPPL KEK meeting 51
Conclusion
Several large dynamic range ASICs developped for CALICE physics prototypes ECAL W-Si calorimeter : FLC_PHY3 = 104