From Transistors To Computers
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From TransistorsTo Computers
Gajski and Kuhn’s Y Chart
Physical/Geometry
StructuralBehavioral
Processor
Hardware Modules
ALUs, Registers
Gates, FFs
Transistors
Systems
Algorithms
Register TransferLogic
Transfer Functions
Architectural
Algorithmic
Functional Block
Logic
Circuit
Rectangles
Cell, Module Plans
Floor Plans
Clusters
Physical Partitions
Discovery of the Electron -- 1898
J. J. ThomsonCathode Tube
Cavendish Labs
Electric Field -- “corpuscle”
Physical/Geometry
StructuralBehavioral
Processor
Hardware Modules
ALUs, Registers
Gates, FFs
Transistors
Systems
Algorithms
Register TransferLogic
Transfer Functions
Architectural
Algorithmic
Functional Block
Logic
Circuit
Rectangles
Cell, Module Plans
Floor Plans
Clusters
Physical Partitions
The Transistor
The Vacuum Tube
The FirstPoint-Contact
Transistor1947
Bell Labs Museum
The FirstJunction Transistor
1951
Bell Labs
Lab model
M1752Outside the Lab
The Field Effect Transistor
The Transistor
Texas Instrument’s First IC -- 1958
Jack Kilby
Robert NoyceFairchildIntel
CMOS Circuits
Physical/Geometry
StructuralBehavioral
Processor
Hardware Modules
ALUs, Registers
Gates, FFs
Transistors
Systems
Algorithms
Register TransferLogic
Transfer Functions
Architectural
Algorithmic
Functional Block
Logic
Circuit
Rectangles
Cell, Module Plans
Floor Plans
Clusters
Physical Partitions
Implementing Gates
Relays
Normally openNormally closed
A
B
C
A
B
C
A
B
C
nMOS transistorA-B closed whenC = 1(normally open)
pMOS transistorA-B closed whenC = 0(normally closed)
CMOS Circuits
Logic Circuits
X
Y
Logic Circuits
Logic Circuits - Functions
Logic Circuits - Multiplexers
4-line 2 x 1 Mux
n-line 2 x 1 MultiplexerLab 1
a(n-1:0)
b(n-1:0)
y(n-1:0)
sel
n-line2 x 1MUX
library IEEE;use IEEE.std_logic_1164.all; entity mux2g is generic(width:positive); port ( a: in STD_LOGIC_VECTOR(width-1 downto 0); b: in STD_LOGIC_VECTOR(width-1 downto 0); sel: in STD_LOGIC; y: out STD_LOGIC_VECTOR(width-1 downto 0) );end mux2g; architecture mux2g_arch of mux2g isbegin mux2_1: process(a, b, sel) begin if sel = '0' then y <= a; else y <= b; end if; end process mux2_1;end mux2g_arch;
VHDL – n-line 2 x 1 Multiplexer
ALU1- Shifting, Incr, and Decr Lab 2
a(n-1:0) y(n-1:0)
Sel(2:0)
n-line
ALU1
sel y Instruction name
“000” a + 1 1+
“001” a - 1 1-
“010” not a invert
“011” shift left a 2*
“100” logic shift right a U2/
“101” arithmetic shift right a
2/
“110” all ones true
“111” all zeros false
Logic Circuits - Binary Adder
Logic Circuits - Binary Adder
Logic Circuits - Full Adder
Binary Adder/Subtractor
ALU2 – Arithmetic and Logic InstructionsLab 3
a(n-1:0)y(n-1:0)
sel(2:0)
n-line
ALU2
b(n-1:0)
sel y Instruction name
“000” a + b +
“001” b - a -
“010” a and b AND
“011” a or b OR
“100” a xor b XOR
“101” true if a = 0false otherwise
0=
“110” true if a < 0false otherwise
0<
“111” true if b > a (unsigned)
false otherwise
U>
ALU3 – Comparators Lab 4
a(n-1:0)y(n-1:0)
sel(2:0)
n-line
ALU3
b(n-1:0)
sel y Instruction name
“000” true if b = afalse otherwise
=
“001” true if b /= afalse otherwise
<>
“010” true if b < a (unsigned)false otherwise
U<
“011” true if b > a (unsigned)false otherwise
U>
“100” true if b <= a (unsigned)
false otherwise
U<=
“101” true if b < a (signed)false otherwise
<
“110” true if b > a (signed)false otherwise
>
“111” true if b <= a (signed)false otherwise
<=
CMOS Circuits
Physical/Geometry
StructuralBehavioral
Processor
Hardware Modules
ALUs, Registers
Gates, FFs
Transistors
Systems
Algorithms
Register TransferLogic
Transfer Functions
Architectural
Algorithmic
Functional Block
Logic
Circuit
Rectangles
Cell, Module Plans
Floor Plans
Clusters
Physical Partitions
Latches and Flip-Flops
Latches and Flip-Flops
Latches and Flip-Flops
State Machines
ALUs, Registers
Physical/Geometry
StructuralBehavioral
Processor
Hardware Modules
ALUs, Registers
Gates, FFs
Transistors
Systems
Algorithms
Register TransferLogic
Transfer Functions
Architectural
Algorithmic
Functional Block
Logic
Circuit
Rectangles
Cell, Module Plans
Floor Plans
Clusters
Physical Partitions
An n-bit Register
q(n-1 downto 0)
clk clr
load
d(n-1 downto 0)
reg
A Function Unit (ALU1 – ALU3)
Funit1
y(n-1:0)
fcode(5:0)
b(n-1:0) a(n-1:0)
ALU
Datapath
Physical/Geometry
StructuralBehavioral
Processor
Hardware Modules
ALUs, Registers
Gates, FFs
Transistors
Systems
Algorithms
Register TransferLogic
Transfer Functions
Architectural
Algorithmic
Functional Block
Logic
Circuit
Rectangles
Cell, Module Plans
Floor Plans
Clusters
Physical Partitions
Datapath
A Single-Cycle Processor Lab 5
mux4g
Tregclk
clr
Nregclkclr
Funit1
T
N
tin
SW(1:8)
LD(1:8)
Fcode(5:0)
msel(1:0)
tloadnload
y
dig7seg
A(1:4) AtoG(6:0)
cclk
clr
T
Prom
Pcountclr
clk
M
P
M
a b
fcodemseltload
Ny ground
a cb d
nload
anode =“1111”
Program Counter and Program ControlLab 6
mux4
Tregclkclr
Nregclkclr
Funit1
T
N
tload
nload
tin
Pcontrol
Prom
pinc
M
P
nload
tload
icodemsel(1:0)
DigDisplay
A(1:4) AtoG(6:0)
SW(1:8)
LD(1:8)
clk
clr
T
T
N
digload
fcode(5:0)
BTN4
iregclkclr iload
digload
iloadfcode(5:0)
pinc
mclk clkdiv
clr
clk
M
clr
clk
PCclkclr pload
pload
y
yM
abcd
bn
cclk
IBUFG
ab
T
ldg‘1’
led
Lab6
Processor
Physical/Geometry
StructuralBehavioral
Processor
Hardware Modules
ALUs, Registers
Gates, FFs
Transistors
Systems
Algorithms
Register TransferLogic
Transfer Functions
Architectural
Algorithmic
Functional Block
Logic
Circuit
Rectangles
Cell, Module Plans
Floor Plans
Clusters
Physical Partitions
Originally with Transistors
A Close Up
ReturnStack
RmuxPmux
PCclrclk
pload
pinc
IRclrclkirload
W8Y_rom
W8Y_control
plus1
R
DS
Rin
R T
P
Pin
M
M P1
R
M
SW(1:8)
LDreg
LD(1:8)
T
ldloadclkclr
step_display
A(3:0) AtoG(6:0)
clk
clr
TN
BTN(1)
BTN(4)
clr
step
The W8YMicrocontroller
clkclr
rpop
rpush
psel rinsel
dssel(1:0)
rload
rdec
rsel
T
icode
E
BTN(1:4)
DataStack_ALUclkclr
dpop
dpush
ssel
nloadnsel
tload
tsel(1:0)
alusel(3:0)
T
0 11
1
0
0 2 3DSmux
W8ZProcessor
reg_stack
Funit
TN2 N1N3
d0
y1cout
clr
clk
Rcode(3:0)
Fcode(4:0)
msel(5:0)
Wcontrol
Wrom
WPC
clk
clr
inc2
M1(7:0) M2(7:0)
P
d1
ReturnStack
R
Pmux
Rmux
dual_mux8g
add1
sub1
ROM
RAM
T
T N1
y2
SW(1:8)
rsel(1:0)
psel
BTN(1:4)
rpush
rload
pselrsel
pload
DigReg
LDreg
dig3 dig1dig4 dig2
LD(1:8)
T
TN1
clrclk
rpush
rpop
pload
clrclk
rload
rdecclkclr
we
rpoprdec
ldloadclkclr
clk
clrdigload
P1
R
R1
RM1
p_in
r_in
T
T
ReturnStack
RmuxPmux
PCclrclk
pload
pinc
IRclrclkirload
FC16_control
plus1
R
Tin
Rin
R T
P
Pin
M
M P1
R
M
The FC16Forth Core
clkclr
rpop
rpush
psel rinsel
tsel(2:0)
rload
rdec
rsel
T
icode
E1(15:0)
B(1:4)DataStackclk
clr
dpop
dpush
ssel
nloadnsel
tload
y1(15:0)
T
0 11
1
0
0 2 3Tmux
Funit16
NN2
y(15:0)
y NN2E2E1S
S(1:8)
54 6 7
E2(15:0)
P(15:0)
M(15:0)
clr
clk
T(15:0)
N(15:0)
oe
we
cclk
Fcode(5:0)
digload
ldload
The FC16Forth Core
Tregclkclr
Nregclkclr
T1
Tin(15:0)
tload
nload
Nmux
Nin
T(15:0)
Smux
stack32x16
N1 T
N2
clkclr
dpop
dpush
empty
full
d
ssel
0
0
1
1
clkclr
dpop
dpush
ssel
nload
nsel(1:0)
tload
DataStack
y1(15:0)y1
2
N(15:0) N2(15:0)
nsel(1:0)
Data Stack
Lab 7
Return StackLab 8
Stack32x16
R
Rmuxrsel
clrclk
rpush
rpop
clrclk
rload
rdec
R
R1
r_in
Rin(15:0)
ReturnStack
clrclk
rpush
rpop
rload
rdec
rsel
01
R(15:0)
full
empty
ReturnStack
RmuxPmux
PCclrclk
pload
pinc
IRclrclkirload
WC16_control
plus1
R
Tin
Rin
R T
P
Pin
M
M P1
R
M
The WC16WHYP Core
clkclr
rpop
rpush
psel rinsel
tsel(2:0)
rload
rdec
rsel
T
icode
E1(15:0)
B(1:4)DataStackclk
clr
dpop
dpush
ssel
nloadnsel
tload
y1(15:0)
T
0 11
1
0
0 2 3Tmux
Funit2
NN2
y(15:0)
y NN2E2E1S
S(1:8)
54 6 7
E2(15:0)
P(15:0)
M(15:0)
clr
clk
T(15:0)
N(15:0)
oe
we
Fcode(5:0)
digload
cs
LCD_RW
LCD_RS
LCD_E
The WC16WHYP Core
Lab 9
Multi-cycle Computer
Pipelined Computer
CISC Processor
QuantumComputer
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