Freescale Semiconductor, Inc.jj — High-order byte of a 16-bit immediate data value. kk — Low-order byte of a 16-bit immediate data value. lb — Loop primitive (DBNE) post-byte.
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CPU12RG/DRev. 2, 11/2001
CPU12 Reference Guide(for HCS12 and original M68HC12)
Reference Guide
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Figure 1. Programming Model
7
15
15
15
15
15
D
X
Y
SP
PC
A B
NS X H I Z V C
0
0
0
0
0
0
70
CONDITION CODE REGISTER
8-BIT ACCUMULATORS A AND B
16-BIT DOUBLE ACCUMULATOR D
INDEX REGISTER X
INDEX REGISTER Y
STACK POINTER
PROGRAM COUNTER
OR
STOP DISABLE (IGNORE STOP OPCODES)RESET DEFAULT IS 1
CARRY
OVERFLOW
ZERO
NEGATIVE
MASK (DISABLE) IRQ INTERRUPTS
HALF-CARRY (USED IN BCD ARITHMETIC)
MASK (DISABLE) XIRQ INTERRUPTSRESET OR XIRQ SET X,INSTRUCTIONS MAY CLEAR X BUT CANNOT SET X
CPU Register NotationAccumulator A — A or a Index Register Y — Y or yAccumulator B — B or b Stack Pointer — SP, sp, or sAccumulator D — D or d Program Counter — PC, pc, or pIndex Register X — X or x Condition Code Register — CCR or c
2 CPU12 Reference Guide (for HCS12 and original M68HC12) MOTOROLA
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Explanation of Italic Expressions in Source Form Columnabc — A or B or CCR
abcdxys — A or B or CCR or D or X or Y or SP. Some assemblers also allow T2 or T3.abd — A or B or D
abdxys — A or B or D or X or Y or SPdxys — D or X or Y or SP
msk8 — 8-bit mask, some assemblers require # symbol before valueopr8i — 8-bit immediate value
opr16i — 16-bit immediate valueopr8a — 8-bit address used with direct address mode
oprx3,–xys Predecrement X or Y or SP by 1 . . . 8oprx3,+xys Preincrement X or Y or SP by 1 . . . 8oprx3,xys– Postdecrement X or Y or SP by 1 . . . 8oprx3,xys+ Postincrement X or Y or SP by 1 . . . 8oprx5,xysp 5-bit constant offset from X or Y or SP or PCabd,xysp Accumulator A or B or D offset from X or Y or SP or PC
oprx3 — Any positive integer 1 . . . 8 for pre/post increment/decrementoprx5 — Any integer in the range –16 . . . +15oprx9 — Any integer in the range –256 . . . +255
oprx16 — Any integer in the range –32,768 . . . 65,535page — 8-bit value for PPAGE, some assemblers require # symbol before this value
rel8 — Label of branch destination within –256 to +255 locationsrel9 — Label of branch destination within –512 to +511 locations
rel16 — Any label within 64K memory spacetrapnum — Any 8-bit integer in the range $30-$39 or $40-$FF
xys — X or Y or SPxysp — X or Y or SP or PC
Operators
+ — Addition
±
— Subtraction
• — Logical AND
+ — Logical OR (inclusive)
⊕ — Logical exclusive OR
× — Multiplication
÷ — Division
M — Negation. One’s complement (invert each bit of M)
: — ConcatenateExample: A : B means the 16-bit value formed by concatenating 8-bit accumulator A with 8-bit accumulator B.A is in the high-order position.
Continued on next page
MOTOROLA CPU12 Reference Guide (for HCS12 and original M68HC12) 3
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Operators (continued)
⇒ — TransferExample: (A) ⇒ M means the content of accumulator A is transferred to memory location M.
⇔ — ExchangeExample: D ⇔ X means exchange the contents of D with those of X.
Address Mode NotationINH — Inherent; no operands in object codeIMM — Immediate; operand in object codeDIR — Direct; operand is the lower byte of an address from $0000 to $00FFEXT — Operand is a 16-bit addressREL — Two’s complement relative offset; for branch instructionsIDX — Indexed (no extension bytes); includes:
5-bit constant offset from X, Y, SP, or PCPre/post increment/decrement by 1 . . . 8Accumulator A, B, or D offset
IDX1 — 9-bit signed offset from X, Y, SP, or PC; 1 extension byteIDX2 — 16-bit signed offset from X, Y, SP, or PC; 2 extension bytes
[IDX2] — Indexed-indirect; 16-bit offset from X, Y, SP, or PC[D, IDX] — Indexed-indirect; accumulator D offset from X, Y, SP, or PC
Machine Codingdd — 8-bit direct address $0000 to $00FF. (High byte assumed to be $00).ee — High-order byte of a 16-bit constant offset for indexed addressing.eb — Exchange/Transfer post-byte. See Table 3 on page 22.ff — Low-order eight bits of a 9-bit signed constant offset for indexed addressing,
or low-order byte of a 16-bit constant offset for indexed addressing.hh — High-order byte of a 16-bit extended address.ii — 8-bit immediate data value.jj — High-order byte of a 16-bit immediate data value.kk — Low-order byte of a 16-bit immediate data value.lb — Loop primitive (DBNE) post-byte. See Table 4 on page 23.ll — Low-order byte of a 16-bit extended address.mm — 8-bit immediate mask value for bit manipulation instructions.
Set bits indicate bits to be affected.pg — Program page (bank) number used in CALL instruction.qq — High-order byte of a 16-bit relative offset for long branches.tn — Trap number $30–$39 or $40–$FF.rr — Signed relative offset $80 (–128) to $7F (+127).
Offset relative to the byte following the relative offset byte, orlow-order byte of a 16-bit relative offset for long branches.
xb — Indexed addressing post-byte. See Table 1 on page 20 and Table 2 on page 21.
4 CPU12 Reference Guide (for HCS12 and original M68HC12) MOTOROLA
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Access Detail
Each code letter except (,), and comma equals one CPU cycle. Uppercase = 16-bit operation and lowercase = 8-bit operation. For complex sequences see the CPU12 Reference Manual (CPU12RM/AD) for more detailed information.
Condition Codes Columns
f — Free cycle, CPU doesn’t use busg — Read PPAGE internallyI — Read indirect pointer (indexed indirect)i — Read indirect PPAGE value (CALL indirect only)n — Write PPAGE internallyO — Optional program word fetch (P) if instruction is misaligned and has
an odd number of bytes of object code — otherwise, appears as a free cycle (f); Page 2 prebyte treated as a separate 1-byte instruction
P — Program word fetch (always an aligned-word read)r — 8-bit data readR — 16-bit data reads — 8-bit stack writeS — 16-bit stack writew — 8-bit data writeW — 16-bit data writeu — 8-bit stack readU — 16-bit stack readV — 16-bit vector fetch (always an aligned-word read)t — 8-bit conditional read (or free cycle)T — 16-bit conditional read (or free cycle)x — 8-bit conditional write (or free cycle)
() — Indicate a microcode loop, — Indicates where an interrupt could be honored
Special Cases
PPP/P — Short branch, PPP if branch taken, P if notOPPP/OPO — Long branch, OPPP if branch taken, OPO if not
– — Status bit not affected by operation.0 — Status bit cleared by operation.1 — Status bit set by operation.∆ — Status bit affected by operation.? — Status bit may be cleared or remain set, but is not set by operation.⇑ — Status bit may be set or remain cleared, but is not cleared by operation.? — Status bit may be changed by operation but the final state is not defined.! — Status bit used for a special purpose.
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(B) • (M)Logical AND B with MemoryDoes not change Accumulator or Memory
IMMDIREXTIDX
IDX1IDX2
[D,IDX][IDX2]
C5 iiD5 ddF5 hh llE5 xbE5 xb ffE5 xb ee ffE5 xbE5 xb ee ff
PrPfrPOrPfrPOfrPPfIfrPffIPrPf
PrfPrOPrfPrPOfrPP
fIfrfPfIPrfP
– – – – ∆ ∆ 0 –
BLE rel8 Branch if Less Than or Equal(if Z + (N ⊕ V) = 1) (signed)
REL 2F rr PPP/P1 PPP/P1 – – – – – – – –
BLO rel8 Branch if Lower(if C = 1) (unsigned)same function as BCS
REL 25 rr PPP/P1 PPP/P1 – – – – – – – –
Note 1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.
Instruction Set Summary (Sheet 2 of 14)
Source Form Operation Addr.Mode
MachineCoding (hex)
Access DetailS X H I N Z V C
HCS12 HC12
C0
b7 b0
C0
b7 b0A Bb7b0
Cb7 b0
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BLS rel8 Branch if Lower or Same(if C + Z = 1) (unsigned)
REL 23 rr PPP/P1 PPP/P1 – – – – – – – –
BLT rel8 Branch if Less Than(if N ⊕ V = 1) (signed)
REL 2D rr PPP/P1 PPP/P1 – – – – – – – –
BMI rel8 Branch if Minus (if N = 1) REL 2B rr PPP/P1 PPP/P1 – – – – – – – –
BNE rel8 Branch if Not Equal (if Z = 0) REL 26 rr PPP/P1 PPP/P1 – – – – – – – –
BPL rel8 Branch if Plus (if N = 0) REL 2A rr PPP/P1 PPP/P1 – – – – – – – –
0 ⇒ A Clear Accumulator A0 ⇒ B Clear Accumulator B
EXTIDX
IDX1IDX2
[D,IDX][IDX2]INHINH
79 hh ll69 xb69 xb ff69 xb ee ff69 xb69 xb ee ff87C7
PwOPwPwOPwPPIfwPIPwOO
wOPPwPwOPwP
PIfPwPIPPw
OO
– – – – 0 1 0 0
CLV 0 ⇒ VTranslates to ANDCC #$FD
IMM 10 FD P P – – – – – – 0 –
Note 1. PPP/P indicates this instruction takes three cycles to refill the instruction queue if the branch is taken and one program fetch cycle if the branch is not taken.
Instruction Set Summary (Sheet 3 of 14)
Source Form Operation Addr.Mode
MachineCoding (hex)
Access DetailS X H I N Z V C
HCS12 HC12
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88 ii98 ddB8 hh llA8 xbA8 xb ffA8 xb ee ffA8 xbA8 xb ee ff
PrPfrPOrPfrPOfrPPfIfrPffIPrPf
PrfPrOPrfPrPOfrPP
fIfrfPfIPrfP
– – – – ∆ ∆ 0 –
Notes:1. Due to internal CPU requirements, the program word fetch is performed twice to the same address during this instruction.2. opr16a is an extended address specification. Both X and Y point to source operands.
Instruction Set Summary (Sheet 5 of 14)
Source Form Operation Addr.Mode
MachineCoding (hex)
Access DetailS X H I N Z V C
HCS12 HC12
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CC jj kkDC ddFC hh llEC xbEC xb ffEC xb ee ffEC xbEC xb ee ff
PORPfRPORPfRPOfRPPfIfRPffIPRPf
OPRfPROPRfPRPOfRPP
fIfRfPfIPRfP
– – – – ∆ ∆ 0 –
Note 1. OPPP/OPO indicates this instruction takes four cycles to refill the instruction queue if the branch is taken and three cycles if the branch is not taken.
Instruction Set Summary (Sheet 7 of 14)
Source Form Operation Addr.Mode
MachineCoding (hex)
Access DetailS X H I N Z V C
HCS12 HC12
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N, Z, V and C status bits reflect result ofinternal compare ((A) – (M)).
IDXIDX1IDX2
[D,IDX][IDX2]
18 1C xb18 1C xb ff18 1C xb ee ff18 1C xb18 1C xb ee ff
OrPwOrPwOOfrPwPOfIfrPwOfIPrPw
OrPwOrPwOOfrPwPOfIfrPwOfIPrPw
– – – – ∆ ∆ ∆ ∆
MEM µ (grade) ⇒ M(Y);(X) + 4 ⇒ X; (Y) + 1 ⇒ Y; A unchanged
if (A) < P1 or (A) > P2 then µ = 0, elseµ = MIN[((A) – P1)×S1, (P2 – (A))×S2, $FF]where:A = current crisp input value;X points at 4-byte data structure that describes a trapezoidal membership function (P1, P2, S1, S2);Y points at fuzzy input (RAM location).See CPU12 Reference Manual for special cases.
Special 01 RRfOw RRfOw – – ? – ? ? ? ?
MINA oprx0_xyspMINA oprx9,xyspMINA oprx16,xyspMINA [D,xysp]MINA [oprx16,xysp]
MIN((A), (M)) ⇒ AMIN of 2 Unsigned 8-Bit Values
N, Z, V and C status bits reflect result ofinternal compare ((A) – (M)).
IDXIDX1IDX2
[D,IDX][IDX2]
18 19 xb18 19 xb ff18 19 xb ee ff18 19 xb18 19 xb ee ff
PULD (M(SP):M(SP+1)) ⇒ A:B; (SP) + 2 ⇒ SPPull D from Stack
INH 3A UfO UfO – – – – – – – –
PULX (M(SP):M(SP+1)) ⇒ XH:XL; (SP) + 2 ⇒ SPPull Index Register X from Stack
INH 30 UfO UfO – – – – – – – –
PULY (M(SP):M(SP+1)) ⇒ YH:YL; (SP) + 2 ⇒ SPPull Index Register Y from Stack
INH 31 UfO UfO – – – – – – – –
REV MIN-MAX rule evaluationFind smallest rule input (MIN).Store to rule outputs unless fuzzy output is already larger (MAX).
For rule weights see REVW.
Each rule input is an 8-bit offset from the base address in Y. Each rule output is an 8-bit offset from the base address in Y. $FE separates rule inputs from rule outputs. $FF terminates the rule list.
REVW MIN-MAX rule evaluationFind smallest rule input (MIN),Store to rule outputs unless fuzzy output is already larger (MAX).
Rule weights supported, optional.
Each rule input is the 16-bit address of a fuzzy input. Each rule output is the 16-bit address of a fuzzy output. The value $FFFE separates rule inputs from rule outputs. $FFFF terminates the rule list.
REVW may be interrupted.
Special 18 3B ORf(t,Tx)O ORf(t,Tx)O – – ? – ? ? ∆ !(loop to read weight if enabled)
(r,RfRf) (r,RfRf)
(exit + re-entry replaces comma above if interrupted)
ffff + ORf(t, fff + ORf(t,
Instruction Set Summary (Sheet 10 of 14)
Source Form Operation Addr.Mode
MachineCoding (hex)
Access DetailS X H I N Z V C
HCS12 HC12
MOTOROLA CPU12 Reference Guide (for HCS12 and original M68HC12) 15
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ROL opr16aROL oprx0_xyspROL oprx9,xyspROL oprx16,xyspROL [D,xysp]ROL [oprx16,xysp]ROLAROLB
Rotate Memory Left through Carry
Rotate A Left through CarryRotate B Left through Carry
EXTIDX
IDX1IDX2
[D,IDX][IDX2]INHINH
75 hh ll65 xb65 xb ff65 xb ee ff65 xb65 xb ee ff4555
Calculate Sum of Products and Sum of Weights for Weighted Average Calculation
Initialize B, X, and Y before WAV. B specifies number of ele-ments. X points at first element in Si list. Y points at first ele-ment in Fi list.
All Si and Fi elements are 8-bits.
If interrupted, six extra bytes of stack used for intermediate values
Special 18 3C Of(frr,ffff)OOff(frr,fffff)O
– – ? – ? ∆ ? ?
(add if interrupt)
SSS + UUUrr, SSSf + UUUrr
wavr
pseudo-instruction
see WAV
Resume executing an interrupted WAV instruction (recover in-termediate results from stack rather than initializing them to zero)
Special 3C UUUrr,ffff(frr,ffff)O
UUUrrfffff(frr,fffff)O
– – ? – ? ∆ ? ?
(exit + re-entry replaces commaabove if interrupted)
SSS + UUUrr, SSSf + UUUrr
XGDX (D) ⇔ (X)Translates to EXG D, X
INH B7 C5 P P – – – – – – – –
XGDY (D) ⇔ (Y)Translates to EXG D, Y
INH B7 C6 P P – – – – – – – –
Instruction Set Summary (Sheet 14 of 14)
Source Form Operation Addr.Mode
MachineCoding (hex)
Access DetailS X H I N Z V C
HCS12 HC12
Fi
i 1=
B
∑ X⇒SiFi
i 1=
B
∑ Y:D⇒ and
MOTOROLA CPU12 Reference Guide (for HCS12 and original M68HC12) 19
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Tab
le 1
. In
dex
ed A
dd
ress
ing
Mo
de
Po
stb
yte
En
cod
ing
(xb
)00
0,X
5b c
onst
10–1
6,X
5b c
onst
201,
+X
pre-
inc
301,
X+
post
-inc
400
,Y5b
con
st
50–1
6,Y
5b c
onst
601,
+Y
pre-
inc
701,
Y+
post
-inc
800,
SP
5b c
onst
90–1
6,S
P5b
con
st
A0 1,
+S
Ppr
e-in
c
B0 1,
SP
+po
st-in
c
C0
0,P
C5b
con
st
D0 –1
6,P
C5b
con
st
E0
n,X
9b c
onst
F0
n,S
P9b
con
st01
1,X
5b c
onst
11–1
5,X
5b c
onst
212,
+X
pre-
inc
312,
X+
post
-inc
411
,Y5b
con
st
51–1
5,Y
5b c
onst
612,
+Y
pre-
inc
712,
Y+
post
-inc
811,
SP
5b c
onst
91–1
5,S
P5b
con
st
A1 2,
+S
Ppr
e-in
c
B1 2,
SP
+po
st-in
c
C1
1,P
C5b
con
st
D1 –1
5,P
C5b
con
st
E1
–n,
X9b
con
st
F1
–n,S
P9b
con
st02
2,X
5b c
onst
12–1
4,X
5b c
onst
223,
+X
pre-
inc
323,
X+
post
-inc
422
,Y5b
con
st
52–1
4,Y
5b c
onst
623,
+Y
pre-
inc
723,
Y+
post
-inc
822,
SP
5b c
onst
92–1
4,S
P5b
con
st
A2 3,
+S
Ppr
e-in
c
B2 3,
SP
+po
st-in
c
C2
2,P
C5b
con
st
D2 –1
4,P
C5b
con
st
E2
n,X
16b
cons
t
F2
n,S
P16
b co
nst
033
,X5b
con
st
13–1
3,X
5b c
onst
234,
+X
pre-
inc
334,
X+
post
-inc
433
,Y5b
con
st
53–1
3,Y
5b c
onst
634,
+Y
pre-
inc
734,
Y+
post
-inc
833,
SP
5b c
onst
93–1
3,S
P5b
con
st
A3 4,
+S
Ppr
e-in
c
B3 4,
SP
+po
st-in
c
C3
3,P
C5b
con
st
D3 –1
3,P
C5b
con
st
E3
[n,X
]16
b in
dr
F3
[n,S
P]
16b
indr
044
,X5b
con
st
14–1
2,X
5b c
onst
245,
+X
pre-
inc
345,
X+
post
-inc
444
,Y5b
con
st
54–1
2,Y
5b c
onst
645,
+Y
pre-
inc
745,
Y+
post
-inc
844,
SP
5b c
onst
94–1
2,S
P5b
con
st
A4 5,
+S
Ppr
e-in
c
B4 5,
SP
+po
st-in
c
C4
4,P
C5b
con
st
D4 –1
2,P
C5b
con
st
E4
A,X
A o
ffset
F4
A,S
PA
offs
et05
5,X
5b c
onst
15–1
1,X
5b c
onst
256,
+X
pre-
inc
356,
X+
post
-inc
455
,Y5b
con
st
55–
11,Y
5b c
onst
656,
+Y
pre-
inc
756,
Y+
post
-inc
855,
SP
5b c
onst
95–1
1,S
P5b
con
st
A5 6,
+S
Ppr
e-in
c
B5 6,
SP
+po
st-in
c
C5
5,P
C5b
con
st
D5 –1
1,P
C5b
con
st
E5
B,X
B o
ffset
F5
B,S
PB
offs
et06
6,X
5b c
onst
16–1
0,X
5b c
onst
267,
+X
pre-
inc
367,
X+
post
-inc
466
,Y5b
con
st
56–1
0,Y
5b c
onst
667,
+Y
pre-
inc
767,
Y+
post
-inc
866,
SP
5b c
onst
96–1
0,S
P5b
con
st
A6 7,
+S
Ppr
e-in
c
B6 7,
SP
+po
st-in
c
C6
6,P
C5b
con
st
D6 –1
0,P
C5b
con
st
E6
D,X
D o
ffset
F6
D,S
PD
offs
et07
7,X
5b c
onst
17–
9,X
5b c
onst
278,
+X
pre-
inc
378,
X+
post
-inc
477
,Y5b
con
st
57–
9,Y
5b c
onst
678,
+Y
pre-
inc
778,
Y+
post
-inc
877,
SP
5b c
onst
97–9
,SP
5b c
onst
A7 8,
+S
Ppr
e-in
c
B7 8,
SP
+po
st-in
c
C7
7,P
C5b
con
st
D7 –9
,PC
5b c
onst
E7
[D,X
]D
indi
rect
F7 [D
,SP
]D
indi
rect
088
,X5b
con
st
18–
8,X
5b c
onst
288
,–X
pre-
dec
388
,X–
post
-dec
488
,Y5b
con
st
58–
8,Y
5b c
onst
688
,–Y
pre-
dec
788
,Y–
post
-dec
888,
SP
5b c
onst
98–8
,SP
5b c
onst
A8 8,
–SP
pre-
dec
B8 8,
SP
–po
st-d
ec
C8
8,P
C5b
con
st
D8 –8
,PC
5b c
onst
E8
n,Y
9b c
onst
F8
n,P
C9b
con
st09
9,X
5b c
onst
19–
7,X
5b c
onst
297
,–X
pre-
dec
397
,X–
post
-dec
499
,Y5b
con
st
59–
7,Y
5b c
onst
697
,–Y
pre-
dec
797
,Y–
post
-dec
899,
SP
5b c
onst
99–7
,SP
5b c
onst
A9 7,
–SP
pre-
dec
B9 7,
SP
–po
st-d
ec
C9
9,P
C5b
con
st
D9 –7
,PC
5b c
onst
E9
–n,
Y9b
con
st
F9 –n
,PC
9b c
onst
0A1
0,X
5b c
onst
1A–
6,X
5b c
onst
2A6
,–X
pre-
dec
3A6
,X–
post
-dec
4A1
0,Y
5b c
onst
5A–
6,Y
5b c
onst
6A6
,–Y
pre-
dec
7A6
,Y–
post
-dec
8A10
,SP
5b c
onst
9A–6
,SP
5b c
onst
AA 6,
–SP
pre-
dec
BA 6,
SP
–po
st-d
ec
CA 10
,PC
5b c
onst
DA –6
,PC
5b c
onst
EA
n,Y
16b
cons
t
FAn,
PC
16b
cons
t0B
11,X
5b c
onst
1B–
5,X
5b c
onst
2B5
,–X
pre-
dec
3B5
,X–
pos
t-de
c
4B11
,Y5b
con
st
5B–
5,Y
5b c
onst
6B5
,–Y
pre-
dec
7B5
,Y–
post
-dec
8B11
,SP
5b c
onst
9B–5
,SP
5b c
onst
AB 5,
–SP
pre-
dec
BB 5,
SP
–po
st-d
ec
CB 11
,PC
5b c
onst
DB –5
,PC
5b c
onst
EB
[n,Y
]16
b in
dr
FB [n
,PC
]16
b in
dr0C
12,
X5b
con
st
1C–
4,X
5b c
onst
2C4
,–X
pre-
dec
3C4
,X–
post
-dec
4C1
2,Y
5b c
onst
5C–
4,Y
5b c
onst
6C4
,–Y
pre-
dec
7C4
,Y–
post
-dec
8C12
,SP
5b c
onst
9C–4
,SP
5b c
onst
AC 4,
–SP
pre-
dec
BC 4,
SP
–po
st-d
ec
CC 12
,PC
5b c
onst
DC –4
,PC
5b c
onst
EC
A,Y
A o
ffset
FC
A,P
CA
offs
et0D
13,
X5b
con
st
1D–
3,X
5b c
onst
2D3
,–X
pre-
dec
3D3
,X–
post
-dec
4D1
3,Y
5b c
onst
5D–
3,Y
5b c
onst
6D3
,–Y
pre-
dec
7D3
,Y–
post
-dec
8D13
,SP
5b c
onst
9D–3
,SP
5b c
onst
AD 3,
–SP
pre-
dec
BD 3,
SP
–po
st-d
ec
CD 13
,PC
5b c
onst
DD –3
,PC
5b c
onst
ED
B,Y
B o
ffset
FD
B,P
CB
offs
et0E
14,
X5b
con
st
1E–
2,X
5b c
onst
2E2
,–X
pre-
dec
3E2
,X–
post
-dec
4E1
4,Y
5b c
onst
5E–
2,Y
5b c
onst
6E2
,–Y
pre-
dec
7E2
,Y–
post
-dec
8E14
,SP
5b c
onst
9E–2
,SP
5b c
onst
AE 2,
–SP
pre-
dec
BE 2,
SP
–po
st-d
ec
CE 14
,PC
5b c
onst
DE –2
,PC
5b c
onst
EE
D,Y
D o
ffset
FE
D,P
CD
offs
et0F
15,
X5b
con
st
1F–
1,X
5b c
onst
2F1
,–X
pre-
dec
3F1
,X–
post
-dec
4F1
5,Y
5b c
onst
5F–
1,Y
5b c
onst
6F1
,–Y
pre-
dec
7F1
,Y–
post
-dec
8F15
,SP
5b c
onst
9F–1
,SP
5b c
onst
AF 1,
–SP
pre-
dec
BF 1,
SP
–po
st-d
ec
CF 15
,PC
5b c
onst
DF –1
,PC
5b c
onst
EF
[D,Y
]D
indi
rect
FF [D
,PC
]D
indi
rect
post
byte
(he
x)B
0 #,R
EG
type
type
offs
et u
sed
sour
ce c
ode
synt
ax
Key
to
Tab
le 1
20 CPU12 Reference Guide (for HCS12 and original M68HC12) MOTOROLA
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Table 2. Indexed Addressing Mode Summary
PostbyteCode (xb)
OperandSyntax Comments
rr0nnnnn ,rn,r–n,r
5-bit constant offset n = –16 to +15rr can specify X, Y, SP, or PC
111rr0zs n,r–n,r
Constant offset (9- or 16-bit signed)z- 0 = 9-bit with sign in LSB of postbyte (s)
1 = 16-bitif z = s = 1, 16-bit offset indexed-indirect (see below)rr can specify X, Y, SP, or PC
rr1pnnnn n,–rn,+rn,r– n,r+
Auto predecrement, preincrement, postdecrement, or postincrement; p = pre-(0) or post-(1), n = –8 to –1, +1 to +8rr can specify X, Y, or SP (PC not a valid choice)
111rr1aa A,rB,rD,r
Accumulator offset (unsigned 8-bit or 16-bit)aa - 00 = A
01 = B10 = D (16-bit)11 = see accumulator D offset indexed-indirect
rr can specify X, Y, SP, or PC
111rr011 [n,r] 16-bit offset indexed-indirectrr can specify X, Y, SP, or PC
111rr111 [D,r] Accumulator D offset indexed-indirectrr can specify X, Y, SP, or PC
MOTOROLA CPU12 Reference Guide (for HCS12 and original M68HC12) 21
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Tab
le 3
. Tra
nsf
er a
nd
Exc
han
ge
Po
stb
yte
En
cod
ing
TR
AN
SF
ER
S
⇓ L
SM
S⇒
01
23
45
67
0A
⇒ A
B ⇒
AC
CR
⇒ A
TM
P3 L
⇒ A
B ⇒
AX
L ⇒
AY
L ⇒
AS
PL
⇒ A
1A
⇒ B
B ⇒
BC
CR
⇒ B
TM
P3 L
⇒ B
B ⇒
BX
L ⇒
BY
L ⇒
BS
PL
⇒ B
2A
⇒ C
CR
B ⇒
CC
RC
CR
⇒ C
CR
TM
P3 L
⇒ C
CR
B ⇒
CC
RX
L ⇒
CC
RY
L ⇒
CC
RS
PL
⇒ C
CR
3se
x:A
⇒ T
MP
2se
x:B
⇒ T
MP
2se
x:C
CR
⇒ T
MP
2T
MP
3 ⇒
TM
P2
D ⇒
TM
P2
X ⇒
TM
P2
Y ⇒
TM
P2
SP
⇒ T
MP
2
4se
x:A
⇒ D
SE
X A
,Dse
x:B
⇒ D
SE
X B
,Dse
x:C
CR
⇒ D
SE
X C
CR
,DT
MP
3 ⇒
DD
⇒ D
X ⇒
DY
⇒ D
SP
⇒ D
5se
x:A
⇒ X
SE
X A
,Xse
x:B
⇒ X
SE
X B
,Xse
x:C
CR
⇒ X
SE
X C
CR
,XT
MP
3 ⇒
XD
⇒ X
X ⇒
XY
⇒ X
SP
⇒ X
6se
x:A
⇒ Y
SE
X A
,Yse
x:B
⇒ Y
SE
X B
,Yse
x:C
CR
⇒ Y
SE
X C
CR
,YT
MP
3 ⇒
YD
⇒ Y
X ⇒
YY
⇒ Y
SP
⇒ Y
7se
x:A
⇒ S
PS
EX
A,S
Pse
x:B
⇒ S
PS
EX
B,S
Pse
x:C
CR
⇒ S
PS
EX
CC
R,S
PT
MP
3 ⇒
SP
D ⇒
SP
X ⇒
SP
Y ⇒
SP
SP
⇒ S
P
EX
CH
AN
GE
S
⇓ L
SM
S⇒
89
AB
CD
EF
0 A
⇔ A
B ⇔
AC
CR
⇔ A
TM
P3 L
⇒ A
$00:
A ⇒
TM
P3
B ⇒
AA
⇒ B
XL
⇒ A
$00:
A ⇒
XY
L ⇒
A$0
0:A
⇒ Y
SP
L ⇒
A$0
0:A
⇒ S
P
1A
⇔ B
B ⇔
BC
CR
⇔ B
TM
P3 L
⇒ B
$FF
:B ⇒
TM
P3
B ⇒
B$F
F ⇒
AX
L ⇒
B$F
F:B
⇒ X
YL
⇒ B
$FF
:B ⇒
YS
PL
⇒ B
$FF
:B ⇒
SP
2A
⇔ C
CR
B ⇔
CC
RC
CR
⇔ C
CR
TM
P3 L
⇒ C
CR
$FF
:CC
R ⇒
TM
P3
B ⇒
CC
R$F
F:C
CR
⇒ D
XL
⇒ C
CR
$FF
:CC
R ⇒
XY
L ⇒
CC
R$F
F:C
CR
⇒ Y
SP
L ⇒
CC
R$F
F:C
CR
⇒ S
P
3$0
0:A
⇒ T
MP
2T
MP
2 L ⇒
A$0
0:B
⇒ T
MP
2T
MP
2 L ⇒
B$0
0:C
CR
⇒ T
MP
2T
MP
2 L ⇒
CC
RT
MP
3 ⇔
TM
P2
D ⇔
TM
P2
X ⇔
TM
P2
Y ⇔
TM
P2
SP
⇔ T
MP
2
4 $0
0:A
⇒ D
$00:
B ⇒
D$0
0:C
CR
⇒ D
B ⇒
CC
RT
MP
3 ⇔
DD
⇔ D
X ⇔
DY
⇔ D
SP
⇔ D
5$0
0:A
⇒ X
XL
⇒ A
$00:
B ⇒
XX
L ⇒
B$0
0:C
CR
⇒ X
XL
⇒ C
CR
TM
P3
⇔ X
D ⇔
XX
⇔ X
Y ⇔
XS
P ⇔
X
6 $0
0:A
⇒ Y
YL
⇒ A
$00:
B ⇒
YY
L ⇒
B$0
0:C
CR
⇒ Y
YL
⇒ C
CR
TM
P3
⇔ Y
D ⇔
YX
⇔ Y
Y ⇔
YS
P ⇔
Y
7$0
0:A
⇒ S
PS
PL
⇒ A
$00:
B ⇒
SP
SP
L ⇒
B$0
0:C
CR
⇒ S
PS
PL
⇒ C
CR
TM
P3
⇔ S
PD
⇔ S
PX
⇔ S
PY
⇔ S
PS
P ⇔
SP
TM
P2
and
TM
P3
regi
ster
s ar
e fo
r fa
ctor
y us
e on
ly.
22 CPU12 Reference Guide (for HCS12 and original M68HC12) MOTOROLA
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Table 4. Loop Primitive Postbyte Encoding (lb)00 A
DBEQ(+)
10 ADBEQ
(–)
20 ADBNE
(+)
30 ADBNE
(–)
40 ATBEQ
(+)
50 ATBEQ
(–)
60 ATBNE
(+)
70 ATBNE
(–)
80 AIBEQ
(+)
90 AIBEQ
(–)
A0 AIBNE
(+)
B0 AIBNE
(–)01 B
DBEQ(+)
11 BDBEQ
(–)
21 BDBNE
(+)
31 BDBNE
(–)
41 BTBEQ
(+)
51 BTBEQ
(–)
61 BTBNE
(+)
71 BTBNE
(–)
81 BIBEQ
(+)
91 BIBEQ
(–)
A1 BIBNE
(+)
B1 BIBNE
(–)02
—12
—22
—32
—42
—52
—62
—72
—82
—92
—A2
—B2
—
03—
13—
23—
33—
43—
53—
63—
73—
83—
93—
A3—
B3—
04 DDBEQ
(+)
14 DDBEQ
(–)
24 DDBNE
(+)
34 DDBNE
(–)
44 DTBEQ
(+)
54 DTBEQ
(–)
64 DTBNE
(+)
74 DTBNE
(–)
84 DIBEQ
(+)
94 DIBEQ
(–)
A4 DIBNE
(+)
B4 DIBNE
(–)05 X
DBEQ(+)
15 XDBEQ
(–)
25 XDBNE
(+)
35 XDBNE
(–)
45 XTBEQ
(+)
55 XTBEQ
(–)
65 XTBNE
(+)
75 XTBNE
(–)
85 XIBEQ
(+)
95 XIBEQ
(–)
A5 XIBNE
(+)
B5 XIBNE
(–)06 Y
DBEQ(+)
16 YDBEQ
(–)
26 YDBNE
(+)
36 YDBNE
(–)
46 YTBEQ
(+)
56 YTBEQ
(–)
66 YTBNE
(+)
76 YTBNE
(–)
86 YIBEQ
(+)
96 YIBEQ
(–)
A6 YIBNE
(+)
B6 YIBNE
(–)07 SP
DBEQ(+)
17 SPDBEQ
(–)
27 SPDBNE
(+)
37 SPDBNE
(–)
47 SPTBEQ
(+)
57 SPTBEQ
(–)
67 SPTBNE
(+)
77 SPTBNE
(–)
87 SPIBEQ
(+)
97 SPIBEQ
(–)
A7 SPIBNE
(+)
B7 SPIBNE
(–)
postbyte (hex)B0 A_BEQ
(–)
counter used
sign of 9-bit relative branch offset(lower eight bits are an extension byte following postbyte)
branch condition
Key to Table 4
(bit 3 is don’t care)
Table 5. Branch/Complementary Branch
Branch Complementary BranchTest Mnemonic Opcode Boolean Test Mnemonic Opcode Comment r>m BGT 2E Z + (N ⊕ V) = 0 r≤m BLE 2F Signed r≥m BGE 2C N ⊕ V = 0 r<m BLT 2D Signed r=m BEQ 27 Z = 1 r≠m BNE 26 Signed r≤m BLE 2F Z + (N ⊕ V) = 1 r>m BGT 2E Signed r<m BLT 2D N ⊕ V = 1 r≥m BGE 2C Signed r>m BHI 22 C + Z = 0 r≤m BLS 23 Unsigned r≥m BHS/BCC 24 C = 0 r<m BLO/BCS 25 Unsigned r=m BEQ 27 Z = 1 r≠m BNE 26 Unsigned r≤m BLS 23 C + Z = 1 r>m BHI 22 Unsigned r<m BLO/BCS 25 C = 1 r≥m BHS/BCC 24 Unsigned
Carry BCS 25 C = 1 No Carry BCC 24 Simple Negative BMI 2B N = 1 Plus BPL 2A Simple Overflow BVS 29 V = 1 No Overflow BVC 28 Simple
r=0 BEQ 27 Z = 1 r≠0 BNE 26 Simple Always BRA 20 — Never BRN 21 Unconditional
For 16-bit offset long branches precede opcode with a $18 page prebyte.
MOTOROLA CPU12 Reference Guide (for HCS12 and original M68HC12) 23
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Memory Expansion
There are three basic memory expansion configurations in the M68HC12 and HCS12 MCU Families.
1. Basic 64 Kbyte memory map with no additional expanded memory support
2. >5 megabyte expanded memory support with 8-bit PPAGE, DPAGE, and EPAGE registers (MC68HC812A4 only)
3. >1 megabyte expanded memory support with 6-bit PPAGE register only — This configuration applies to all currently available HC12 and HCS12 devices with >60 Kbytes of on-chip FLASH memory.
Memory precedence— Highest —On-chip registers (usually $0000 or $1000)BDM ROM (only when BDM active)On-chip RAMOn-chip EEPROMOn-chip program memory (FLASH or ROM)Expansion windows (on MCUs with expanded memory)Other external memory— Lowest —
CPU sees 64 Kbytes of address space (CPU_ADDR [15:0])PPAGE 8-bit register to select 1 of 256 —16 Kbyte program pages
or 6-bit register to select 1 of 64 — 16 Kbyte program pagesDPAGE 8-bit register to select 1 of 256 — 4 Kbyte data pagesEPAGE 8-bit register to select 1 of 256 — 1 Kbyte extra pages
Extended address is up to 22 bits (EXT_ADDR [21:0])Program expansion window works with CALL and RTC instructions to simplify program access to extended memory space. Data and extra expansion windows (when present) use traditional banked expansion memory techniques.
24 CPU12 Reference Guide (for HCS12 and original M68HC12) MOTOROLA
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Program windowIf CPU_ADDR [15:0] = $8000–BFFF and PWEN = 1
Program window works with CALL/RTC to automate bank switching. 256 pages (banks) of 16 Kbytes each = 4 megabytes or 64 pages (banks) of 16 Kbytes each = 1 megabyte
Data window (when present)If CPU_ADDR [15:0] = $7000–7FFF and DWEN = 1
Then EXT_ADDR [21:0] = 1:1:DPAGE [7:0]:CPU_ADDR [11:0]User program controls DPAGE value
Extra window (when present)If CPU_ADDR [15:0] = $0000–03FF and EWDIR = 1
and EWEN = 1or CPU_ADDR [15:0] = $0400–07FF and EWDIR = 0
and EWEN = 1Then EXT_ADDR [21:0] = 1:1:1:1:EPAGE [7:0]:CPU_ADDR
[9:0]User program controls EPAGE value
CPU address not in any enabled windowEXT_ADDR [21:0] = 1:1:1:1:1:1:CPU_ADDR [15:0] (4 megabyte map)
or (for 1 megabyte map)If CPU_ADDR [15:0] = $0000–3FFF
Then EXT_ADDR [19:0] = 1:1:1:1:0:1:CPU_ADDR [13:0]This causes the FLASH at PPAGE $3D to also appearas unpaged memory at CPU addresses $0000–3FFF.
If CPU_ADDR [15:0] = $4000–7FFFThen EXT_ADDR [19:0] = 1:1:1:1:1:0:CPU_ADDR [13:0]
This causes the FLASH at PPAGE $3E to also appearas unpaged memory at CPU addresses $4000–7FFF.
If CPU_ADDR [15:0] = $C000–FFFFThen EXT_ADDR [19:0] = 1:1:1:1:1:1:CPU_ADDR [13:0]
This causes the FLASH at PPAGE $3F to also appear as unpaged memory at CPU addresses $C000–FFFF.
MOTOROLA CPU12 Reference Guide (for HCS12 and original M68HC12) 25
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Figure 2. Memory Mapping in 1-Megabyte Map
64 PAGES OF 16 KBYTES EACH VIEWED THROUGH P-WINDOW0 0000
3 0000
C 0000
E FFFFF 0000
F 8000
F BFFF
F FFFFFFFF
0000
1FFF
3FFF
5FFF
6FFF
7FFF
DFFF
BFFF
9FFFP WINDOW
PPAGE($3F)
63
PPAGE($3E)
62
PPAGE($3D)
61
PPAGE($3C)
60
CPU_ADDR EXT_ADR
2000
4000
040007FF
6000
7000
8000 F 0000
A000
C000 F C000
E000
“PPAGE($3D)
“image”
“PPAGE($3E)
“image”
“PPAGE($3F)
“image”
26 CPU12 Reference Guide (for HCS12 and original M68HC12) MOTOROLA
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Figure 3. Memory Mapping in 4-Megabyte Map
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
DPAGE($F1)241
DPAGE($F2)242
DPAGE($F3)243
DPAGE($F4)244
DPAGE($F5)245
DPAGE($F6)246
DPAGE($F7)247
DPAGE($F0)240
DPAGE($F8)248
DPAGE($F9)249
DPAGE($FA)250
DPAGE($FB)251
DPAGE($FC)252
DPAGE($FD)253
DPAGE($FE)254
DPAGE($FF)255
PPAGE($FC)252
PPAGE($FD)253
PPAGE($FE)254
PPAGE($FF)255
.
.
....
.
.
.
256 pages of 1 Kbyte each viewed
256 pages of 4 Kbytes each viewed through D-window (1 M)
256 pages of 16 Kbytes each viewed through P-window (4 M)00 0000
30 0000
3C 0000
3E FFFF3F 0000
3F 7FFF3F 8000
3F BFFF3F C000
3F FFFFFFFF
0000
040007FF
1FFF2000
3FFF4000
5FFF6000
6FFF7000
7FFF8000
DFFFE000
BFFFC000
9FFFA000
D window
P window
E window(EWDIR = 1)
E window(EWDIR = 0)
CPU_ADDR EXT_ADDR
through E-window (256 K)
MOTOROLA CPU12 Reference Guide (for HCS12 and original M68HC12) 27
For More Information On This Product, Go to: www.freescale.com
CPU12RG/D
F
ree
sca
le S
em
ico
nd
uc
tor,
I
Freescale Semiconductor, Inc.n
c..
.
Tab
le 6
. CP
U12
Op
cod
e M
ap (
Sh
eet
1 o
f 2)
00†
5B
GN
DIH
1
101
AN
DC
CIM
2
203
BR
AR
L2
303
PU
LXIH
1
401
NE
GA
IH1
501
NE
GB
IH1
603-
6N
EG
ID2-
4
70
4N
EG
EX
3
801
SU
BA
IM2
903
SU
BA
DI
2
A0
3-6
SU
BA
ID2-
4
B0
3S
UB
AE
X3
C0
1S
UB
BIM
2
D0
3S
UB
BD
I2
E0
3-6
SU
BB
ID2-
4
F0
3S
UB
BE
X3
015
ME
MIH
1
1111
ED
IVIH
1
211
BR
NR
L2
313
PU
LYIH
1
411
CO
MA
IH1
511
CO
MB
IH1
613-
6C
OM
ID2-
4
71
4C
OM
EX
3
811
CM
PA
IM2
913
CM
PA
DI
2
A1
3-6
CM
PA
ID2-
4
B1
3C
MPA
EX
3
C1
1C
MP
BIM
2
D1
3C
MP
BD
I2
E1
3-6
CM
PB
ID2-
4
F1
3C
MP
BE
X3
021
INY
IH1
12‡1
MU
LIH
1
223/
1B
HI
RL
2
323
PU
LAIH
1
421
INC
AIH
1
521
INC
BIH
1
623-
6IN
CID
2-4
72
4IN
CE
X3
821
SB
CA
IM2
923
SB
CA
DI
2
A2
3-6
SB
CA
ID2-
4
B2
3S
BC
AE
X3
C2
1S
BC
BIM
2
D2
3S
BC
BD
I2
E2
3-6
SB
CB
ID2-
4
F2
3S
BC
BE
X3
031
DE
YIH
1
133
EM
UL
IH1
233/
1B
LSR
L2
333
PU
LBIH
1
431
DE
CA
IH1
531
DE
CB
IH1
633-
6D
EC
ID2-
4
73
4D
EC
EX
3
832
SU
BD
IM3
933
SU
BD
DI
2
A3
3-6
SU
BD
ID2-
4
B3
3S
UB
DE
X3
C3
2A
DD
DIM
3
D3
3A
DD
DD
I2
E3
3-6
AD
DD
ID2-
4
F3
3A
DD
DE
X3
043
loop
*
RL
3
141
OR
CC
IM2
243/
1B
CC
RL
2
342
PS
HX
IH1
441
LSR
AIH
1
541
LSR
BIH
1
643-
6LS
RID
2-4
74
4LS
RE
X3
841
AN
DA
IM2
943
AN
DA
DI
2
A4
3-6
AN
DA
ID2-
4
B4
3A
ND
AE
X3
C4
1A
ND
BIM
2
D4
3A
ND
BD
I2
E4
3-6
AN
DB
ID2-
4
F4
3A
ND
BE
X3
053-
6JM
PID
2-4
154-
7JS
RID
2-4
253/
1B
CS
RL
2
352
PS
HY
IH1
451
RO
LAIH
1
551
RO
LBIH
1
653-
6R
OL
ID2-
4
75
4R
OL
EX
3
851
BIT
AIM
2
953
BIT
AD
I2
A5
3-6
BIT
AID
2-4
B5
3B
ITA
EX
3
C5
1B
ITB
IM2
D5
3B
ITB
DI
2
E5
3-6
BIT
BID
2-4
F5
3B
ITB
EX
306
3JM
PE
X3
164
JSR
EX
3
263/
1B
NE
RL
2
362
PS
HA
IH1
461
RO
RA
IH1
561
RO
RB
IH1
663-
6R
OR
ID2-
4
76
4R
OR
EX
3
861
LDA
AIM
2
963
LDA
AD
I2
A6
3-6
LDA
AID
2-4
B6
3LD
AA
EX
3
C6
1LD
AB
IM2
D6
3LD
AB
DI
2
E6
3-6
LDA
BID
2-4
F6
3LD
AB
EX
307
4B
SR
RL
2
174
JSR
DI
2
273/
1B
EQ
RL
2
372
PS
HB
IH1
471
AS
RA
IH1
571
AS
RB
IH1
673-
6A
SR
ID2-
4
77
4A
SR
EX
3
871
CLR
AIH
1
971
TS
TAIH
1
A7
1N
OP
IH1
B7
1T
FR
/EX
GIH
2
C7
1C
LRB
IH1
D7
1T
ST
BIH
1
E7
3-6
TS
TID
2-4
F7
3T
ST
EX
308
1IN
XIH
1
18-
page
2-
-
283/
1B
VC
RL
2
383
PU
LCIH
1
481
AS
LAIH
1
581
AS
LBIH
1
683-
6A
SL
ID2-
4
78
4A
SL
EX
3
881
EO
RA
IM2
983
EO
RA
DI
2
A8
3-6
EO
RA
ID2-
4
B8
3E
OR
AE
X3
C8
1E
OR
BIM
2
D8
3E
OR
BD
I2
E8
3-6
EO
RB
ID2-
4
F8
3E
OR
BE
X3
091
DE
XIH
1
192
LEA
YID
2-4
293/
1B
VS
RL
2
392
PS
HC
IH1
491
LSR
DIH
1
591
AS
LDIH
1
69‡2
-4C
LRID
2-4
79
3C
LRE
X3
891
AD
CA
IM2
993
AD
CA
DI
2
A9
3-6
AD
CA
ID2-
4
B9
3A
DC
AE
X3
C9
1A
DC
BIM
2
D9
3A
DC
BD
I2
E9
3-6
AD
CB
ID2-
4
F9
3A
DC
BE
X3
0A‡7
RT
CIH
1
1A2
LEA
XID
2-4
2A3/
1B
PL
RL
2
3A3
PU
LDIH
1
4A‡7
CA
LLE
X4
5A2
STA
AD
I2
6A‡2
-4S
TAA
ID2-
4
7A
3S
TAA
EX
3
8A1
OR
AA
IM2
9A3
OR
AA
DI
2
AA
3-6
OR
AA
ID2-
4
BA
3O
RA
AE
X3
CA
1O
RA
BIM
2
DA
3O
RA
BD
I2
EA
3-6
OR
AB
ID2-
4
FA
3O
RA
BE
X3
0B†
8R
TI
IH1
1B2
LEA
SID
2-4
2B3/
1B
MI
RL
2
3B2
PS
HD
IH1
4B‡7
-10
CA
LLID
2-5
5B2
STA
BD
I2
6B‡2
-4S
TAB
ID2-
4
7B
3S
TAB
EX
3
8B1
AD
DA
IM2
9B3
AD
DA
DI
2
AB
3-6
AD
DA
ID2-
4
BB
3A
DD
AE
X3
CB
1A
DD
BIM
2
DB
3A
DD
BD
I2
EB
3-6
AD
DB
ID2-
4
FB
3A
DD
BE
X3
0C4-
6B
SE
TID
3-5
1C4
BS
ET
EX
4
2C3/
1B
GE
RL
2
3C‡+
5w
avr
SP
1
4C4
BS
ET
DI
3
5C2
ST
DD
I2
6C‡2
-4S
TD
ID2-
4
7C
3S
TD
EX
3
8C2
CP
DIM
3
9C3
CP
DD
I2
AC
3-6
CP
DID
2-4
BC
3C
PD
EX
3
CC
2LD
DIM
3
DC
3LD
DD
I2
EC
3-6
LDD
ID2-
4
FC
3LD
DE
X3
0D4-
6B
CLR
ID3-
5
1D4
BC
LRE
X4
2D3/
1B
LTR
L2
3D5
RT
SIH
1
4D4
BC
LRD
I3
5D2
ST
YD
I2
6D‡2
-4S
TY
ID2-
4
7D
3S
TY
EX
3
8D2
CP
YIM
3
9D3
CP
YD
I2
AD
3-6
CP
YID
2-4
BD
3C
PY
EX
3
CD
2LD
YIM
3
DD
3LD
YD
I2
ED
3-6
LDY
ID2-
4
FD
3LD
YE
X3
0E‡4
-6B
RS
ET
ID4-
6
1E5
BR
SE
TE
X5
2E3/
1B
GT
RL
2
3E‡†
7W
AI
IH1
4E4
BR
SE
TD
I4
5E2
ST
XD
I2
6E‡2
-4S
TX
ID2-
4
7E
3S
TX
EX
3
8E2
CP
XIM
3
9E3
CP
XD
I2
AE
3-6
CP
XID
2-4
BE
3C
PX
EX
3
CE
2LD
XIM
3
DE
3LD
XD
I2
EE
3-6
LDX
ID2-
4
FE
3LD
XE
X3
0F‡4
-6B
RC
LRID
4-6
1F5
BR
CLR
EX
5
2F3/
1B
LER
L2
3F9
SW
IIH
1
4F4
BR
CLR
DI
4
5F2
ST
SD
I2
6F‡2
-4S
TS
ID2-
4
7F
3S
TS
EX
3
8F2
CP
SIM
3
9F3
CP
SD
I2
AF
3-6
CP
SID
2-4
BF
3C
PS
EX
3
CF
2LD
SIM
3
DF
3LD
SD
I2
EF
3-6
LDS
ID2-
4
FF
3LD
SE
X3
005
BG
ND
IHI
Num
ber
of H
CS
12 c
ycle
s (‡
indi
cate
s H
C12
diff
eren
t)K
ey t
o T
able
6:
Num
ber
of b
ytes
Opc
ode
Mne
mon
icA
ddre
ss M
ode
28 CPU12 Reference Guide (for HCS12 and original M68HC12) MOTOROLA
For More Information On This Product, Go to: www.freescale.com
CPU12RG/D
F
ree
sca
le S
em
ico
nd
uc
tor,
I
Freescale Semiconductor, Inc.n
c..
.
* T
he o
pcod
e $0
4 (o
n sh
eet 1
of 2
) co
rres
pond
s to
one
of t
he lo
op p
rimiti
ve in
stru
ctio
ns D
BE
Q, D
BN
E, I
BE
Q, I
BN
E, T
BE
Q, o
r T
BN
E.
† R
efer
to in
stru
ctio
n su
mm
ary
for
mor
e in
form
atio
n.‡
Ref
er to
inst
ruct
ion
sum
mar
y fo
r di
ffere
nt H
C12
cyc
le c
ount
.
004
MO
VW
IM-I
D5
1012
IDIV
IH2
204
LBR
AR
L4
3010
TR
AP
IH2
4010
TR
AP
IH2
5010
TR
AP
IH2
6010
TR
AP
IH2
70
10T
RA
PIH
2
801
0T
RA
PIH
2
9010
TR
AP
IH2
A0
10T
RA
PIH
2
B0
10T
RA
PIH
2
C0
10T
RA
PIH
2
D0
10
TR
AP
IH2
E0
10T
RA
PIH
2
F0
10T
RA
PIH
201
5M
OV
WE
X-I
D5
1112
FD
IVIH
2
213
LBR
NR
L4
3110
TR
AP
IH2
4110
TR
AP
IH2
5110
TR
AP
IH2
6110
TR
AP
IH2
71
10T
RA
PIH
2
811
0T
RA
PIH
2
9110
TR
AP
IH2
A1
10T
RA
PIH
2
B1
10T
RA
PIH
2
C1
10T
RA
PIH
2
D1
10
TR
AP
IH2
E1
10T
RA
PIH
2
F1
10T
RA
PIH
202
5M
OV
WID
-ID
4
1213
EM
AC
SS
P4
224/
3LB
HI
RL
4
3210
TR
AP
IH2
4210
TR
AP
IH2
5210
TR
AP
IH2
6210
TR
AP
IH2
72
10T
RA
PIH
2
821
0T
RA
PIH
2
9210
TR
AP
IH2
A2
10T
RA
PIH
2
B2
10T
RA
PIH
2
C2
10T
RA
PIH
2
D2
10
TR
AP
IH2
E2
10T
RA
PIH
2
F2
10T
RA
PIH
203
5M
OV
WIM
-EX
6
133
EM
ULS
IH2
234/
3LB
LSR
L4
3310
TR
AP
IH2
4310
TR
AP
IH2
5310
TR
AP
IH2
6310
TR
AP
IH2
73
10T
RA
PIH
2
831
0T
RA
PIH
2
9310
TR
AP
IH2
A3
10T
RA
PIH
2
B3
10T
RA
PIH
2
C3
10T
RA
PIH
2
D3
10
TR
AP
IH2
E3
10T
RA
PIH
2
F3
10T
RA
PIH
204
6M
OV
WE
X-E
X6
1412
ED
IVS
IH2
244/
3LB
CC
RL
4
3410
TR
AP
IH2
4410
TR
AP
IH2
5410
TR
AP
IH2
6410
TR
AP
IH2
74
10T
RA
PIH
2
841
0T
RA
PIH
2
9410
TR
AP
IH2
A4
10T
RA
PIH
2
B4
10T
RA
PIH
2
C4
10T
RA
PIH
2
D4
10
TR
AP
IH2
E4
10T
RA
PIH
2
F4
10T
RA
PIH
205
5M
OV
WID
-EX
5
1512
IDIV
SIH
2
254/
3LB
CS
RL
4
3510
TR
AP
IH2
4510
TR
AP
IH2
5510
TR
AP
IH2
6510
TR
AP
IH2
75
10T
RA
PIH
2
851
0T
RA
PIH
2
9510
TR
AP
IH2
A5
10T
RA
PIH
2
B5
10T
RA
PIH
2
C5
10T
RA
PIH
2
D5
10
TR
AP
IH2
E5
10T
RA
PIH
2
F5
10T
RA
PIH
206
2A
BA
IH2
162
SB
AIH
2
264/
3LB
NE
RL
4
3610
TR
AP
IH2
4610
TR
AP
IH2
5610
TR
AP
IH2
6610
TR
AP
IH2
76
10T
RA
PIH
2
861
0T
RA
PIH
2
9610
TR
AP
IH2
A6
10T
RA
PIH
2
B6
10T
RA
PIH
2
C6
10T
RA
PIH
2
D6
10
TR
AP
IH2
E6
10T
RA
PIH
2
F6
10T
RA
PIH
207
3D
AA
IH2
172
CB
AIH
2
274/
3LB
EQ
RL
4
3710
TR
AP
IH2
4710
TR
AP
IH2
5710
TR
AP
IH2
6710
TR
AP
IH2
77
10T
RA
PIH
2
871
0T
RA
PIH
2
9710
TR
AP
IH2
A7
10T
RA
PIH
2
B7
10T
RA
PIH
2
C7
10T
RA
PIH
2
D7
10
TR
AP
IH2
E7
10T
RA
PIH
2
F7
10T
RA
PIH
208
4M
OV
BIM
-ID
4
184-
7M
AX
AID
3-5
284/
3LB
VC
RL
4
3810
TR
AP
IH2
4810
TR
AP
IH2
5810
TR
AP
IH2
6810
TR
AP
IH2
78
10T
RA
PIH
2
881
0T
RA
PIH
2
9810
TR
AP
IH2
A8
10T
RA
PIH
2
B8
10T
RA
PIH
2
C8
10T
RA
PIH
2
D8
10
TR
AP
IH2
E8
10T
RA
PIH
2
F8
10T
RA
PIH
209
5M
OV
BE
X-I
D5
194-
7M
INA
ID3-
5
294/
3LB
VS
RL
4
3910
TR
AP
IH2
4910
TR
AP
IH2
5910
TR
AP
IH2
6910
TR
AP
IH2
79
10T
RA
PIH
2
891
0T
RA
PIH
2
9910
TR
AP
IH2
A9
10T
RA
PIH
2
B9
10T
RA
PIH
2
C9
10T
RA
PIH
2
D9
10
TR
AP
IH2
E9
10T
RA
PIH
2
F9
10T
RA
PIH
20A
5M
OV
BID
-ID
4
1A4-
7E
MA
XD
ID3-
5
2A4/
3LB
PL
RL
4
3A†
3nR
EV
SP
2
4A10
TR
AP
IH2
5A10
TR
AP
IH2
6A10
TR
AP
IH2
7A
10T
RA
PIH
2
8A1
0T
RA
PIH
2
9A10
TR
AP
IH2
AA
10T
RA
PIH
2
BA
10T
RA
PIH
2
CA
10T
RA
PIH
2
DA
10
TR
AP
IH2
EA
10T
RA
PIH
2
FA
10T
RA
PIH
20B
4M
OV
BIM
-EX
5
1B4-
7E
MIN
DID
3-5
2B4/
3LB
MI
RL
4
3B†5
n/3n
RE
VW
SP
2
4B10
TR
AP
IH2
5B10
TR
AP
IH2
6B10
TR
AP
IH2
7B
10T
RA
PIH
2
8B1
0T
RA
PIH
2
9B10
TR
AP
IH2
AB
10T
RA
PIH
2
BB
10T
RA
PIH
2
CB
10T
RA
PIH
2
DB
10
TR
AP
IH2
EB
10T
RA
PIH
2
FB
10T
RA
PIH
20C
6M
OV
BE
X-E
X6
1C4-
7M
AX
MID
3-5
2C4/
3LB
GE
RL
4
3C‡†
7BW
AVS
P2
4C10
TR
AP
IH2
5C10
TR
AP
IH2
6C10
TR
AP
IH2
7C
10T
RA
PIH
2
8C1
0T
RA
PIH
2
9C10
TR
AP
IH2
AC
10T
RA
PIH
2
BC
10T
RA
PIH
2
CC
10T
RA
PIH
2
DC
10
TR
AP
IH2
EC
10T
RA
PIH
2
FC
10T
RA
PIH
20D
5M
OV
BID
-EX
5
1D
4-7
MIN
MID
3-5
2D4/
3LB
LTR
L4
3D‡6
TB
LID
3
4D10
TR
AP
IH2
5D10
TR
AP
IH2
6D10
TR
AP
IH2
7D
10T
RA
PIH
2
8D1
0T
RA
PIH
2
9D10
TR
AP
IH2
AD
10T
RA
PIH
2
BD
10T
RA
PIH
2
CD
10T
RA
PIH
2
DD
10
TR
AP
IH2
ED
10T
RA
PIH
2
FD
10T
RA
PIH
20E
2TA
BIH
2
1E4-
7E
MA
XM
ID3-
5
2E4/
3LB
GT
RL
4
3E‡8
ST
OP
IH2
4E10
TR
AP
IH2
5E10
TR
AP
IH2
6E10
TR
AP
IH2
7E
10T
RA
PIH
2
8E1
0T
RA
PIH
2
9E10
TR
AP
IH2
AE
10T
RA
PIH
2
BE
10T
RA
PIH
2
CE
10T
RA
PIH
2
DE
10
TR
AP
IH2
EE
10T
RA
PIH
2
FE
10T
RA
PIH
20F
2T
BA
IH2
1F4-
7E
MIN
MID
3-5
2F4/
3LB
LER
L4
3F10
ET
BL
ID3
4F10
TR
AP
IH2
5F10
TR
AP
IH2
6F10
TR
AP
IH2
7F
10T
RA
PIH
2
8F1
0T
RA
PIH
2
9F10
TR
AP
IH2
AF
10T
RA
PIH
2
BF
10T
RA
PIH
2
CF
10T
RA
PIH
2
DF
10
TR
AP
IH2
EF
10T
RA
PIH
2
FF
10T
RA
PIH
2
Tab
le 6
. CP
U12
Op
cod
e M
ap (
Sh
eet
2 o
f 2)
MOTOROLA CPU12 Reference Guide (for HCS12 and original M68HC12) 29
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Table 7. Hexadecimal to ASCII Conversion
Hex ASCII Hex ASCII Hex ASCII Hex ASCII
$00 NUL $20 SP space $40 @ $60 ‘ grave
$01 SOH $21 ! $41 A $61 a
$02 STX $22 “ quote $42 B $62 b
$03 ETX $23 # $43 C $63 c
$04 EOT $24 $ $44 D $64 d
$05 ENQ $25 % $45 E $65 e
$06 ACK $26 & $46 F $66 f
$07 BEL beep $27 ‘ apost. $47 G $67 g
$08BS back
sp$28 ( $48 H $68 h
$09 HT tab $29 ) $49 I $69 i
$0ALF
linefeed$2A * $4A J $6A j
$0B VT $2B + $4B K $6B k
$0C FF $2C , comma $4C L $6C l
$0D CR return $2D - dash $4D M $6D m
$0E SO $2E . period $4E N $6E n
$0F SI $2F / $4F O $6F o
$10 DLE $30 0 $50 P $70 p
$11 DC1 $31 1 $51 Q $71 q
$12 DC2 $32 2 $52 R $72 r
$13 DC3 $33 3 $53 S $73 s
$14 DC4 $34 4 $54 T $74 t
$15 NAK $35 5 $55 U $75 u
$16 SYN $36 6 $56 V $76 v
$17 ETB $37 7 $57 W $77 w
$18 CAN $38 8 $58 X $78 x
$19 EM $39 9 $59 Y $79 y
$1A SUB $3A : $5A Z $7A z
$1B ESCAPE $3B ; $5B [ $7B {
$1C FS $3C < $5C \ $7C |
$1D GS $3D = $5D ] $7D }
$1E RS $3E > $5E ^ $7E ~
$1F US $3F ? $5F _ under $7FDEL
delete
30 CPU12 Reference Guide (for HCS12 and original M68HC12) MOTOROLA
For More Information On This Product, Go to: www.freescale.com
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Hexadecimal to Decimal Conversion
To convert a hexadecimal number (up to four hexadecimal digits) to decimal, look up the decimal equivalent of each hexadecimal digit in Table 8. The decimal equivalent of the original hexadecimal number is the sum of the weights found in the table for all hexadecimal digits.
Decimal to Hexadecimal Conversion
To convert a decimal number (up to 65,53510) to hexadecimal, find the largest decimal number in Table 8 that is less than or equal to the number you are converting. The corresponding hexadecimal digit is the most significant hexadecimal digit of the result. Subtract the decimal number found from the original decimal number to get the remaining decimal value. Repeat the procedure using the remaining decimal value for each subsequent hexadecimal digit.
Table 8. Hexadecimal to/from Decimal Conversion15 Bit 8 7 Bit 0
MOTOROLA CPU12 Reference Guide (for HCS12 and original M68HC12) 31
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