Frank Vahid, UC Riverside 1 Recent Results at UCR with Configurable Cache and Hw/Sw Partitioning Frank Vahid Associate Professor Dept. of Computer Science and Engineering University of California, Riverside Also with the Center for Embedded Computer Systems at UC Irvine http://www.cs.ucr.edu/~vahid
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Frank Vahid, UC Riverside 1 Recent Results at UCR with Configurable Cache and Hw/Sw Partitioning Frank Vahid Associate Professor Dept. of Computer Science.
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Frank Vahid, UC Riverside
1
Recent Results at UCR with Configurable Cache and Hw/Sw Partitioning
Frank VahidAssociate Professor
Dept. of Computer Science and EngineeringUniversity of California, Riverside
Also with the Center for Embedded Computer Systems at UC Irvine
http://www.cs.ucr.edu/~vahid
Frank Vahid, UC Riverside 2
Trend Towards Pre-Fabricated Platforms: ASSPs
ASSP: application specific standard product
Domain-specific pre-fabricated IC
e.g., digital camera IC ASIC: application specific IC ASSP revenue > ASIC ASSP design starts > ASIC
Unique IC design Ignores quantity of same IC
ASIC design starts decreasing Due to strong benefits of
using pre-fabricated devices
Sourc
e:
Gart
ner/
Data
quest
Septe
mber’
01
Frank Vahid, UC Riverside 3
Will High End ICs Still be Made?
YES The point is that
mainstream designers likely won’t be making them
Very high volume or very high cost products
Platforms are one such product – high volume
Need to be highly configurable to adapt to different applications and constraints
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10
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1 2 3 4
Volume
Cost
per
IC 1990
20002010Mainstream
design
Becoming out of reach of
mainstream designers
Frank Vahid, UC Riverside 4
UCR Focus
Configurable Cache Hardware/Software Partitioning
Frank Vahid, UC Riverside 5
UCR Focus
Configurable Cache Hardware/Software Partitioning
Frank Vahid, UC Riverside 6
Configurable Cache: Why
uP
L1 cache
DSP
JPEG dcd
Periph-erals
FPGA
Pre-fabricated Platform
(A pre-designed system-level architecture)
IC ARM920T: Caches consume
half of total power (Segars 01)
M*CORE: Unified cache consumes half of total power (Lee/Moyer/Arends 99)
L1 cache
Frank Vahid, UC Riverside 7
Best Cache for Embedded Systems?
Not clear Huge variety among popular embedded processors
What’s the best… Associativity, Line size, Total size?
Processor Size As. Line Size As. Line Processor Size As. Line Size As. Line
Instruct. Cache Data Cache Instruct. Cache Data Cache
D1100
11 0 000
0000
Frank Vahid, UC Riverside 14
Our Solution: Way Concatenatable Cache
Can be configured as 4, 2, or 1 way Ways can be
concatenated
D11xx C10x
11 0 000
This bit selects the way
0000
Frank Vahid, UC Riverside 15
Configurable Cache Design: Way Concatenation (4, 2 or 1 way)
index
c1 c3c0 c2
a11
a12
reg1
reg0
sense ampscolumn mux
tag part
tag address
mux driver
c1
line offset
data output
critical path
c0
c2
c0 c1
6x64
6x64
c3c2
6x64
6x64
c3
6x64
6x64
a31 tag address a13 a12 a11 a10 index a5 a4 line offset a0
Configuration circuit
data array
bitline
Small area and performance overhead
Frank Vahid, UC Riverside 16
Way Concatenate Experiments
Experiment Motorola PowerStone benchmark g3fax Considering dynamic power only
L1 access energy, CPU stall energy, memory access energy Way concatenate outperforms 4 way and direct map.
Just as good as way shutdown
0.0000
0.0005
0.0010
0.0015
0.0020
0.0025
0.0030
0.0035
0.0040
Configuration
En
erg
y(n
J)
Frank Vahid, UC Riverside 17
Way Concatenate Experiments
Considered 23 programs (Powerstone, MediaBench, and Spec2000) Dynamic power only (L1 access energy, CPU stall energy, memory access energy)
Way concatenate Better than way shutdown (due to less performance penalty) Saves over conventional 4-way Also avoids big penalties of 1-way on some programs
100% = 4-way conventional cache 111%113% 289%
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
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epic
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g721 ar
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er vpr
Ave
rage
Benchmarks
Ene
rgy
(no
rmal
ize
d)
CnvI1D1
cnct
shut
both
Frank Vahid, UC Riverside 18
Way Concatenate Experiments
Best configuration varies Need to tune
configuration to a given program
Example Best Example Bestpadpcm I8KD8KI1D1 ucbqsort I4KD4KI1D1
crc I4KD4KI1D1 v42 I8KD8KI1D1
auto2 I8KD4KI1D1 adpcm I2KD8KI1D1
bcnt I8KD2KI1D1 epic I8KD8KI1D1
bilv I4KD4KI1D1 jpeg I8KD8KI4D2
binary I8KD2KI1D1 mpeg2 I8KD8KI1D2
blit I2KD8KI1D1 g721 I8KD8KI2D1
brev I8KD4KI1D2 art I4KD8KI1D1
g3fax I4KD4KI1D1 mcf I8KD8KI1D1
fir I8KD2KI1D1 parser I8KD8K41D1
pjepg I4KD8KI1D1 vpr I8KD8KI2D1
pegw it I8KD8KI1D1
Frank Vahid, UC Riverside 19
Normalized Execution Times
122% 245% 121%
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
110%
120%
padp
cm crc
auto
2
bcnt
bliv
bina
ry blit
brev
g3fa
x fir
pjep
g
ucbq
sort
v42
adpc
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epic
jpeg
mpe
g2
pegw
it
g721 ar
t
mcf
pars
er vpr
Ave
rage
CnvI1D1
cncf
shut
both
Way shutdown suffers performance penalty As does direct mapped
Way concatenate has almost no performance penalty Though 3% longer critical path than conventional 4-
way
Frank Vahid, UC Riverside 20
Way Shutdown for Static Power Savings
Albonesi and Motorola used logic to gate clock Reduced dynamic power, but not static (leakage) Way concatenate clearly superior for reducing dynamic
pwr Shutting down ways still useful to save static power
But we’ll use another method (Agarwal DRG-cache)
Gnd
Vdd bitlinebitline
Gated-VddControl
SRAM cell
Frank Vahid, UC Riverside 21
Way Concatenate Plus Way Shutdown
We set static power = 30% of dynamic power Way shutdown now preferred in many
examples But way concatenate still very helpful
114%268%116%
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
padp
cm crc
auto
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bcnt
bilv
bina
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brev
g3fa
x fir
pjep
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ucbq
sort
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epic
jpeg
mpe
g2
pegw
it
g721 ar
t
mcf
pars
er vpr
Ave
rage
Benchmarks
En
erg
y (n
orm
aliz
ed
)
CnvI1D1cnctshutboth
Frank Vahid, UC Riverside 22
Configurable Line Size Too
Best line size also differs per example Our cache can be configured for line of 16, 32 or 64 bytes 64 is usually best; but 16 is much better in a couple cases
100% = 4-way conventional cache
127% 127%122%
126% 129%
119%
1.44E+00 147%230% 133%144%125%
0%
20%
40%
60%
80%
100%
120%
padp
cm crc
auto
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bcnt
bilv
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brev
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epic
g721
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it
mpe
g
jpeg
csb16 csb32 cbs64 cnv4w32 cnv1w32
csb: concatenate plus shutdown cache
Frank Vahid, UC Riverside 23
Configurable Cache
A configurable cache with way concatenation, way shutdown, and variable line size, can save a lot of energy
Well-suited for configurable devices like Triscend’s
Frank Vahid, UC Riverside 24
UCR Focus
Configurable Cache Hardware/Software Partitioning
Frank Vahid, UC Riverside 25
Using On-Chip FPGA to Reduce Sw Energy
Hennessey/Patterson: “The best way to save power is to have less
hardware” (pg 392) Actually, best way is to have less ACTIVE hw
Paradoxically, MORE hw can actually REDUCE power, as long as overall activity is reduced
How?
Frank Vahid, UC Riverside 26
Using On-Chip FPGA to Reduce Sw Energy
uP
L1 cache
DSP
JPEG dcd
Periph-erals
FPGA
Pre-fabricated Platform
Move critical sw loops to FPGA
Loop executes in 1/10th the time
Use this time to power down the system longer during task period
Alternatively, slow down the microprocessor using voltage scaling
ICFPGA
uP
idleuP active
idleuP FPGA
Task period
Frank Vahid, UC Riverside 27
The 90-10 rule (or 80-20 rule)
Most software time is spent in a few small loops
e.g., MediaBench and NetBench benchmarks
Known as the 90-10 rule
10% of the code accounts for 90% of the execution time
Use physical platform to aid search of configuration space
Configure cache, hw/sw partition
Configure, execute, and measure
Goal: Define best cooperation between desktop CAD and platform
NSF grant 2002-2005 (with N. Dutt at UC Irvine)
Frank Vahid, UC Riverside 35
Other Research Directions: Dynamic Hw/Sw Partitioning
My favorite Add component on-chip:
Detects most frequent sw loops Decompiles a loop Performs compiler
optimizations Synthesizes to a netlist Places and routes the netlist
onto FPGA Updates sw to call FPGA
Self-improving IC Can be invisible to designer Appears as efficient processor Can also dynamically tune the
cache configuration
Config. Logic
MemProcessor
DMA
D$
I$
Profiler
Proc.
Mem
Frank Vahid, UC Riverside 36
Current Researchers Working in Embedded Systems at UCR
Prof. Frank Vahid 5 Ph.D. students, 2 M.S.
Prof. Walid Najjar 3 Ph.D. students, 1 M.S., working on hw/sw partitioning, and on
compiling C to FPGAs Prof. Tom Payne
1 Ph.D. student, working on compiling C to FPGAs Prof. Jun Yang (new hire)
Working on low power architectures (frequent value detection) Prof. Harry Hsieh
2 Ph.D. students, working on formal verification of system models
Prof. Sheldon Tan (new hire) 1 Ph.D, working on physical design, and analog synthesis
Frank Vahid, UC Riverside 37
Conclusions
Highly configurable platforms have a bright future
Cost equations just don’t justify ASIC production as much as before
Triscend parts are well situated; close collaboration desired Configurable cache improves memory energy
Tuning to a particular program is CRUCIAL to low energy Way concatenation is effective at reducing dynamic power Way shutdown saves static power Variable line size reduces traffic All must be tuned to a particular program
Configurable logic improves software energy Without requiring excessive amounts of hardware