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Microelectronics and Solid State Electronics 2013, 2(2A): 1-15
DOI: 10.5923/s.msse.201302.01
Device/Circuit/Architectural Techniques for Ultra-low
Power FPGA Design
Pooran Singh , Santosh Kumar Vishvakarma*
Nanoscale Devices and VLSI/ULSI Circuit & System Design Lab School of Engineering, Electrical Engineering Discipline, Indian Institute of Technology (IIT), Indore, MP, 145341, India
Abstract Field Programmable Gate Arrays (FPGAs) are widely used for implementation of dig ital system design due to
their flexibility, low time-to-market, growing density and speed. But the Power consumption, especially leakage and
dynamic power has become a major concern for semiconductor industries. FPGAs are less power-efficient than custom
ASICs, due to the overhead required to provide programmability. Despite this, power has been largely ignored by the
FPGA research community earlier, whose prime focus centred on improving FPGA speed and area -efficiency. But
nowadays research extensively focuses on power too. Hence this paper demonstrates so me of the most utilized and efficient
techniques for Power optimizat ion and reduction in FPGAs currently. After reviewing latest research work on power
reduction in FPGA we examined that using Dual VT and fine-grained VDD static power reduces upto 64% and 95%
respectively. Clock Gat ing reduces the power consumption by the factor 50% and also by using latest novel devices like
Tunnel FET power can be reduced much lower than present .
Keywords FPGA, Power Reduction, CAD, SRAM, Non-Classical MOS Devices
1. Introduction
Field-Programmable Gate Arrays (FPGAs) are integrated
circuits that can be programmed to implement any digital
circuit. The main d ifference between FPGAs and
conventional fixed logic implementations, such as
Application Specific Integrated Circuits (ASICs), is that the
designer/customer programs the FPGA on-site[1-3]. For
fixed logic implementations, the designer must create a
layout mask and send it to a foundry to be fabricated.
Creat ing a layout is labour-intensive and requires expensive
CAD tools and experienced engineers. Programmable
switches controlled by configuration memory occupy a
large area in the FPGA and add a significant amount of
parasitic capacitance and resistance to the logic and routing
resources. Because of this, FPGAs are approx 3 times
slower, 20 times larger, and 12 times less power efficient
compared to ASICs[4].
Many studies have focused on reducing the speed and
area overhead of FPGAs. Important advancements include
cluster-based logic blocks[5], which improve speed by
grouping the basic logic elements of the FPGA into clusters
with faster local interconnect; embedded memories [6],
which reduce the speed and area overhead for applications
further design FPGA interconnects fabrics for fine g rained
VDD programmability with minimal increase of the number
of configuration static-random-access-memory cells. W ith a
simple yet pract ical computer-aided design flow to leverage
the field-programmable dual-VDD logic and interconnect
fabrics, its carry out a highly quantitative study using placed
and routed benchmark circuits, and delay, power, and area
models obtained from detailed circuit designs. Compared to
single-VDD FPGAs with the VDD level suggested by the
ITRS for 100nm technology, field-programmable dual-VDD
FPGA reduce the total power by 47.61% and the
energy-delay product by 27.36%.
4.3. Architectural Level Power Reduction Techniques
At architectural level power reduction we have several
techniques which will reduce the power in data path, clock
gating, and power gating. Some of those power reduction
techniques are discussed in this section which will
overcome both static and dynamic power.
4.3.1. Fine g rained-VDD
Low power FPGA architecture[60] is generated with the
use of fine-grained VDD control scheme called
micro -VDD-hopping, 4 CLB’s are grouped into one block
where VDD is shared as shown in Fig. 19. In the
10 Pooran Singh et al.: Device/Circuit/Architectural Techniques for Ultra-low Power FPGA Design
micro -VDD-hopping scheme, VDD of each block is varied
between the higher VDD (VDDH) and the lower VDD (VDDL)
spatially and temporally to achieve lower power, while
keeping performance un-degraded. Simulation using 90nm
CMOS technology shows that a leakage power reduction of
95% can be achieved, when this method is used.
Figure 19. Schematic of the CLB, four BLE's are clustered into one
CLB[60]
4.3.2. Leakage Reduction in FPGA Routing Multip lexers
It is the technique for reducing the leakage current
which is based on the architecture such as multip lexer based
interconnect matrix of an FPGA which consumes most of
the static power. Leakage reduction in FPGA routing
multip lexers[61] investigates reducing leakage power in
unused FPGA routing multiplexers by controlling their
inputs at the deep submicron 22nm technology node.
HSPICE simulation using Berkeley Pred ictive Technology
Models (BPTM) on different sizes and topologies of routing
multip lexers shows that the minimum leakage vector at the
22nm technology node significantly varies from that at
65nm node. This is due to higher gate leakage and output
stage loading effects. The application of this vector results
in 20% more leakage power saving as compared to the
existing approaches. This technique saves significant
leakage power because most of the routing multiplexers are
unused in an FPGA.
4.3.3. Power Gat ing
Power gating is the technique which is used for leakage
power reduction, in which reg ions of the chip can be
powered down. It is the modification to the fabric of an
FPGA that enables dynamically-controlled power gating, in
which logic clusters can be selectively powered down at
run-time. For applications containing blocks with large id le
times, this could lead to significant leakage power savings.
There architecture utilizes the existing routing fabric and
unused input pins of logic clusters to route the power
control signals. The area and power tradeoffs have been
studied by varying the basic architecture parameters of an
FPGA, and by vary ing the size of the power gating reg ions.
It shows that the leakage energy savings using a model that
characterizes an application in terms of its structure and
behavior. Using the application model[62], they show that
up to 40% leakage energy reduction can be achieved using
the architecture for different application parameters.
Figure 20. Dynamic power gating architecture for a logic cluster and its
routing channels[62]
Fig.20 shows an example of the basic power gating
architecture. In this figure, a logic cluster has four input
pins, with the required four connection boxes, d istributed
uniformly on its four sides. Each of the connection boxes
can be used either to route an endpoint of a connection to
the corresponding input pin, or to route a power control
signal to the cluster. If a power control signal is to be routed,
then the corresponding input pin of the cluster is not used.
The outputs of the connection boxes are fed as inputs to the
power gating multip lexer. This mult iplexer selects the input
pin that will be used as the power control signal for the
cluster and the bounding routing channels; this signal is
labeled PG_ CNTL1 in the figure. PG_CNTL1 could drive
the gate of the sleep transistor to turn it off for low-leakage
mode, or to turn it on for normal circuit activ ity.
4.3.4. Low Power Programmable FPGA Routing Circu itry
Programmable FPGA routing[63] technique is for
reducing FPGA power consumption, it proposes a family of
new FPGA routing switch designs that are programmable to
operate in three different modes: high-speed, low-power, or
sleep. High-speed mode provides similar power and
performance to tradit ional FPGA routing switches. In
low-power mode, speed is curtailed in order to reduce
power consumption. Leakage is reduced by 28%-52% in
low-power versus high-speed mode, depending on the
particular switch design selected. Dynamic power is
reduced by 28%-31% in low-power mode. Leakage power
in sleep mode, which is suitable for unused routing switches,
is 61%-79% lower than in high-speed mode.
Fig. 21(a) shows a typical buffered FPGA routing
switch[63]. It consists of a multiplexer, a buffer and SRAM
con-figuration cells and a transistor-level view of a switch
with 4 inputs is shown in Fig. 21(b). NMOS transistor trees
are used to implement mult iplexers in FPGAs. Routing
switch inputs are tolerant to “weak-1” signals. That is,
logic-1 in-put signals need not be rail; it is acceptable if
they are lower than this. This is due to the level-restoring
Microelectronics and Solid State Electronics 2013, 2(2A): 1-15 11
buffers that are already deployed in FPGA routing
switches[see Fig. 21(b)]. It permits such switches to
produce “weak-1” signals. The main exceptions to this
observation are switches that drive inputs on logic blocks.
Based on these three observations,[63] p roposed a new
switch design shown in Fig. 22. The switch includes
n-MOS and p-MOS sleep transistors in parallel (MNX and
MPX).
Figure 21. Programmable low power routing switch (basic design)[63]
Figure 22. Switch multiplexer with programmable mode[63]
4.3.5. Clock Gat ing Power Reduction Technique
This is the most widely used technique for power
reduction. The principle is to stop the clock whenever the
device is not in use. Clock gating can be applied to
sub-blocks of the design as well as to the whole device.
However, correctly stopping the clock is very important.
Knowing that the gating logic adds a delay to the clock
signal, the effects on setup and hold times must be analyzed.
While using clock gating, on FPGAs in particu lar, the user
should take care of the p lacement of gating logic to
minimize delay in the clock network. For reduction of
dynamic power through clock gating approach first we
discuss about the clock gating architectures for FPGA
power reduction[64]. Clock gating is a power reduction
technique that has been used successfully in the custom
FPGA/ASIC domain. Clock and logic signal power are
saved by temporarily disabling the clock signal on registers
whose outputs do not affect circu it outputs. By considering
and evaluating FPGA clock network architectures with
built-in clock gating capability and describe a flexib le
placement algorithm that can operate with various gating
granularit ies (various sizes of device regions containing
clock loads that can be gated together). Results show that
depending on the clock gating architecture and the fraction
of time clock signals are enabled, clock power can be
reduced by over 50%, and results suggest that a fine
granularity gating architecture yields s ignificant power
benefits. The architectures are illustrated in Fig. 23. Fig.
23(a) shows the REGION architecture where enables are
present on switches entering a region. Fig. 23(b) shows the
more flexib le COLUMN architecture where enables are
also present on switches driving vertical spines in logic
block columns. Thus, consider a broad range of clock
gating architectures with various levels of granularity
within clock distribution frameworks that resemble those in
commercial ch ips.
Figure 23. Clock gating architectures; (a) Enables are present on switches
entering a region (b) enables are also present on switches driving vertical
spines in logic block columns[64]
4.3.6. Subthreshold FPGAs
Sub-threshold operation in CMOS has in recent years
become an accepted ultra-low power solution. However,
many low-volume applications cannot afford to produce
custom silicon. An FPGA, which delivers the flexib ility of
programming and yet consumes ultra-low power by way of
sub-threshold operation, can fill this gap.
Field-programmable gate arrays (FPGAs) are an attractive
option for low-power systems requiring flexib le computing
resources. However, the lowest power systems have yet to
adopt FPGAs. Subthreshold circuit operation offers the
opportunity to operate FPGAs at their min imum energy
point. Peter J. Grossmann et al.[65] measured data from an
12 Pooran Singh et al.: Device/Circuit/Architectural Techniques for Ultra-low Power FPGA Design
FPGA test chip fabricated in a 0.18-μm SOI process. They
showed that the test chip can function at supply voltages as
low as 0.26 V without an ext ra supply for write assists by
using latches for configuration bit storage instead of static
random access memory. Investigation of the minimum
energy point of the FPGA for a h igh-activity test pattern
shows that the min imum energy point of the FPGA can be
well below the threshold voltage of the transistors. While
Kyeong-Jae Lee et al.[66] demonstrated a subthreshold
FPGA system using monolithically integrated graphene
wires. The graphene wires replace double-length lines in the
interconnect fabric of a custom FPGA implemented in
0.18-μm CMOS. The four-layer graphene wires have lower
capacitance than the CMOS alumin ium wires, resulting in
up to 2.11× faster speeds and 1.54× lower interconnect
energy when driven by a low-swing voltage of 0.4 V. They
present’s us the first graphene-based system application and
experimentally demonstrates the potential of using low
capacitance graphene wires for ultralow power electronics.
Figure 24. Overview of FPGA test chip. Graphene wires are integrated on
top of the CMOS chip and interface to the switch matrices (SW). Only a
portion of the logic array and switch matrices are shown[66]
Figure 25. Diagram of graphene interface
Fig. 24 and Fig. 25 shows as the graphene based FPGA
test set up and the interface of graphene. Rajsaktish
Sankaranarayanan et al.[67] proposed a single VDD
sub-threshold FPGA and mapped a benchmark circu it
application to it and analyze the resulting fabric from
various standpoints. The constituent blocks functionally
work down to 110mV and the ISCAS benchmark mapped
onto the fabric has a mini-mum energy point around 200mV
while consuming 8pJ/operation. These results serve as the
foundation to further investigate energy efficiency in the
context of sub-threshold operation and identify limits of
scale, impact of design styles and achievable performance.
5. Conclusions and Future Work
Due to the dramatic increase in power conscious
applications and tighter power budgets, there is a necessity
of low power consumption systems. The use of FPGA
technology in low-power applications is increasing
now-a-days, which makes achieving low power systems an
increasingly important challenge. FPGAs have been
adopted widely in recent years due to advanced technology
that lowered the unit price, but the reduction in price have
come at the cost of higher power due to higher transistor
leakage. Various FPGA technologies have significantly
different power profiles, and these differences can have a
profound impact on the overall system design and power
budget. Power consumption in FPGAs has become a
primary concern for FPGA select ion as previously more
focus was on speed and making device more compact. But
due to regressive use of mobile and portable devices human
beings indirectly consume power from the nature as we are
utilizing the power in the devices through natural resources
like wind, water and other natural resources. According to
Moore’s law, the device size reduces half of its present size
in every 1.5 years. With reduced size, system will be faster
and compact, but high end devices require lots of battery
and natural power to run. So there is a need to focus on
Power savings and to develop more refined and more
optimize devices which can work on low power.
This paper is focused on Device, Circuit & Architectural
Techniques for ultra-low power FPGA design. We
discussed various power models for accurately computing
the static and dynamic power both. We explore a strong
review of various power reduction techniques and finds out
the best technique for static and dynamic power. The
techniques used for static power reduction reduces power
upto 60-90% and dynamic power reduction techniques
reduces power upto 30-50%. In static power reduction,
dual-VT FPGA architecture is exp lored and it indicates an
average leakage power savings of upto 64%. In case of
dynamic power, power savings of upto 61.6% can be
achieved using LOPASS Technique[68] and upto 30% and
50% with clock gating and Glitch reduction techniques [69]
respectively. Table 2 and table 3 shows the static &
dynamic power results and various comparisons between
them.
Microelectronics and Solid State Electronics 2013, 2(2A): 1-15 13
Table 2. Static power reduction techniques
S.
No.
Static power reduction
technique
Technology
parameters
Reduction
in static
power (%)
1 Dual threshold transistor
stacking[ 55] 90 nm
22.09
2 Selection of polarities for logic
signals in FPGA[63] 90 nm 30
3 Fine-grained VDD[60] 90nm 86/95
4 Dual-threshold FPGA routing
design[56] 90nm 28.83
5 Input vector reordering[57] 90 nm 50.3
6 FPGA Routing
Multiplexers[61] 22 nm 20%
7 CLB- Clustering[58] 90 nm 50
8 Power gating[62] 45 nm 40
9 Carbon Nanotube SRAM
Design[50-54] 90-150 nm 45
10 Subthreshold FPGAs[65- 67] 90-180 nm 54
Table 3. Dynamic Power reduction techniques
S.
No.
Dynamic power reduction
technique
Technology
parameters
Reduction in
dynamic
power (%)
1 Programmable FPGA
routing circuitry[ 63] 90 nm 28-31
2 Clock gating[64] 90 nm 50
3 Programmability of
VDD[59] 90 nm 47.61
4 LOPASS Technique[68] 90nm 61.6
5 Glitch reduction
techniques[69] 90nm 30
6 Guarded evaluation[70] 45nm, 90 nm 32, 28
The work till now on reduction of power is qu ite
impressive but it is not upto the mark if the devices are used
with reduced size or for high end applications. So our prime
focus must be to reduce the power. In current and future
research work which is focused on high level design flows,
multi-core arch itectures, advanced applications in network
processing, signal processing, and embedded systems, the
power utilization is extreme. So the power can be reduced
in steps from device level to system level. At initial stage,
low power devices like Fin-FET, double gate, Tunneling
FET can be used to make circu its. Power reduction
techniques can be applied on the circuit which can be used
in FPGA architecture. Then on FPGA architecture, the RTL
level and CAD level power reduction techniques can be
imposed which will reduce overall power of the system.
Currently FPGA IC is fabricated using CMOS technology
but the research is going on to fabrication of the FPGA v ia
Fin-FET, Tunneling-FET MOS, and Multi-Gate FET
devices. The devices would be developed which can work
on low source power and also with low leakage current. The
objective must be focused on power reduction techniques
and the future challenges which can come across while
implementing the techniques on FPGA.
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